2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 * Steven Scholz, steven.scholz@imc-berlin.de
7 * SPDX-License-Identifier: GPL-2.0+
11 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
12 * DS1374 Real Time Clock (RTC).
22 #if defined(CONFIG_CMD_DATE)
24 /*---------------------------------------------------------------------*/
29 #define DEBUGR(fmt,args...) printf(fmt ,##args)
31 #define DEBUGR(fmt,args...)
33 /*---------------------------------------------------------------------*/
35 #ifndef CONFIG_SYS_I2C_RTC_ADDR
36 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
39 #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
40 # error The DS1374 is specified up to 400kHz in fast mode!
44 * RTC register addresses
46 #define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
47 #define RTC_TOD_CNT_BYTE1_ADDR 0x01
48 #define RTC_TOD_CNT_BYTE2_ADDR 0x02
49 #define RTC_TOD_CNT_BYTE3_ADDR 0x03
51 #define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
52 #define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
53 #define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
55 #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
56 #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
57 #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
59 #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
60 #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
61 #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
62 #define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
63 #define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
64 #define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
65 #define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
66 #define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
68 #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
69 #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
71 const char RtcTodAddr
[] = {
72 RTC_TOD_CNT_BYTE0_ADDR
,
73 RTC_TOD_CNT_BYTE1_ADDR
,
74 RTC_TOD_CNT_BYTE2_ADDR
,
75 RTC_TOD_CNT_BYTE3_ADDR
78 static uchar
rtc_read (uchar reg
);
79 static void rtc_write(uchar reg
, uchar val
, bool set
);
80 static void rtc_write_raw (uchar reg
, uchar val
);
83 * Get the current time from the RTC
85 int rtc_get (struct rtc_time
*tm
){
87 unsigned long time1
, time2
;
93 * Since the reads are being performed one byte at a time,
94 * there is a chance that a carry will occur during the read.
95 * To detect this, 2 reads are performed and compared.
102 tmp
= rtc_read(RtcTodAddr
[i
]);
103 time1
= (time1
<< 8) | (tmp
& 0xff);
109 tmp
= rtc_read(RtcTodAddr
[i
]);
110 time2
= (time2
<< 8) | (tmp
& 0xff);
112 } while ((time1
!= time2
) && limit
--);
114 if (time1
!= time2
) {
115 printf("can't get consistent time from rtc chip\n");
119 DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1
);
121 rtc_to_tm(time1
, tm
); /* To Gregorian Date */
123 if (rtc_read(RTC_SR_ADDR
) & RTC_SR_BIT_OSF
) {
124 printf ("### Warning: RTC oscillator has stopped\n");
128 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
129 tm
->tm_year
, tm
->tm_mon
, tm
->tm_mday
, tm
->tm_wday
,
130 tm
->tm_hour
, tm
->tm_min
, tm
->tm_sec
);
138 int rtc_set (struct rtc_time
*tmp
){
143 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
144 tmp
->tm_year
, tmp
->tm_mon
, tmp
->tm_mday
, tmp
->tm_wday
,
145 tmp
->tm_hour
, tmp
->tm_min
, tmp
->tm_sec
);
147 if (tmp
->tm_year
< 1970 || tmp
->tm_year
> 2069)
148 printf("WARNING: year should be between 1970 and 2069!\n");
150 time
= rtc_mktime(tmp
);
152 DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time
, time
);
154 /* write to RTC_TOD_CNT_BYTEn_ADDR */
155 for (i
= 0; i
<= 3; i
++) {
156 rtc_write_raw(RtcTodAddr
[i
], (unsigned char)(time
& 0xff));
161 rtc_write(RTC_CTL_ADDR
, RTC_CTL_BIT_EN_OSC
, false);
167 * Reset the RTC. We setting the date back to 1970-01-01.
168 * We also enable the oscillator output on the SQW/OUT pin and program
169 * it for 32,768 Hz output. Note that according to the datasheet, turning
170 * on the square wave output increases the current drain on the backup
171 * battery to something between 480nA and 800nA.
173 void rtc_reset (void){
177 /* clear status flags */
178 rtc_write(RTC_SR_ADDR
, (RTC_SR_BIT_AF
|RTC_SR_BIT_OSF
), false); /* clearing OSF and AF */
180 /* Initialise DS1374 oriented to MPC8349E-ADS */
181 rtc_write (RTC_CTL_ADDR
, (RTC_CTL_BIT_EN_OSC
183 |RTC_CTL_BIT_AIE
), false);/* start osc, disable WACE, clear AIE
185 rtc_write (RTC_CTL_ADDR
, (RTC_CTL_BIT_WD_ALM
189 |RTC_CTL_BIT_BBSQW
), true);/* disable WD/ALM, WDSTR set to INT-pin,
190 set BBSQW and SQW to 32k
201 printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
202 tmp
.tm_year
, tmp
.tm_mon
, tmp
.tm_mday
,
203 tmp
.tm_hour
, tmp
.tm_min
, tmp
.tm_sec
);
205 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR
, 0xAC, true);
206 rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR
, 0xDE, true);
207 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR
, 0xAD, true);
213 static uchar
rtc_read (uchar reg
)
215 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR
, reg
));
218 static void rtc_write(uchar reg
, uchar val
, bool set
)
221 val
|= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR
, reg
);
222 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR
, reg
, val
);
224 val
= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR
, reg
) & ~val
;
225 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR
, reg
, val
);
229 static void rtc_write_raw (uchar reg
, uchar val
)
231 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR
, reg
, val
);