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hpsa: simplify update scsi devices
[people/ms/linux.git] / drivers / scsi / hpsa.c
1 /*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/fs.h>
28 #include <linux/timer.h>
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
31 #include <linux/compat.h>
32 #include <linux/blktrace_api.h>
33 #include <linux/uaccess.h>
34 #include <linux/io.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/completion.h>
37 #include <linux/moduleparam.h>
38 #include <scsi/scsi.h>
39 #include <scsi/scsi_cmnd.h>
40 #include <scsi/scsi_device.h>
41 #include <scsi/scsi_host.h>
42 #include <scsi/scsi_tcq.h>
43 #include <scsi/scsi_eh.h>
44 #include <scsi/scsi_dbg.h>
45 #include <linux/cciss_ioctl.h>
46 #include <linux/string.h>
47 #include <linux/bitmap.h>
48 #include <linux/atomic.h>
49 #include <linux/jiffies.h>
50 #include <linux/percpu-defs.h>
51 #include <linux/percpu.h>
52 #include <asm/unaligned.h>
53 #include <asm/div64.h>
54 #include "hpsa_cmd.h"
55 #include "hpsa.h"
56
57 /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
58 #define HPSA_DRIVER_VERSION "3.4.10-0"
59 #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
60 #define HPSA "hpsa"
61
62 /* How long to wait for CISS doorbell communication */
63 #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64 #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65 #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66 #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
67 #define MAX_IOCTL_CONFIG_WAIT 1000
68
69 /*define how many times we will try a command because of bus resets */
70 #define MAX_CMD_RETRIES 3
71
72 /* Embedded module documentation macros - see modules.h */
73 MODULE_AUTHOR("Hewlett-Packard Company");
74 MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76 MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77 MODULE_VERSION(HPSA_DRIVER_VERSION);
78 MODULE_LICENSE("GPL");
79
80 static int hpsa_allow_any;
81 module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82 MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
84 static int hpsa_simple_mode;
85 module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86 MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
88
89 /* define the PCI info for the cards we can control */
90 static const struct pci_device_id hpsa_pci_device_id[] = {
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
144 {0,}
145 };
146
147 MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149 /* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153 static struct board_type products[] = {
154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
183 {0x21C4103C, "Smart Array", &SA5_access},
184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
188 {0x21C9103C, "Smart Array", &SA5_access},
189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
193 {0x21CE103C, "Smart HBA", &SA5_access},
194 {0x05809005, "SmartHBA-SA", &SA5_access},
195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206 };
207
208 #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209 static const struct scsi_cmnd hpsa_cmd_busy;
210 #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211 static const struct scsi_cmnd hpsa_cmd_idle;
212 static int number_of_controllers;
213
214 static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215 static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
216 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
217
218 #ifdef CONFIG_COMPAT
219 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
221 #endif
222
223 static void cmd_free(struct ctlr_info *h, struct CommandList *c);
224 static struct CommandList *cmd_alloc(struct ctlr_info *h);
225 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
228 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
230 int cmd_type);
231 static void hpsa_free_cmd_pool(struct ctlr_info *h);
232 #define VPD_PAGE (1 << 8)
233 #define HPSA_SIMPLE_ERROR_BITS 0x03
234
235 static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
236 static void hpsa_scan_start(struct Scsi_Host *);
237 static int hpsa_scan_finished(struct Scsi_Host *sh,
238 unsigned long elapsed_time);
239 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
240
241 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
242 static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
243 static int hpsa_slave_alloc(struct scsi_device *sdev);
244 static int hpsa_slave_configure(struct scsi_device *sdev);
245 static void hpsa_slave_destroy(struct scsi_device *sdev);
246
247 static void hpsa_update_scsi_devices(struct ctlr_info *h);
248 static int check_for_unit_attention(struct ctlr_info *h,
249 struct CommandList *c);
250 static void check_ioctl_unit_attention(struct ctlr_info *h,
251 struct CommandList *c);
252 /* performant mode helper functions */
253 static void calc_bucket_map(int *bucket, int num_buckets,
254 int nsgs, int min_blocks, u32 *bucket_map);
255 static void hpsa_free_performant_mode(struct ctlr_info *h);
256 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
257 static inline u32 next_command(struct ctlr_info *h, u8 q);
258 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
259 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
260 u64 *cfg_offset);
261 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
262 unsigned long *memory_bar);
263 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
264 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
265 int wait_for_ready);
266 static inline void finish_cmd(struct CommandList *c);
267 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
268 #define BOARD_NOT_READY 0
269 #define BOARD_READY 1
270 static void hpsa_drain_accel_commands(struct ctlr_info *h);
271 static void hpsa_flush_cache(struct ctlr_info *h);
272 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
273 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
274 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
275 static void hpsa_command_resubmit_worker(struct work_struct *work);
276 static u32 lockup_detected(struct ctlr_info *h);
277 static int detect_controller_lockup(struct ctlr_info *h);
278 static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
279
280 static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
281 {
282 unsigned long *priv = shost_priv(sdev->host);
283 return (struct ctlr_info *) *priv;
284 }
285
286 static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
287 {
288 unsigned long *priv = shost_priv(sh);
289 return (struct ctlr_info *) *priv;
290 }
291
292 static inline bool hpsa_is_cmd_idle(struct CommandList *c)
293 {
294 return c->scsi_cmd == SCSI_CMD_IDLE;
295 }
296
297 static inline bool hpsa_is_pending_event(struct CommandList *c)
298 {
299 return c->abort_pending || c->reset_pending;
300 }
301
302 /* extract sense key, asc, and ascq from sense data. -1 means invalid. */
303 static void decode_sense_data(const u8 *sense_data, int sense_data_len,
304 u8 *sense_key, u8 *asc, u8 *ascq)
305 {
306 struct scsi_sense_hdr sshdr;
307 bool rc;
308
309 *sense_key = -1;
310 *asc = -1;
311 *ascq = -1;
312
313 if (sense_data_len < 1)
314 return;
315
316 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
317 if (rc) {
318 *sense_key = sshdr.sense_key;
319 *asc = sshdr.asc;
320 *ascq = sshdr.ascq;
321 }
322 }
323
324 static int check_for_unit_attention(struct ctlr_info *h,
325 struct CommandList *c)
326 {
327 u8 sense_key, asc, ascq;
328 int sense_len;
329
330 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
331 sense_len = sizeof(c->err_info->SenseInfo);
332 else
333 sense_len = c->err_info->SenseLen;
334
335 decode_sense_data(c->err_info->SenseInfo, sense_len,
336 &sense_key, &asc, &ascq);
337 if (sense_key != UNIT_ATTENTION || asc == 0xff)
338 return 0;
339
340 switch (asc) {
341 case STATE_CHANGED:
342 dev_warn(&h->pdev->dev,
343 "%s: a state change detected, command retried\n",
344 h->devname);
345 break;
346 case LUN_FAILED:
347 dev_warn(&h->pdev->dev,
348 "%s: LUN failure detected\n", h->devname);
349 break;
350 case REPORT_LUNS_CHANGED:
351 dev_warn(&h->pdev->dev,
352 "%s: report LUN data changed\n", h->devname);
353 /*
354 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
355 * target (array) devices.
356 */
357 break;
358 case POWER_OR_RESET:
359 dev_warn(&h->pdev->dev,
360 "%s: a power on or device reset detected\n",
361 h->devname);
362 break;
363 case UNIT_ATTENTION_CLEARED:
364 dev_warn(&h->pdev->dev,
365 "%s: unit attention cleared by another initiator\n",
366 h->devname);
367 break;
368 default:
369 dev_warn(&h->pdev->dev,
370 "%s: unknown unit attention detected\n",
371 h->devname);
372 break;
373 }
374 return 1;
375 }
376
377 static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
378 {
379 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
380 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
381 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
382 return 0;
383 dev_warn(&h->pdev->dev, HPSA "device busy");
384 return 1;
385 }
386
387 static u32 lockup_detected(struct ctlr_info *h);
388 static ssize_t host_show_lockup_detected(struct device *dev,
389 struct device_attribute *attr, char *buf)
390 {
391 int ld;
392 struct ctlr_info *h;
393 struct Scsi_Host *shost = class_to_shost(dev);
394
395 h = shost_to_hba(shost);
396 ld = lockup_detected(h);
397
398 return sprintf(buf, "ld=%d\n", ld);
399 }
400
401 static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
402 struct device_attribute *attr,
403 const char *buf, size_t count)
404 {
405 int status, len;
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408 char tmpbuf[10];
409
410 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
411 return -EACCES;
412 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
413 strncpy(tmpbuf, buf, len);
414 tmpbuf[len] = '\0';
415 if (sscanf(tmpbuf, "%d", &status) != 1)
416 return -EINVAL;
417 h = shost_to_hba(shost);
418 h->acciopath_status = !!status;
419 dev_warn(&h->pdev->dev,
420 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
421 h->acciopath_status ? "enabled" : "disabled");
422 return count;
423 }
424
425 static ssize_t host_store_raid_offload_debug(struct device *dev,
426 struct device_attribute *attr,
427 const char *buf, size_t count)
428 {
429 int debug_level, len;
430 struct ctlr_info *h;
431 struct Scsi_Host *shost = class_to_shost(dev);
432 char tmpbuf[10];
433
434 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
435 return -EACCES;
436 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
437 strncpy(tmpbuf, buf, len);
438 tmpbuf[len] = '\0';
439 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
440 return -EINVAL;
441 if (debug_level < 0)
442 debug_level = 0;
443 h = shost_to_hba(shost);
444 h->raid_offload_debug = debug_level;
445 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
446 h->raid_offload_debug);
447 return count;
448 }
449
450 static ssize_t host_store_rescan(struct device *dev,
451 struct device_attribute *attr,
452 const char *buf, size_t count)
453 {
454 struct ctlr_info *h;
455 struct Scsi_Host *shost = class_to_shost(dev);
456 h = shost_to_hba(shost);
457 hpsa_scan_start(h->scsi_host);
458 return count;
459 }
460
461 static ssize_t host_show_firmware_revision(struct device *dev,
462 struct device_attribute *attr, char *buf)
463 {
464 struct ctlr_info *h;
465 struct Scsi_Host *shost = class_to_shost(dev);
466 unsigned char *fwrev;
467
468 h = shost_to_hba(shost);
469 if (!h->hba_inquiry_data)
470 return 0;
471 fwrev = &h->hba_inquiry_data[32];
472 return snprintf(buf, 20, "%c%c%c%c\n",
473 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
474 }
475
476 static ssize_t host_show_commands_outstanding(struct device *dev,
477 struct device_attribute *attr, char *buf)
478 {
479 struct Scsi_Host *shost = class_to_shost(dev);
480 struct ctlr_info *h = shost_to_hba(shost);
481
482 return snprintf(buf, 20, "%d\n",
483 atomic_read(&h->commands_outstanding));
484 }
485
486 static ssize_t host_show_transport_mode(struct device *dev,
487 struct device_attribute *attr, char *buf)
488 {
489 struct ctlr_info *h;
490 struct Scsi_Host *shost = class_to_shost(dev);
491
492 h = shost_to_hba(shost);
493 return snprintf(buf, 20, "%s\n",
494 h->transMethod & CFGTBL_Trans_Performant ?
495 "performant" : "simple");
496 }
497
498 static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
499 struct device_attribute *attr, char *buf)
500 {
501 struct ctlr_info *h;
502 struct Scsi_Host *shost = class_to_shost(dev);
503
504 h = shost_to_hba(shost);
505 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
506 (h->acciopath_status == 1) ? "enabled" : "disabled");
507 }
508
509 /* List of controllers which cannot be hard reset on kexec with reset_devices */
510 static u32 unresettable_controller[] = {
511 0x324a103C, /* Smart Array P712m */
512 0x324b103C, /* Smart Array P711m */
513 0x3223103C, /* Smart Array P800 */
514 0x3234103C, /* Smart Array P400 */
515 0x3235103C, /* Smart Array P400i */
516 0x3211103C, /* Smart Array E200i */
517 0x3212103C, /* Smart Array E200 */
518 0x3213103C, /* Smart Array E200i */
519 0x3214103C, /* Smart Array E200i */
520 0x3215103C, /* Smart Array E200i */
521 0x3237103C, /* Smart Array E500 */
522 0x323D103C, /* Smart Array P700m */
523 0x40800E11, /* Smart Array 5i */
524 0x409C0E11, /* Smart Array 6400 */
525 0x409D0E11, /* Smart Array 6400 EM */
526 0x40700E11, /* Smart Array 5300 */
527 0x40820E11, /* Smart Array 532 */
528 0x40830E11, /* Smart Array 5312 */
529 0x409A0E11, /* Smart Array 641 */
530 0x409B0E11, /* Smart Array 642 */
531 0x40910E11, /* Smart Array 6i */
532 };
533
534 /* List of controllers which cannot even be soft reset */
535 static u32 soft_unresettable_controller[] = {
536 0x40800E11, /* Smart Array 5i */
537 0x40700E11, /* Smart Array 5300 */
538 0x40820E11, /* Smart Array 532 */
539 0x40830E11, /* Smart Array 5312 */
540 0x409A0E11, /* Smart Array 641 */
541 0x409B0E11, /* Smart Array 642 */
542 0x40910E11, /* Smart Array 6i */
543 /* Exclude 640x boards. These are two pci devices in one slot
544 * which share a battery backed cache module. One controls the
545 * cache, the other accesses the cache through the one that controls
546 * it. If we reset the one controlling the cache, the other will
547 * likely not be happy. Just forbid resetting this conjoined mess.
548 * The 640x isn't really supported by hpsa anyway.
549 */
550 0x409C0E11, /* Smart Array 6400 */
551 0x409D0E11, /* Smart Array 6400 EM */
552 };
553
554 static u32 needs_abort_tags_swizzled[] = {
555 0x323D103C, /* Smart Array P700m */
556 0x324a103C, /* Smart Array P712m */
557 0x324b103C, /* SmartArray P711m */
558 };
559
560 static int board_id_in_array(u32 a[], int nelems, u32 board_id)
561 {
562 int i;
563
564 for (i = 0; i < nelems; i++)
565 if (a[i] == board_id)
566 return 1;
567 return 0;
568 }
569
570 static int ctlr_is_hard_resettable(u32 board_id)
571 {
572 return !board_id_in_array(unresettable_controller,
573 ARRAY_SIZE(unresettable_controller), board_id);
574 }
575
576 static int ctlr_is_soft_resettable(u32 board_id)
577 {
578 return !board_id_in_array(soft_unresettable_controller,
579 ARRAY_SIZE(soft_unresettable_controller), board_id);
580 }
581
582 static int ctlr_is_resettable(u32 board_id)
583 {
584 return ctlr_is_hard_resettable(board_id) ||
585 ctlr_is_soft_resettable(board_id);
586 }
587
588 static int ctlr_needs_abort_tags_swizzled(u32 board_id)
589 {
590 return board_id_in_array(needs_abort_tags_swizzled,
591 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
592 }
593
594 static ssize_t host_show_resettable(struct device *dev,
595 struct device_attribute *attr, char *buf)
596 {
597 struct ctlr_info *h;
598 struct Scsi_Host *shost = class_to_shost(dev);
599
600 h = shost_to_hba(shost);
601 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
602 }
603
604 static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
605 {
606 return (scsi3addr[3] & 0xC0) == 0x40;
607 }
608
609 static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
610 "1(+0)ADM", "UNKNOWN"
611 };
612 #define HPSA_RAID_0 0
613 #define HPSA_RAID_4 1
614 #define HPSA_RAID_1 2 /* also used for RAID 10 */
615 #define HPSA_RAID_5 3 /* also used for RAID 50 */
616 #define HPSA_RAID_51 4
617 #define HPSA_RAID_6 5 /* also used for RAID 60 */
618 #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
619 #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
620
621 static ssize_t raid_level_show(struct device *dev,
622 struct device_attribute *attr, char *buf)
623 {
624 ssize_t l = 0;
625 unsigned char rlevel;
626 struct ctlr_info *h;
627 struct scsi_device *sdev;
628 struct hpsa_scsi_dev_t *hdev;
629 unsigned long flags;
630
631 sdev = to_scsi_device(dev);
632 h = sdev_to_hba(sdev);
633 spin_lock_irqsave(&h->lock, flags);
634 hdev = sdev->hostdata;
635 if (!hdev) {
636 spin_unlock_irqrestore(&h->lock, flags);
637 return -ENODEV;
638 }
639
640 /* Is this even a logical drive? */
641 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
642 spin_unlock_irqrestore(&h->lock, flags);
643 l = snprintf(buf, PAGE_SIZE, "N/A\n");
644 return l;
645 }
646
647 rlevel = hdev->raid_level;
648 spin_unlock_irqrestore(&h->lock, flags);
649 if (rlevel > RAID_UNKNOWN)
650 rlevel = RAID_UNKNOWN;
651 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
652 return l;
653 }
654
655 static ssize_t lunid_show(struct device *dev,
656 struct device_attribute *attr, char *buf)
657 {
658 struct ctlr_info *h;
659 struct scsi_device *sdev;
660 struct hpsa_scsi_dev_t *hdev;
661 unsigned long flags;
662 unsigned char lunid[8];
663
664 sdev = to_scsi_device(dev);
665 h = sdev_to_hba(sdev);
666 spin_lock_irqsave(&h->lock, flags);
667 hdev = sdev->hostdata;
668 if (!hdev) {
669 spin_unlock_irqrestore(&h->lock, flags);
670 return -ENODEV;
671 }
672 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
673 spin_unlock_irqrestore(&h->lock, flags);
674 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
675 lunid[0], lunid[1], lunid[2], lunid[3],
676 lunid[4], lunid[5], lunid[6], lunid[7]);
677 }
678
679 static ssize_t unique_id_show(struct device *dev,
680 struct device_attribute *attr, char *buf)
681 {
682 struct ctlr_info *h;
683 struct scsi_device *sdev;
684 struct hpsa_scsi_dev_t *hdev;
685 unsigned long flags;
686 unsigned char sn[16];
687
688 sdev = to_scsi_device(dev);
689 h = sdev_to_hba(sdev);
690 spin_lock_irqsave(&h->lock, flags);
691 hdev = sdev->hostdata;
692 if (!hdev) {
693 spin_unlock_irqrestore(&h->lock, flags);
694 return -ENODEV;
695 }
696 memcpy(sn, hdev->device_id, sizeof(sn));
697 spin_unlock_irqrestore(&h->lock, flags);
698 return snprintf(buf, 16 * 2 + 2,
699 "%02X%02X%02X%02X%02X%02X%02X%02X"
700 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
701 sn[0], sn[1], sn[2], sn[3],
702 sn[4], sn[5], sn[6], sn[7],
703 sn[8], sn[9], sn[10], sn[11],
704 sn[12], sn[13], sn[14], sn[15]);
705 }
706
707 static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
708 struct device_attribute *attr, char *buf)
709 {
710 struct ctlr_info *h;
711 struct scsi_device *sdev;
712 struct hpsa_scsi_dev_t *hdev;
713 unsigned long flags;
714 int offload_enabled;
715
716 sdev = to_scsi_device(dev);
717 h = sdev_to_hba(sdev);
718 spin_lock_irqsave(&h->lock, flags);
719 hdev = sdev->hostdata;
720 if (!hdev) {
721 spin_unlock_irqrestore(&h->lock, flags);
722 return -ENODEV;
723 }
724 offload_enabled = hdev->offload_enabled;
725 spin_unlock_irqrestore(&h->lock, flags);
726 return snprintf(buf, 20, "%d\n", offload_enabled);
727 }
728
729 #define MAX_PATHS 8
730 #define PATH_STRING_LEN 50
731
732 static ssize_t path_info_show(struct device *dev,
733 struct device_attribute *attr, char *buf)
734 {
735 struct ctlr_info *h;
736 struct scsi_device *sdev;
737 struct hpsa_scsi_dev_t *hdev;
738 unsigned long flags;
739 int i;
740 int output_len = 0;
741 u8 box;
742 u8 bay;
743 u8 path_map_index = 0;
744 char *active;
745 unsigned char phys_connector[2];
746 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
747
748 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
749 sdev = to_scsi_device(dev);
750 h = sdev_to_hba(sdev);
751 spin_lock_irqsave(&h->devlock, flags);
752 hdev = sdev->hostdata;
753 if (!hdev) {
754 spin_unlock_irqrestore(&h->devlock, flags);
755 return -ENODEV;
756 }
757
758 bay = hdev->bay;
759 for (i = 0; i < MAX_PATHS; i++) {
760 path_map_index = 1<<i;
761 if (i == hdev->active_path_index)
762 active = "Active";
763 else if (hdev->path_map & path_map_index)
764 active = "Inactive";
765 else
766 continue;
767
768 output_len = snprintf(path[i],
769 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
770 h->scsi_host->host_no,
771 hdev->bus, hdev->target, hdev->lun,
772 scsi_device_type(hdev->devtype));
773
774 if (is_ext_target(h, hdev) ||
775 (hdev->devtype == TYPE_RAID) ||
776 is_logical_dev_addr_mode(hdev->scsi3addr)) {
777 output_len += snprintf(path[i] + output_len,
778 PATH_STRING_LEN, "%s\n",
779 active);
780 continue;
781 }
782
783 box = hdev->box[i];
784 memcpy(&phys_connector, &hdev->phys_connector[i],
785 sizeof(phys_connector));
786 if (phys_connector[0] < '0')
787 phys_connector[0] = '0';
788 if (phys_connector[1] < '0')
789 phys_connector[1] = '0';
790 if (hdev->phys_connector[i] > 0)
791 output_len += snprintf(path[i] + output_len,
792 PATH_STRING_LEN,
793 "PORT: %.2s ",
794 phys_connector);
795 if (hdev->devtype == TYPE_DISK && hdev->expose_device) {
796 if (box == 0 || box == 0xFF) {
797 output_len += snprintf(path[i] + output_len,
798 PATH_STRING_LEN,
799 "BAY: %hhu %s\n",
800 bay, active);
801 } else {
802 output_len += snprintf(path[i] + output_len,
803 PATH_STRING_LEN,
804 "BOX: %hhu BAY: %hhu %s\n",
805 box, bay, active);
806 }
807 } else if (box != 0 && box != 0xFF) {
808 output_len += snprintf(path[i] + output_len,
809 PATH_STRING_LEN, "BOX: %hhu %s\n",
810 box, active);
811 } else
812 output_len += snprintf(path[i] + output_len,
813 PATH_STRING_LEN, "%s\n", active);
814 }
815
816 spin_unlock_irqrestore(&h->devlock, flags);
817 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
818 path[0], path[1], path[2], path[3],
819 path[4], path[5], path[6], path[7]);
820 }
821
822 static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
823 static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
824 static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
825 static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
826 static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
827 host_show_hp_ssd_smart_path_enabled, NULL);
828 static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
829 static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
830 host_show_hp_ssd_smart_path_status,
831 host_store_hp_ssd_smart_path_status);
832 static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
833 host_store_raid_offload_debug);
834 static DEVICE_ATTR(firmware_revision, S_IRUGO,
835 host_show_firmware_revision, NULL);
836 static DEVICE_ATTR(commands_outstanding, S_IRUGO,
837 host_show_commands_outstanding, NULL);
838 static DEVICE_ATTR(transport_mode, S_IRUGO,
839 host_show_transport_mode, NULL);
840 static DEVICE_ATTR(resettable, S_IRUGO,
841 host_show_resettable, NULL);
842 static DEVICE_ATTR(lockup_detected, S_IRUGO,
843 host_show_lockup_detected, NULL);
844
845 static struct device_attribute *hpsa_sdev_attrs[] = {
846 &dev_attr_raid_level,
847 &dev_attr_lunid,
848 &dev_attr_unique_id,
849 &dev_attr_hp_ssd_smart_path_enabled,
850 &dev_attr_path_info,
851 &dev_attr_lockup_detected,
852 NULL,
853 };
854
855 static struct device_attribute *hpsa_shost_attrs[] = {
856 &dev_attr_rescan,
857 &dev_attr_firmware_revision,
858 &dev_attr_commands_outstanding,
859 &dev_attr_transport_mode,
860 &dev_attr_resettable,
861 &dev_attr_hp_ssd_smart_path_status,
862 &dev_attr_raid_offload_debug,
863 NULL,
864 };
865
866 #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
867 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
868
869 static struct scsi_host_template hpsa_driver_template = {
870 .module = THIS_MODULE,
871 .name = HPSA,
872 .proc_name = HPSA,
873 .queuecommand = hpsa_scsi_queue_command,
874 .scan_start = hpsa_scan_start,
875 .scan_finished = hpsa_scan_finished,
876 .change_queue_depth = hpsa_change_queue_depth,
877 .this_id = -1,
878 .use_clustering = ENABLE_CLUSTERING,
879 .eh_abort_handler = hpsa_eh_abort_handler,
880 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
881 .ioctl = hpsa_ioctl,
882 .slave_alloc = hpsa_slave_alloc,
883 .slave_configure = hpsa_slave_configure,
884 .slave_destroy = hpsa_slave_destroy,
885 #ifdef CONFIG_COMPAT
886 .compat_ioctl = hpsa_compat_ioctl,
887 #endif
888 .sdev_attrs = hpsa_sdev_attrs,
889 .shost_attrs = hpsa_shost_attrs,
890 .max_sectors = 8192,
891 .no_write_same = 1,
892 };
893
894 static inline u32 next_command(struct ctlr_info *h, u8 q)
895 {
896 u32 a;
897 struct reply_queue_buffer *rq = &h->reply_queue[q];
898
899 if (h->transMethod & CFGTBL_Trans_io_accel1)
900 return h->access.command_completed(h, q);
901
902 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
903 return h->access.command_completed(h, q);
904
905 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
906 a = rq->head[rq->current_entry];
907 rq->current_entry++;
908 atomic_dec(&h->commands_outstanding);
909 } else {
910 a = FIFO_EMPTY;
911 }
912 /* Check for wraparound */
913 if (rq->current_entry == h->max_commands) {
914 rq->current_entry = 0;
915 rq->wraparound ^= 1;
916 }
917 return a;
918 }
919
920 /*
921 * There are some special bits in the bus address of the
922 * command that we have to set for the controller to know
923 * how to process the command:
924 *
925 * Normal performant mode:
926 * bit 0: 1 means performant mode, 0 means simple mode.
927 * bits 1-3 = block fetch table entry
928 * bits 4-6 = command type (== 0)
929 *
930 * ioaccel1 mode:
931 * bit 0 = "performant mode" bit.
932 * bits 1-3 = block fetch table entry
933 * bits 4-6 = command type (== 110)
934 * (command type is needed because ioaccel1 mode
935 * commands are submitted through the same register as normal
936 * mode commands, so this is how the controller knows whether
937 * the command is normal mode or ioaccel1 mode.)
938 *
939 * ioaccel2 mode:
940 * bit 0 = "performant mode" bit.
941 * bits 1-4 = block fetch table entry (note extra bit)
942 * bits 4-6 = not needed, because ioaccel2 mode has
943 * a separate special register for submitting commands.
944 */
945
946 /*
947 * set_performant_mode: Modify the tag for cciss performant
948 * set bit 0 for pull model, bits 3-1 for block fetch
949 * register number
950 */
951 #define DEFAULT_REPLY_QUEUE (-1)
952 static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
953 int reply_queue)
954 {
955 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
956 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
957 if (unlikely(!h->msix_vector))
958 return;
959 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
960 c->Header.ReplyQueue =
961 raw_smp_processor_id() % h->nreply_queues;
962 else
963 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
964 }
965 }
966
967 static void set_ioaccel1_performant_mode(struct ctlr_info *h,
968 struct CommandList *c,
969 int reply_queue)
970 {
971 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
972
973 /*
974 * Tell the controller to post the reply to the queue for this
975 * processor. This seems to give the best I/O throughput.
976 */
977 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
978 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
979 else
980 cp->ReplyQueue = reply_queue % h->nreply_queues;
981 /*
982 * Set the bits in the address sent down to include:
983 * - performant mode bit (bit 0)
984 * - pull count (bits 1-3)
985 * - command type (bits 4-6)
986 */
987 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
988 IOACCEL1_BUSADDR_CMDTYPE;
989 }
990
991 static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
992 struct CommandList *c,
993 int reply_queue)
994 {
995 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
996 &h->ioaccel2_cmd_pool[c->cmdindex];
997
998 /* Tell the controller to post the reply to the queue for this
999 * processor. This seems to give the best I/O throughput.
1000 */
1001 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1002 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1003 else
1004 cp->reply_queue = reply_queue % h->nreply_queues;
1005 /* Set the bits in the address sent down to include:
1006 * - performant mode bit not used in ioaccel mode 2
1007 * - pull count (bits 0-3)
1008 * - command type isn't needed for ioaccel2
1009 */
1010 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1011 }
1012
1013 static void set_ioaccel2_performant_mode(struct ctlr_info *h,
1014 struct CommandList *c,
1015 int reply_queue)
1016 {
1017 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1018
1019 /*
1020 * Tell the controller to post the reply to the queue for this
1021 * processor. This seems to give the best I/O throughput.
1022 */
1023 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1024 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1025 else
1026 cp->reply_queue = reply_queue % h->nreply_queues;
1027 /*
1028 * Set the bits in the address sent down to include:
1029 * - performant mode bit not used in ioaccel mode 2
1030 * - pull count (bits 0-3)
1031 * - command type isn't needed for ioaccel2
1032 */
1033 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1034 }
1035
1036 static int is_firmware_flash_cmd(u8 *cdb)
1037 {
1038 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1039 }
1040
1041 /*
1042 * During firmware flash, the heartbeat register may not update as frequently
1043 * as it should. So we dial down lockup detection during firmware flash. and
1044 * dial it back up when firmware flash completes.
1045 */
1046 #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1047 #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1048 static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1049 struct CommandList *c)
1050 {
1051 if (!is_firmware_flash_cmd(c->Request.CDB))
1052 return;
1053 atomic_inc(&h->firmware_flash_in_progress);
1054 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1055 }
1056
1057 static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1058 struct CommandList *c)
1059 {
1060 if (is_firmware_flash_cmd(c->Request.CDB) &&
1061 atomic_dec_and_test(&h->firmware_flash_in_progress))
1062 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1063 }
1064
1065 static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1066 struct CommandList *c, int reply_queue)
1067 {
1068 dial_down_lockup_detection_during_fw_flash(h, c);
1069 atomic_inc(&h->commands_outstanding);
1070 switch (c->cmd_type) {
1071 case CMD_IOACCEL1:
1072 set_ioaccel1_performant_mode(h, c, reply_queue);
1073 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
1074 break;
1075 case CMD_IOACCEL2:
1076 set_ioaccel2_performant_mode(h, c, reply_queue);
1077 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1078 break;
1079 case IOACCEL2_TMF:
1080 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1081 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1082 break;
1083 default:
1084 set_performant_mode(h, c, reply_queue);
1085 h->access.submit_command(h, c);
1086 }
1087 }
1088
1089 static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
1090 {
1091 if (unlikely(hpsa_is_pending_event(c)))
1092 return finish_cmd(c);
1093
1094 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1095 }
1096
1097 static inline int is_hba_lunid(unsigned char scsi3addr[])
1098 {
1099 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1100 }
1101
1102 static inline int is_scsi_rev_5(struct ctlr_info *h)
1103 {
1104 if (!h->hba_inquiry_data)
1105 return 0;
1106 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1107 return 1;
1108 return 0;
1109 }
1110
1111 static int hpsa_find_target_lun(struct ctlr_info *h,
1112 unsigned char scsi3addr[], int bus, int *target, int *lun)
1113 {
1114 /* finds an unused bus, target, lun for a new physical device
1115 * assumes h->devlock is held
1116 */
1117 int i, found = 0;
1118 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
1119
1120 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
1121
1122 for (i = 0; i < h->ndevices; i++) {
1123 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
1124 __set_bit(h->dev[i]->target, lun_taken);
1125 }
1126
1127 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1128 if (i < HPSA_MAX_DEVICES) {
1129 /* *bus = 1; */
1130 *target = i;
1131 *lun = 0;
1132 found = 1;
1133 }
1134 return !found;
1135 }
1136
1137 static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1138 struct hpsa_scsi_dev_t *dev, char *description)
1139 {
1140 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1141 return;
1142
1143 dev_printk(level, &h->pdev->dev,
1144 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1145 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1146 description,
1147 scsi_device_type(dev->devtype),
1148 dev->vendor,
1149 dev->model,
1150 dev->raid_level > RAID_UNKNOWN ?
1151 "RAID-?" : raid_label[dev->raid_level],
1152 dev->offload_config ? '+' : '-',
1153 dev->offload_enabled ? '+' : '-',
1154 dev->expose_device);
1155 }
1156
1157 /* Add an entry into h->dev[] array. */
1158 static int hpsa_scsi_add_entry(struct ctlr_info *h,
1159 struct hpsa_scsi_dev_t *device,
1160 struct hpsa_scsi_dev_t *added[], int *nadded)
1161 {
1162 /* assumes h->devlock is held */
1163 int n = h->ndevices;
1164 int i;
1165 unsigned char addr1[8], addr2[8];
1166 struct hpsa_scsi_dev_t *sd;
1167
1168 if (n >= HPSA_MAX_DEVICES) {
1169 dev_err(&h->pdev->dev, "too many devices, some will be "
1170 "inaccessible.\n");
1171 return -1;
1172 }
1173
1174 /* physical devices do not have lun or target assigned until now. */
1175 if (device->lun != -1)
1176 /* Logical device, lun is already assigned. */
1177 goto lun_assigned;
1178
1179 /* If this device a non-zero lun of a multi-lun device
1180 * byte 4 of the 8-byte LUN addr will contain the logical
1181 * unit no, zero otherwise.
1182 */
1183 if (device->scsi3addr[4] == 0) {
1184 /* This is not a non-zero lun of a multi-lun device */
1185 if (hpsa_find_target_lun(h, device->scsi3addr,
1186 device->bus, &device->target, &device->lun) != 0)
1187 return -1;
1188 goto lun_assigned;
1189 }
1190
1191 /* This is a non-zero lun of a multi-lun device.
1192 * Search through our list and find the device which
1193 * has the same 8 byte LUN address, excepting byte 4 and 5.
1194 * Assign the same bus and target for this new LUN.
1195 * Use the logical unit number from the firmware.
1196 */
1197 memcpy(addr1, device->scsi3addr, 8);
1198 addr1[4] = 0;
1199 addr1[5] = 0;
1200 for (i = 0; i < n; i++) {
1201 sd = h->dev[i];
1202 memcpy(addr2, sd->scsi3addr, 8);
1203 addr2[4] = 0;
1204 addr2[5] = 0;
1205 /* differ only in byte 4 and 5? */
1206 if (memcmp(addr1, addr2, 8) == 0) {
1207 device->bus = sd->bus;
1208 device->target = sd->target;
1209 device->lun = device->scsi3addr[4];
1210 break;
1211 }
1212 }
1213 if (device->lun == -1) {
1214 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1215 " suspect firmware bug or unsupported hardware "
1216 "configuration.\n");
1217 return -1;
1218 }
1219
1220 lun_assigned:
1221
1222 h->dev[n] = device;
1223 h->ndevices++;
1224 added[*nadded] = device;
1225 (*nadded)++;
1226 hpsa_show_dev_msg(KERN_INFO, h, device,
1227 device->expose_device ? "added" : "masked");
1228 device->offload_to_be_enabled = device->offload_enabled;
1229 device->offload_enabled = 0;
1230 return 0;
1231 }
1232
1233 /* Update an entry in h->dev[] array. */
1234 static void hpsa_scsi_update_entry(struct ctlr_info *h,
1235 int entry, struct hpsa_scsi_dev_t *new_entry)
1236 {
1237 int offload_enabled;
1238 /* assumes h->devlock is held */
1239 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1240
1241 /* Raid level changed. */
1242 h->dev[entry]->raid_level = new_entry->raid_level;
1243
1244 /* Raid offload parameters changed. Careful about the ordering. */
1245 if (new_entry->offload_config && new_entry->offload_enabled) {
1246 /*
1247 * if drive is newly offload_enabled, we want to copy the
1248 * raid map data first. If previously offload_enabled and
1249 * offload_config were set, raid map data had better be
1250 * the same as it was before. if raid map data is changed
1251 * then it had better be the case that
1252 * h->dev[entry]->offload_enabled is currently 0.
1253 */
1254 h->dev[entry]->raid_map = new_entry->raid_map;
1255 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1256 }
1257 if (new_entry->hba_ioaccel_enabled) {
1258 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1259 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1260 }
1261 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
1262 h->dev[entry]->offload_config = new_entry->offload_config;
1263 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
1264 h->dev[entry]->queue_depth = new_entry->queue_depth;
1265
1266 /*
1267 * We can turn off ioaccel offload now, but need to delay turning
1268 * it on until we can update h->dev[entry]->phys_disk[], but we
1269 * can't do that until all the devices are updated.
1270 */
1271 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1272 if (!new_entry->offload_enabled)
1273 h->dev[entry]->offload_enabled = 0;
1274
1275 offload_enabled = h->dev[entry]->offload_enabled;
1276 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
1277 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
1278 h->dev[entry]->offload_enabled = offload_enabled;
1279 }
1280
1281 /* Replace an entry from h->dev[] array. */
1282 static void hpsa_scsi_replace_entry(struct ctlr_info *h,
1283 int entry, struct hpsa_scsi_dev_t *new_entry,
1284 struct hpsa_scsi_dev_t *added[], int *nadded,
1285 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1286 {
1287 /* assumes h->devlock is held */
1288 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1289 removed[*nremoved] = h->dev[entry];
1290 (*nremoved)++;
1291
1292 /*
1293 * New physical devices won't have target/lun assigned yet
1294 * so we need to preserve the values in the slot we are replacing.
1295 */
1296 if (new_entry->target == -1) {
1297 new_entry->target = h->dev[entry]->target;
1298 new_entry->lun = h->dev[entry]->lun;
1299 }
1300
1301 h->dev[entry] = new_entry;
1302 added[*nadded] = new_entry;
1303 (*nadded)++;
1304 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
1305 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1306 new_entry->offload_enabled = 0;
1307 }
1308
1309 /* Remove an entry from h->dev[] array. */
1310 static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
1311 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1312 {
1313 /* assumes h->devlock is held */
1314 int i;
1315 struct hpsa_scsi_dev_t *sd;
1316
1317 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1318
1319 sd = h->dev[entry];
1320 removed[*nremoved] = h->dev[entry];
1321 (*nremoved)++;
1322
1323 for (i = entry; i < h->ndevices-1; i++)
1324 h->dev[i] = h->dev[i+1];
1325 h->ndevices--;
1326 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
1327 }
1328
1329 #define SCSI3ADDR_EQ(a, b) ( \
1330 (a)[7] == (b)[7] && \
1331 (a)[6] == (b)[6] && \
1332 (a)[5] == (b)[5] && \
1333 (a)[4] == (b)[4] && \
1334 (a)[3] == (b)[3] && \
1335 (a)[2] == (b)[2] && \
1336 (a)[1] == (b)[1] && \
1337 (a)[0] == (b)[0])
1338
1339 static void fixup_botched_add(struct ctlr_info *h,
1340 struct hpsa_scsi_dev_t *added)
1341 {
1342 /* called when scsi_add_device fails in order to re-adjust
1343 * h->dev[] to match the mid layer's view.
1344 */
1345 unsigned long flags;
1346 int i, j;
1347
1348 spin_lock_irqsave(&h->lock, flags);
1349 for (i = 0; i < h->ndevices; i++) {
1350 if (h->dev[i] == added) {
1351 for (j = i; j < h->ndevices-1; j++)
1352 h->dev[j] = h->dev[j+1];
1353 h->ndevices--;
1354 break;
1355 }
1356 }
1357 spin_unlock_irqrestore(&h->lock, flags);
1358 kfree(added);
1359 }
1360
1361 static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1362 struct hpsa_scsi_dev_t *dev2)
1363 {
1364 /* we compare everything except lun and target as these
1365 * are not yet assigned. Compare parts likely
1366 * to differ first
1367 */
1368 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1369 sizeof(dev1->scsi3addr)) != 0)
1370 return 0;
1371 if (memcmp(dev1->device_id, dev2->device_id,
1372 sizeof(dev1->device_id)) != 0)
1373 return 0;
1374 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1375 return 0;
1376 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1377 return 0;
1378 if (dev1->devtype != dev2->devtype)
1379 return 0;
1380 if (dev1->bus != dev2->bus)
1381 return 0;
1382 return 1;
1383 }
1384
1385 static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1386 struct hpsa_scsi_dev_t *dev2)
1387 {
1388 /* Device attributes that can change, but don't mean
1389 * that the device is a different device, nor that the OS
1390 * needs to be told anything about the change.
1391 */
1392 if (dev1->raid_level != dev2->raid_level)
1393 return 1;
1394 if (dev1->offload_config != dev2->offload_config)
1395 return 1;
1396 if (dev1->offload_enabled != dev2->offload_enabled)
1397 return 1;
1398 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1399 if (dev1->queue_depth != dev2->queue_depth)
1400 return 1;
1401 return 0;
1402 }
1403
1404 /* Find needle in haystack. If exact match found, return DEVICE_SAME,
1405 * and return needle location in *index. If scsi3addr matches, but not
1406 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
1407 * location in *index.
1408 * In the case of a minor device attribute change, such as RAID level, just
1409 * return DEVICE_UPDATED, along with the updated device's location in index.
1410 * If needle not found, return DEVICE_NOT_FOUND.
1411 */
1412 static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1413 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1414 int *index)
1415 {
1416 int i;
1417 #define DEVICE_NOT_FOUND 0
1418 #define DEVICE_CHANGED 1
1419 #define DEVICE_SAME 2
1420 #define DEVICE_UPDATED 3
1421 if (needle == NULL)
1422 return DEVICE_NOT_FOUND;
1423
1424 for (i = 0; i < haystack_size; i++) {
1425 if (haystack[i] == NULL) /* previously removed. */
1426 continue;
1427 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1428 *index = i;
1429 if (device_is_the_same(needle, haystack[i])) {
1430 if (device_updated(needle, haystack[i]))
1431 return DEVICE_UPDATED;
1432 return DEVICE_SAME;
1433 } else {
1434 /* Keep offline devices offline */
1435 if (needle->volume_offline)
1436 return DEVICE_NOT_FOUND;
1437 return DEVICE_CHANGED;
1438 }
1439 }
1440 }
1441 *index = -1;
1442 return DEVICE_NOT_FOUND;
1443 }
1444
1445 static void hpsa_monitor_offline_device(struct ctlr_info *h,
1446 unsigned char scsi3addr[])
1447 {
1448 struct offline_device_entry *device;
1449 unsigned long flags;
1450
1451 /* Check to see if device is already on the list */
1452 spin_lock_irqsave(&h->offline_device_lock, flags);
1453 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1454 if (memcmp(device->scsi3addr, scsi3addr,
1455 sizeof(device->scsi3addr)) == 0) {
1456 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1457 return;
1458 }
1459 }
1460 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1461
1462 /* Device is not on the list, add it. */
1463 device = kmalloc(sizeof(*device), GFP_KERNEL);
1464 if (!device) {
1465 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1466 return;
1467 }
1468 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1469 spin_lock_irqsave(&h->offline_device_lock, flags);
1470 list_add_tail(&device->offline_list, &h->offline_device_list);
1471 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1472 }
1473
1474 /* Print a message explaining various offline volume states */
1475 static void hpsa_show_volume_status(struct ctlr_info *h,
1476 struct hpsa_scsi_dev_t *sd)
1477 {
1478 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1479 dev_info(&h->pdev->dev,
1480 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1481 h->scsi_host->host_no,
1482 sd->bus, sd->target, sd->lun);
1483 switch (sd->volume_offline) {
1484 case HPSA_LV_OK:
1485 break;
1486 case HPSA_LV_UNDERGOING_ERASE:
1487 dev_info(&h->pdev->dev,
1488 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1489 h->scsi_host->host_no,
1490 sd->bus, sd->target, sd->lun);
1491 break;
1492 case HPSA_LV_NOT_AVAILABLE:
1493 dev_info(&h->pdev->dev,
1494 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1495 h->scsi_host->host_no,
1496 sd->bus, sd->target, sd->lun);
1497 break;
1498 case HPSA_LV_UNDERGOING_RPI:
1499 dev_info(&h->pdev->dev,
1500 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
1501 h->scsi_host->host_no,
1502 sd->bus, sd->target, sd->lun);
1503 break;
1504 case HPSA_LV_PENDING_RPI:
1505 dev_info(&h->pdev->dev,
1506 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1507 h->scsi_host->host_no,
1508 sd->bus, sd->target, sd->lun);
1509 break;
1510 case HPSA_LV_ENCRYPTED_NO_KEY:
1511 dev_info(&h->pdev->dev,
1512 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1513 h->scsi_host->host_no,
1514 sd->bus, sd->target, sd->lun);
1515 break;
1516 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1517 dev_info(&h->pdev->dev,
1518 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1519 h->scsi_host->host_no,
1520 sd->bus, sd->target, sd->lun);
1521 break;
1522 case HPSA_LV_UNDERGOING_ENCRYPTION:
1523 dev_info(&h->pdev->dev,
1524 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1525 h->scsi_host->host_no,
1526 sd->bus, sd->target, sd->lun);
1527 break;
1528 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1529 dev_info(&h->pdev->dev,
1530 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1531 h->scsi_host->host_no,
1532 sd->bus, sd->target, sd->lun);
1533 break;
1534 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1535 dev_info(&h->pdev->dev,
1536 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1537 h->scsi_host->host_no,
1538 sd->bus, sd->target, sd->lun);
1539 break;
1540 case HPSA_LV_PENDING_ENCRYPTION:
1541 dev_info(&h->pdev->dev,
1542 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1543 h->scsi_host->host_no,
1544 sd->bus, sd->target, sd->lun);
1545 break;
1546 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1547 dev_info(&h->pdev->dev,
1548 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1549 h->scsi_host->host_no,
1550 sd->bus, sd->target, sd->lun);
1551 break;
1552 }
1553 }
1554
1555 /*
1556 * Figure the list of physical drive pointers for a logical drive with
1557 * raid offload configured.
1558 */
1559 static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1560 struct hpsa_scsi_dev_t *dev[], int ndevices,
1561 struct hpsa_scsi_dev_t *logical_drive)
1562 {
1563 struct raid_map_data *map = &logical_drive->raid_map;
1564 struct raid_map_disk_data *dd = &map->data[0];
1565 int i, j;
1566 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1567 le16_to_cpu(map->metadata_disks_per_row);
1568 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1569 le16_to_cpu(map->layout_map_count) *
1570 total_disks_per_row;
1571 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1572 total_disks_per_row;
1573 int qdepth;
1574
1575 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1576 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1577
1578 logical_drive->nphysical_disks = nraid_map_entries;
1579
1580 qdepth = 0;
1581 for (i = 0; i < nraid_map_entries; i++) {
1582 logical_drive->phys_disk[i] = NULL;
1583 if (!logical_drive->offload_config)
1584 continue;
1585 for (j = 0; j < ndevices; j++) {
1586 if (dev[j] == NULL)
1587 continue;
1588 if (dev[j]->devtype != TYPE_DISK)
1589 continue;
1590 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1591 continue;
1592 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1593 continue;
1594
1595 logical_drive->phys_disk[i] = dev[j];
1596 if (i < nphys_disk)
1597 qdepth = min(h->nr_cmds, qdepth +
1598 logical_drive->phys_disk[i]->queue_depth);
1599 break;
1600 }
1601
1602 /*
1603 * This can happen if a physical drive is removed and
1604 * the logical drive is degraded. In that case, the RAID
1605 * map data will refer to a physical disk which isn't actually
1606 * present. And in that case offload_enabled should already
1607 * be 0, but we'll turn it off here just in case
1608 */
1609 if (!logical_drive->phys_disk[i]) {
1610 logical_drive->offload_enabled = 0;
1611 logical_drive->offload_to_be_enabled = 0;
1612 logical_drive->queue_depth = 8;
1613 }
1614 }
1615 if (nraid_map_entries)
1616 /*
1617 * This is correct for reads, too high for full stripe writes,
1618 * way too high for partial stripe writes
1619 */
1620 logical_drive->queue_depth = qdepth;
1621 else
1622 logical_drive->queue_depth = h->nr_cmds;
1623 }
1624
1625 static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1626 struct hpsa_scsi_dev_t *dev[], int ndevices)
1627 {
1628 int i;
1629
1630 for (i = 0; i < ndevices; i++) {
1631 if (dev[i] == NULL)
1632 continue;
1633 if (dev[i]->devtype != TYPE_DISK)
1634 continue;
1635 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1636 continue;
1637
1638 /*
1639 * If offload is currently enabled, the RAID map and
1640 * phys_disk[] assignment *better* not be changing
1641 * and since it isn't changing, we do not need to
1642 * update it.
1643 */
1644 if (dev[i]->offload_enabled)
1645 continue;
1646
1647 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1648 }
1649 }
1650
1651 static void adjust_hpsa_scsi_table(struct ctlr_info *h,
1652 struct hpsa_scsi_dev_t *sd[], int nsds)
1653 {
1654 /* sd contains scsi3 addresses and devtypes, and inquiry
1655 * data. This function takes what's in sd to be the current
1656 * reality and updates h->dev[] to reflect that reality.
1657 */
1658 int i, entry, device_change, changes = 0;
1659 struct hpsa_scsi_dev_t *csd;
1660 unsigned long flags;
1661 struct hpsa_scsi_dev_t **added, **removed;
1662 int nadded, nremoved;
1663 struct Scsi_Host *sh = NULL;
1664
1665 /*
1666 * A reset can cause a device status to change
1667 * re-schedule the scan to see what happened.
1668 */
1669 if (h->reset_in_progress) {
1670 h->drv_req_rescan = 1;
1671 return;
1672 }
1673
1674 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1675 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
1676
1677 if (!added || !removed) {
1678 dev_warn(&h->pdev->dev, "out of memory in "
1679 "adjust_hpsa_scsi_table\n");
1680 goto free_and_out;
1681 }
1682
1683 spin_lock_irqsave(&h->devlock, flags);
1684
1685 /* find any devices in h->dev[] that are not in
1686 * sd[] and remove them from h->dev[], and for any
1687 * devices which have changed, remove the old device
1688 * info and add the new device info.
1689 * If minor device attributes change, just update
1690 * the existing device structure.
1691 */
1692 i = 0;
1693 nremoved = 0;
1694 nadded = 0;
1695 while (i < h->ndevices) {
1696 csd = h->dev[i];
1697 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1698 if (device_change == DEVICE_NOT_FOUND) {
1699 changes++;
1700 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
1701 continue; /* remove ^^^, hence i not incremented */
1702 } else if (device_change == DEVICE_CHANGED) {
1703 changes++;
1704 hpsa_scsi_replace_entry(h, i, sd[entry],
1705 added, &nadded, removed, &nremoved);
1706 /* Set it to NULL to prevent it from being freed
1707 * at the bottom of hpsa_update_scsi_devices()
1708 */
1709 sd[entry] = NULL;
1710 } else if (device_change == DEVICE_UPDATED) {
1711 hpsa_scsi_update_entry(h, i, sd[entry]);
1712 }
1713 i++;
1714 }
1715
1716 /* Now, make sure every device listed in sd[] is also
1717 * listed in h->dev[], adding them if they aren't found
1718 */
1719
1720 for (i = 0; i < nsds; i++) {
1721 if (!sd[i]) /* if already added above. */
1722 continue;
1723
1724 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1725 * as the SCSI mid-layer does not handle such devices well.
1726 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1727 * at 160Hz, and prevents the system from coming up.
1728 */
1729 if (sd[i]->volume_offline) {
1730 hpsa_show_volume_status(h, sd[i]);
1731 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
1732 continue;
1733 }
1734
1735 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1736 h->ndevices, &entry);
1737 if (device_change == DEVICE_NOT_FOUND) {
1738 changes++;
1739 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
1740 break;
1741 sd[i] = NULL; /* prevent from being freed later. */
1742 } else if (device_change == DEVICE_CHANGED) {
1743 /* should never happen... */
1744 changes++;
1745 dev_warn(&h->pdev->dev,
1746 "device unexpectedly changed.\n");
1747 /* but if it does happen, we just ignore that device */
1748 }
1749 }
1750 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1751
1752 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1753 * any logical drives that need it enabled.
1754 */
1755 for (i = 0; i < h->ndevices; i++) {
1756 if (h->dev[i] == NULL)
1757 continue;
1758 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1759 }
1760
1761 spin_unlock_irqrestore(&h->devlock, flags);
1762
1763 /* Monitor devices which are in one of several NOT READY states to be
1764 * brought online later. This must be done without holding h->devlock,
1765 * so don't touch h->dev[]
1766 */
1767 for (i = 0; i < nsds; i++) {
1768 if (!sd[i]) /* if already added above. */
1769 continue;
1770 if (sd[i]->volume_offline)
1771 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1772 }
1773
1774 /* Don't notify scsi mid layer of any changes the first time through
1775 * (or if there are no changes) scsi_scan_host will do it later the
1776 * first time through.
1777 */
1778 if (!changes)
1779 goto free_and_out;
1780
1781 sh = h->scsi_host;
1782 if (sh == NULL) {
1783 dev_warn(&h->pdev->dev, "%s: scsi_host is null\n", __func__);
1784 goto free_and_out;
1785 }
1786 /* Notify scsi mid layer of any removed devices */
1787 for (i = 0; i < nremoved; i++) {
1788 if (removed[i] == NULL)
1789 continue;
1790 if (removed[i]->expose_device) {
1791 struct scsi_device *sdev =
1792 scsi_device_lookup(sh, removed[i]->bus,
1793 removed[i]->target, removed[i]->lun);
1794 if (sdev != NULL) {
1795 scsi_remove_device(sdev);
1796 scsi_device_put(sdev);
1797 } else {
1798 /*
1799 * We don't expect to get here.
1800 * future cmds to this device will get selection
1801 * timeout as if the device was gone.
1802 */
1803 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1804 "didn't find device for removal.");
1805 }
1806 }
1807 kfree(removed[i]);
1808 removed[i] = NULL;
1809 }
1810
1811 /* Notify scsi mid layer of any added devices */
1812 for (i = 0; i < nadded; i++) {
1813 if (added[i] == NULL)
1814 continue;
1815 if (!(added[i]->expose_device))
1816 continue;
1817 if (scsi_add_device(sh, added[i]->bus,
1818 added[i]->target, added[i]->lun) == 0)
1819 continue;
1820 dev_warn(&h->pdev->dev, "addition failed, device not added.");
1821 /* now we have to remove it from h->dev,
1822 * since it didn't get added to scsi mid layer
1823 */
1824 fixup_botched_add(h, added[i]);
1825 h->drv_req_rescan = 1;
1826 }
1827
1828 free_and_out:
1829 kfree(added);
1830 kfree(removed);
1831 }
1832
1833 /*
1834 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
1835 * Assume's h->devlock is held.
1836 */
1837 static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1838 int bus, int target, int lun)
1839 {
1840 int i;
1841 struct hpsa_scsi_dev_t *sd;
1842
1843 for (i = 0; i < h->ndevices; i++) {
1844 sd = h->dev[i];
1845 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1846 return sd;
1847 }
1848 return NULL;
1849 }
1850
1851 static int hpsa_slave_alloc(struct scsi_device *sdev)
1852 {
1853 struct hpsa_scsi_dev_t *sd;
1854 unsigned long flags;
1855 struct ctlr_info *h;
1856
1857 h = sdev_to_hba(sdev);
1858 spin_lock_irqsave(&h->devlock, flags);
1859 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1860 sdev_id(sdev), sdev->lun);
1861 if (likely(sd)) {
1862 atomic_set(&sd->ioaccel_cmds_out, 0);
1863 sdev->hostdata = sd->expose_device ? sd : NULL;
1864 } else
1865 sdev->hostdata = NULL;
1866 spin_unlock_irqrestore(&h->devlock, flags);
1867 return 0;
1868 }
1869
1870 /* configure scsi device based on internal per-device structure */
1871 static int hpsa_slave_configure(struct scsi_device *sdev)
1872 {
1873 struct hpsa_scsi_dev_t *sd;
1874 int queue_depth;
1875
1876 sd = sdev->hostdata;
1877 sdev->no_uld_attach = !sd || !sd->expose_device;
1878
1879 if (sd)
1880 queue_depth = sd->queue_depth != 0 ?
1881 sd->queue_depth : sdev->host->can_queue;
1882 else
1883 queue_depth = sdev->host->can_queue;
1884
1885 scsi_change_queue_depth(sdev, queue_depth);
1886
1887 return 0;
1888 }
1889
1890 static void hpsa_slave_destroy(struct scsi_device *sdev)
1891 {
1892 /* nothing to do. */
1893 }
1894
1895 static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1896 {
1897 int i;
1898
1899 if (!h->ioaccel2_cmd_sg_list)
1900 return;
1901 for (i = 0; i < h->nr_cmds; i++) {
1902 kfree(h->ioaccel2_cmd_sg_list[i]);
1903 h->ioaccel2_cmd_sg_list[i] = NULL;
1904 }
1905 kfree(h->ioaccel2_cmd_sg_list);
1906 h->ioaccel2_cmd_sg_list = NULL;
1907 }
1908
1909 static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1910 {
1911 int i;
1912
1913 if (h->chainsize <= 0)
1914 return 0;
1915
1916 h->ioaccel2_cmd_sg_list =
1917 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1918 GFP_KERNEL);
1919 if (!h->ioaccel2_cmd_sg_list)
1920 return -ENOMEM;
1921 for (i = 0; i < h->nr_cmds; i++) {
1922 h->ioaccel2_cmd_sg_list[i] =
1923 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1924 h->maxsgentries, GFP_KERNEL);
1925 if (!h->ioaccel2_cmd_sg_list[i])
1926 goto clean;
1927 }
1928 return 0;
1929
1930 clean:
1931 hpsa_free_ioaccel2_sg_chain_blocks(h);
1932 return -ENOMEM;
1933 }
1934
1935 static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1936 {
1937 int i;
1938
1939 if (!h->cmd_sg_list)
1940 return;
1941 for (i = 0; i < h->nr_cmds; i++) {
1942 kfree(h->cmd_sg_list[i]);
1943 h->cmd_sg_list[i] = NULL;
1944 }
1945 kfree(h->cmd_sg_list);
1946 h->cmd_sg_list = NULL;
1947 }
1948
1949 static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
1950 {
1951 int i;
1952
1953 if (h->chainsize <= 0)
1954 return 0;
1955
1956 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1957 GFP_KERNEL);
1958 if (!h->cmd_sg_list) {
1959 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
1960 return -ENOMEM;
1961 }
1962 for (i = 0; i < h->nr_cmds; i++) {
1963 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1964 h->chainsize, GFP_KERNEL);
1965 if (!h->cmd_sg_list[i]) {
1966 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
1967 goto clean;
1968 }
1969 }
1970 return 0;
1971
1972 clean:
1973 hpsa_free_sg_chain_blocks(h);
1974 return -ENOMEM;
1975 }
1976
1977 static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1978 struct io_accel2_cmd *cp, struct CommandList *c)
1979 {
1980 struct ioaccel2_sg_element *chain_block;
1981 u64 temp64;
1982 u32 chain_size;
1983
1984 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1985 chain_size = le32_to_cpu(cp->sg[0].length);
1986 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1987 PCI_DMA_TODEVICE);
1988 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1989 /* prevent subsequent unmapping */
1990 cp->sg->address = 0;
1991 return -1;
1992 }
1993 cp->sg->address = cpu_to_le64(temp64);
1994 return 0;
1995 }
1996
1997 static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1998 struct io_accel2_cmd *cp)
1999 {
2000 struct ioaccel2_sg_element *chain_sg;
2001 u64 temp64;
2002 u32 chain_size;
2003
2004 chain_sg = cp->sg;
2005 temp64 = le64_to_cpu(chain_sg->address);
2006 chain_size = le32_to_cpu(cp->sg[0].length);
2007 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2008 }
2009
2010 static int hpsa_map_sg_chain_block(struct ctlr_info *h,
2011 struct CommandList *c)
2012 {
2013 struct SGDescriptor *chain_sg, *chain_block;
2014 u64 temp64;
2015 u32 chain_len;
2016
2017 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2018 chain_block = h->cmd_sg_list[c->cmdindex];
2019 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2020 chain_len = sizeof(*chain_sg) *
2021 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
2022 chain_sg->Len = cpu_to_le32(chain_len);
2023 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
2024 PCI_DMA_TODEVICE);
2025 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2026 /* prevent subsequent unmapping */
2027 chain_sg->Addr = cpu_to_le64(0);
2028 return -1;
2029 }
2030 chain_sg->Addr = cpu_to_le64(temp64);
2031 return 0;
2032 }
2033
2034 static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2035 struct CommandList *c)
2036 {
2037 struct SGDescriptor *chain_sg;
2038
2039 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
2040 return;
2041
2042 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2043 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2044 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
2045 }
2046
2047
2048 /* Decode the various types of errors on ioaccel2 path.
2049 * Return 1 for any error that should generate a RAID path retry.
2050 * Return 0 for errors that don't require a RAID path retry.
2051 */
2052 static int handle_ioaccel_mode2_error(struct ctlr_info *h,
2053 struct CommandList *c,
2054 struct scsi_cmnd *cmd,
2055 struct io_accel2_cmd *c2)
2056 {
2057 int data_len;
2058 int retry = 0;
2059 u32 ioaccel2_resid = 0;
2060
2061 switch (c2->error_data.serv_response) {
2062 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2063 switch (c2->error_data.status) {
2064 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2065 break;
2066 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
2067 cmd->result |= SAM_STAT_CHECK_CONDITION;
2068 if (c2->error_data.data_present !=
2069 IOACCEL2_SENSE_DATA_PRESENT) {
2070 memset(cmd->sense_buffer, 0,
2071 SCSI_SENSE_BUFFERSIZE);
2072 break;
2073 }
2074 /* copy the sense data */
2075 data_len = c2->error_data.sense_data_len;
2076 if (data_len > SCSI_SENSE_BUFFERSIZE)
2077 data_len = SCSI_SENSE_BUFFERSIZE;
2078 if (data_len > sizeof(c2->error_data.sense_data_buff))
2079 data_len =
2080 sizeof(c2->error_data.sense_data_buff);
2081 memcpy(cmd->sense_buffer,
2082 c2->error_data.sense_data_buff, data_len);
2083 retry = 1;
2084 break;
2085 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
2086 retry = 1;
2087 break;
2088 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
2089 retry = 1;
2090 break;
2091 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
2092 retry = 1;
2093 break;
2094 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
2095 retry = 1;
2096 break;
2097 default:
2098 retry = 1;
2099 break;
2100 }
2101 break;
2102 case IOACCEL2_SERV_RESPONSE_FAILURE:
2103 switch (c2->error_data.status) {
2104 case IOACCEL2_STATUS_SR_IO_ERROR:
2105 case IOACCEL2_STATUS_SR_IO_ABORTED:
2106 case IOACCEL2_STATUS_SR_OVERRUN:
2107 retry = 1;
2108 break;
2109 case IOACCEL2_STATUS_SR_UNDERRUN:
2110 cmd->result = (DID_OK << 16); /* host byte */
2111 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2112 ioaccel2_resid = get_unaligned_le32(
2113 &c2->error_data.resid_cnt[0]);
2114 scsi_set_resid(cmd, ioaccel2_resid);
2115 break;
2116 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2117 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2118 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2119 /* We will get an event from ctlr to trigger rescan */
2120 retry = 1;
2121 break;
2122 default:
2123 retry = 1;
2124 }
2125 break;
2126 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2127 break;
2128 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2129 break;
2130 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
2131 retry = 1;
2132 break;
2133 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
2134 break;
2135 default:
2136 retry = 1;
2137 break;
2138 }
2139
2140 return retry; /* retry on raid path? */
2141 }
2142
2143 static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2144 struct CommandList *c)
2145 {
2146 bool do_wake = false;
2147
2148 /*
2149 * Prevent the following race in the abort handler:
2150 *
2151 * 1. LLD is requested to abort a SCSI command
2152 * 2. The SCSI command completes
2153 * 3. The struct CommandList associated with step 2 is made available
2154 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2155 * 5. Abort handler follows scsi_cmnd->host_scribble and
2156 * finds struct CommandList and tries to aborts it
2157 * Now we have aborted the wrong command.
2158 *
2159 * Reset c->scsi_cmd here so that the abort or reset handler will know
2160 * this command has completed. Then, check to see if the handler is
2161 * waiting for this command, and, if so, wake it.
2162 */
2163 c->scsi_cmd = SCSI_CMD_IDLE;
2164 mb(); /* Declare command idle before checking for pending events. */
2165 if (c->abort_pending) {
2166 do_wake = true;
2167 c->abort_pending = false;
2168 }
2169 if (c->reset_pending) {
2170 unsigned long flags;
2171 struct hpsa_scsi_dev_t *dev;
2172
2173 /*
2174 * There appears to be a reset pending; lock the lock and
2175 * reconfirm. If so, then decrement the count of outstanding
2176 * commands and wake the reset command if this is the last one.
2177 */
2178 spin_lock_irqsave(&h->lock, flags);
2179 dev = c->reset_pending; /* Re-fetch under the lock. */
2180 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2181 do_wake = true;
2182 c->reset_pending = NULL;
2183 spin_unlock_irqrestore(&h->lock, flags);
2184 }
2185
2186 if (do_wake)
2187 wake_up_all(&h->event_sync_wait_queue);
2188 }
2189
2190 static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2191 struct CommandList *c)
2192 {
2193 hpsa_cmd_resolve_events(h, c);
2194 cmd_tagged_free(h, c);
2195 }
2196
2197 static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2198 struct CommandList *c, struct scsi_cmnd *cmd)
2199 {
2200 hpsa_cmd_resolve_and_free(h, c);
2201 cmd->scsi_done(cmd);
2202 }
2203
2204 static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2205 {
2206 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2207 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2208 }
2209
2210 static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2211 {
2212 cmd->result = DID_ABORT << 16;
2213 }
2214
2215 static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2216 struct scsi_cmnd *cmd)
2217 {
2218 hpsa_set_scsi_cmd_aborted(cmd);
2219 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2220 c->Request.CDB, c->err_info->ScsiStatus);
2221 hpsa_cmd_resolve_and_free(h, c);
2222 }
2223
2224 static void process_ioaccel2_completion(struct ctlr_info *h,
2225 struct CommandList *c, struct scsi_cmnd *cmd,
2226 struct hpsa_scsi_dev_t *dev)
2227 {
2228 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2229
2230 /* check for good status */
2231 if (likely(c2->error_data.serv_response == 0 &&
2232 c2->error_data.status == 0))
2233 return hpsa_cmd_free_and_done(h, c, cmd);
2234
2235 /*
2236 * Any RAID offload error results in retry which will use
2237 * the normal I/O path so the controller can handle whatever's
2238 * wrong.
2239 */
2240 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2241 c2->error_data.serv_response ==
2242 IOACCEL2_SERV_RESPONSE_FAILURE) {
2243 if (c2->error_data.status ==
2244 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2245 dev->offload_enabled = 0;
2246
2247 return hpsa_retry_cmd(h, c);
2248 }
2249
2250 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
2251 return hpsa_retry_cmd(h, c);
2252
2253 return hpsa_cmd_free_and_done(h, c, cmd);
2254 }
2255
2256 /* Returns 0 on success, < 0 otherwise. */
2257 static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2258 struct CommandList *cp)
2259 {
2260 u8 tmf_status = cp->err_info->ScsiStatus;
2261
2262 switch (tmf_status) {
2263 case CISS_TMF_COMPLETE:
2264 /*
2265 * CISS_TMF_COMPLETE never happens, instead,
2266 * ei->CommandStatus == 0 for this case.
2267 */
2268 case CISS_TMF_SUCCESS:
2269 return 0;
2270 case CISS_TMF_INVALID_FRAME:
2271 case CISS_TMF_NOT_SUPPORTED:
2272 case CISS_TMF_FAILED:
2273 case CISS_TMF_WRONG_LUN:
2274 case CISS_TMF_OVERLAPPED_TAG:
2275 break;
2276 default:
2277 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2278 tmf_status);
2279 break;
2280 }
2281 return -tmf_status;
2282 }
2283
2284 static void complete_scsi_command(struct CommandList *cp)
2285 {
2286 struct scsi_cmnd *cmd;
2287 struct ctlr_info *h;
2288 struct ErrorInfo *ei;
2289 struct hpsa_scsi_dev_t *dev;
2290 struct io_accel2_cmd *c2;
2291
2292 u8 sense_key;
2293 u8 asc; /* additional sense code */
2294 u8 ascq; /* additional sense code qualifier */
2295 unsigned long sense_data_size;
2296
2297 ei = cp->err_info;
2298 cmd = cp->scsi_cmd;
2299 h = cp->h;
2300 dev = cmd->device->hostdata;
2301 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
2302
2303 scsi_dma_unmap(cmd); /* undo the DMA mappings */
2304 if ((cp->cmd_type == CMD_SCSI) &&
2305 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
2306 hpsa_unmap_sg_chain_block(h, cp);
2307
2308 if ((cp->cmd_type == CMD_IOACCEL2) &&
2309 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2310 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2311
2312 cmd->result = (DID_OK << 16); /* host byte */
2313 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2314
2315 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2316 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2317
2318 /*
2319 * We check for lockup status here as it may be set for
2320 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2321 * fail_all_oustanding_cmds()
2322 */
2323 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2324 /* DID_NO_CONNECT will prevent a retry */
2325 cmd->result = DID_NO_CONNECT << 16;
2326 return hpsa_cmd_free_and_done(h, cp, cmd);
2327 }
2328
2329 if ((unlikely(hpsa_is_pending_event(cp)))) {
2330 if (cp->reset_pending)
2331 return hpsa_cmd_resolve_and_free(h, cp);
2332 if (cp->abort_pending)
2333 return hpsa_cmd_abort_and_free(h, cp, cmd);
2334 }
2335
2336 if (cp->cmd_type == CMD_IOACCEL2)
2337 return process_ioaccel2_completion(h, cp, cmd, dev);
2338
2339 scsi_set_resid(cmd, ei->ResidualCnt);
2340 if (ei->CommandStatus == 0)
2341 return hpsa_cmd_free_and_done(h, cp, cmd);
2342
2343 /* For I/O accelerator commands, copy over some fields to the normal
2344 * CISS header used below for error handling.
2345 */
2346 if (cp->cmd_type == CMD_IOACCEL1) {
2347 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2348 cp->Header.SGList = scsi_sg_count(cmd);
2349 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2350 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2351 IOACCEL1_IOFLAGS_CDBLEN_MASK;
2352 cp->Header.tag = c->tag;
2353 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2354 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
2355
2356 /* Any RAID offload error results in retry which will use
2357 * the normal I/O path so the controller can handle whatever's
2358 * wrong.
2359 */
2360 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2361 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2362 dev->offload_enabled = 0;
2363 return hpsa_retry_cmd(h, cp);
2364 }
2365 }
2366
2367 /* an error has occurred */
2368 switch (ei->CommandStatus) {
2369
2370 case CMD_TARGET_STATUS:
2371 cmd->result |= ei->ScsiStatus;
2372 /* copy the sense data */
2373 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2374 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2375 else
2376 sense_data_size = sizeof(ei->SenseInfo);
2377 if (ei->SenseLen < sense_data_size)
2378 sense_data_size = ei->SenseLen;
2379 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2380 if (ei->ScsiStatus)
2381 decode_sense_data(ei->SenseInfo, sense_data_size,
2382 &sense_key, &asc, &ascq);
2383 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
2384 if (sense_key == ABORTED_COMMAND) {
2385 cmd->result |= DID_SOFT_ERROR << 16;
2386 break;
2387 }
2388 break;
2389 }
2390 /* Problem was not a check condition
2391 * Pass it up to the upper layers...
2392 */
2393 if (ei->ScsiStatus) {
2394 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2395 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2396 "Returning result: 0x%x\n",
2397 cp, ei->ScsiStatus,
2398 sense_key, asc, ascq,
2399 cmd->result);
2400 } else { /* scsi status is zero??? How??? */
2401 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2402 "Returning no connection.\n", cp),
2403
2404 /* Ordinarily, this case should never happen,
2405 * but there is a bug in some released firmware
2406 * revisions that allows it to happen if, for
2407 * example, a 4100 backplane loses power and
2408 * the tape drive is in it. We assume that
2409 * it's a fatal error of some kind because we
2410 * can't show that it wasn't. We will make it
2411 * look like selection timeout since that is
2412 * the most common reason for this to occur,
2413 * and it's severe enough.
2414 */
2415
2416 cmd->result = DID_NO_CONNECT << 16;
2417 }
2418 break;
2419
2420 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2421 break;
2422 case CMD_DATA_OVERRUN:
2423 dev_warn(&h->pdev->dev,
2424 "CDB %16phN data overrun\n", cp->Request.CDB);
2425 break;
2426 case CMD_INVALID: {
2427 /* print_bytes(cp, sizeof(*cp), 1, 0);
2428 print_cmd(cp); */
2429 /* We get CMD_INVALID if you address a non-existent device
2430 * instead of a selection timeout (no response). You will
2431 * see this if you yank out a drive, then try to access it.
2432 * This is kind of a shame because it means that any other
2433 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2434 * missing target. */
2435 cmd->result = DID_NO_CONNECT << 16;
2436 }
2437 break;
2438 case CMD_PROTOCOL_ERR:
2439 cmd->result = DID_ERROR << 16;
2440 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2441 cp->Request.CDB);
2442 break;
2443 case CMD_HARDWARE_ERR:
2444 cmd->result = DID_ERROR << 16;
2445 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2446 cp->Request.CDB);
2447 break;
2448 case CMD_CONNECTION_LOST:
2449 cmd->result = DID_ERROR << 16;
2450 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2451 cp->Request.CDB);
2452 break;
2453 case CMD_ABORTED:
2454 /* Return now to avoid calling scsi_done(). */
2455 return hpsa_cmd_abort_and_free(h, cp, cmd);
2456 case CMD_ABORT_FAILED:
2457 cmd->result = DID_ERROR << 16;
2458 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2459 cp->Request.CDB);
2460 break;
2461 case CMD_UNSOLICITED_ABORT:
2462 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
2463 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2464 cp->Request.CDB);
2465 break;
2466 case CMD_TIMEOUT:
2467 cmd->result = DID_TIME_OUT << 16;
2468 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2469 cp->Request.CDB);
2470 break;
2471 case CMD_UNABORTABLE:
2472 cmd->result = DID_ERROR << 16;
2473 dev_warn(&h->pdev->dev, "Command unabortable\n");
2474 break;
2475 case CMD_TMF_STATUS:
2476 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2477 cmd->result = DID_ERROR << 16;
2478 break;
2479 case CMD_IOACCEL_DISABLED:
2480 /* This only handles the direct pass-through case since RAID
2481 * offload is handled above. Just attempt a retry.
2482 */
2483 cmd->result = DID_SOFT_ERROR << 16;
2484 dev_warn(&h->pdev->dev,
2485 "cp %p had HP SSD Smart Path error\n", cp);
2486 break;
2487 default:
2488 cmd->result = DID_ERROR << 16;
2489 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2490 cp, ei->CommandStatus);
2491 }
2492
2493 return hpsa_cmd_free_and_done(h, cp, cmd);
2494 }
2495
2496 static void hpsa_pci_unmap(struct pci_dev *pdev,
2497 struct CommandList *c, int sg_used, int data_direction)
2498 {
2499 int i;
2500
2501 for (i = 0; i < sg_used; i++)
2502 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2503 le32_to_cpu(c->SG[i].Len),
2504 data_direction);
2505 }
2506
2507 static int hpsa_map_one(struct pci_dev *pdev,
2508 struct CommandList *cp,
2509 unsigned char *buf,
2510 size_t buflen,
2511 int data_direction)
2512 {
2513 u64 addr64;
2514
2515 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2516 cp->Header.SGList = 0;
2517 cp->Header.SGTotal = cpu_to_le16(0);
2518 return 0;
2519 }
2520
2521 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
2522 if (dma_mapping_error(&pdev->dev, addr64)) {
2523 /* Prevent subsequent unmap of something never mapped */
2524 cp->Header.SGList = 0;
2525 cp->Header.SGTotal = cpu_to_le16(0);
2526 return -1;
2527 }
2528 cp->SG[0].Addr = cpu_to_le64(addr64);
2529 cp->SG[0].Len = cpu_to_le32(buflen);
2530 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2531 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2532 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
2533 return 0;
2534 }
2535
2536 #define NO_TIMEOUT ((unsigned long) -1)
2537 #define DEFAULT_TIMEOUT 30000 /* milliseconds */
2538 static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2539 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
2540 {
2541 DECLARE_COMPLETION_ONSTACK(wait);
2542
2543 c->waiting = &wait;
2544 __enqueue_cmd_and_start_io(h, c, reply_queue);
2545 if (timeout_msecs == NO_TIMEOUT) {
2546 /* TODO: get rid of this no-timeout thing */
2547 wait_for_completion_io(&wait);
2548 return IO_OK;
2549 }
2550 if (!wait_for_completion_io_timeout(&wait,
2551 msecs_to_jiffies(timeout_msecs))) {
2552 dev_warn(&h->pdev->dev, "Command timed out.\n");
2553 return -ETIMEDOUT;
2554 }
2555 return IO_OK;
2556 }
2557
2558 static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2559 int reply_queue, unsigned long timeout_msecs)
2560 {
2561 if (unlikely(lockup_detected(h))) {
2562 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2563 return IO_OK;
2564 }
2565 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
2566 }
2567
2568 static u32 lockup_detected(struct ctlr_info *h)
2569 {
2570 int cpu;
2571 u32 rc, *lockup_detected;
2572
2573 cpu = get_cpu();
2574 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2575 rc = *lockup_detected;
2576 put_cpu();
2577 return rc;
2578 }
2579
2580 #define MAX_DRIVER_CMD_RETRIES 25
2581 static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2582 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
2583 {
2584 int backoff_time = 10, retry_count = 0;
2585 int rc;
2586
2587 do {
2588 memset(c->err_info, 0, sizeof(*c->err_info));
2589 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2590 timeout_msecs);
2591 if (rc)
2592 break;
2593 retry_count++;
2594 if (retry_count > 3) {
2595 msleep(backoff_time);
2596 if (backoff_time < 1000)
2597 backoff_time *= 2;
2598 }
2599 } while ((check_for_unit_attention(h, c) ||
2600 check_for_busy(h, c)) &&
2601 retry_count <= MAX_DRIVER_CMD_RETRIES);
2602 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2603 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2604 rc = -EIO;
2605 return rc;
2606 }
2607
2608 static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2609 struct CommandList *c)
2610 {
2611 const u8 *cdb = c->Request.CDB;
2612 const u8 *lun = c->Header.LUN.LunAddrBytes;
2613
2614 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2615 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2616 txt, lun[0], lun[1], lun[2], lun[3],
2617 lun[4], lun[5], lun[6], lun[7],
2618 cdb[0], cdb[1], cdb[2], cdb[3],
2619 cdb[4], cdb[5], cdb[6], cdb[7],
2620 cdb[8], cdb[9], cdb[10], cdb[11],
2621 cdb[12], cdb[13], cdb[14], cdb[15]);
2622 }
2623
2624 static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2625 struct CommandList *cp)
2626 {
2627 const struct ErrorInfo *ei = cp->err_info;
2628 struct device *d = &cp->h->pdev->dev;
2629 u8 sense_key, asc, ascq;
2630 int sense_len;
2631
2632 switch (ei->CommandStatus) {
2633 case CMD_TARGET_STATUS:
2634 if (ei->SenseLen > sizeof(ei->SenseInfo))
2635 sense_len = sizeof(ei->SenseInfo);
2636 else
2637 sense_len = ei->SenseLen;
2638 decode_sense_data(ei->SenseInfo, sense_len,
2639 &sense_key, &asc, &ascq);
2640 hpsa_print_cmd(h, "SCSI status", cp);
2641 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2642 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2643 sense_key, asc, ascq);
2644 else
2645 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
2646 if (ei->ScsiStatus == 0)
2647 dev_warn(d, "SCSI status is abnormally zero. "
2648 "(probably indicates selection timeout "
2649 "reported incorrectly due to a known "
2650 "firmware bug, circa July, 2001.)\n");
2651 break;
2652 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2653 break;
2654 case CMD_DATA_OVERRUN:
2655 hpsa_print_cmd(h, "overrun condition", cp);
2656 break;
2657 case CMD_INVALID: {
2658 /* controller unfortunately reports SCSI passthru's
2659 * to non-existent targets as invalid commands.
2660 */
2661 hpsa_print_cmd(h, "invalid command", cp);
2662 dev_warn(d, "probably means device no longer present\n");
2663 }
2664 break;
2665 case CMD_PROTOCOL_ERR:
2666 hpsa_print_cmd(h, "protocol error", cp);
2667 break;
2668 case CMD_HARDWARE_ERR:
2669 hpsa_print_cmd(h, "hardware error", cp);
2670 break;
2671 case CMD_CONNECTION_LOST:
2672 hpsa_print_cmd(h, "connection lost", cp);
2673 break;
2674 case CMD_ABORTED:
2675 hpsa_print_cmd(h, "aborted", cp);
2676 break;
2677 case CMD_ABORT_FAILED:
2678 hpsa_print_cmd(h, "abort failed", cp);
2679 break;
2680 case CMD_UNSOLICITED_ABORT:
2681 hpsa_print_cmd(h, "unsolicited abort", cp);
2682 break;
2683 case CMD_TIMEOUT:
2684 hpsa_print_cmd(h, "timed out", cp);
2685 break;
2686 case CMD_UNABORTABLE:
2687 hpsa_print_cmd(h, "unabortable", cp);
2688 break;
2689 case CMD_CTLR_LOCKUP:
2690 hpsa_print_cmd(h, "controller lockup detected", cp);
2691 break;
2692 default:
2693 hpsa_print_cmd(h, "unknown status", cp);
2694 dev_warn(d, "Unknown command status %x\n",
2695 ei->CommandStatus);
2696 }
2697 }
2698
2699 static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
2700 u16 page, unsigned char *buf,
2701 unsigned char bufsize)
2702 {
2703 int rc = IO_OK;
2704 struct CommandList *c;
2705 struct ErrorInfo *ei;
2706
2707 c = cmd_alloc(h);
2708
2709 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2710 page, scsi3addr, TYPE_CMD)) {
2711 rc = -1;
2712 goto out;
2713 }
2714 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2715 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2716 if (rc)
2717 goto out;
2718 ei = c->err_info;
2719 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2720 hpsa_scsi_interpret_error(h, c);
2721 rc = -1;
2722 }
2723 out:
2724 cmd_free(h, c);
2725 return rc;
2726 }
2727
2728 static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2729 u8 reset_type, int reply_queue)
2730 {
2731 int rc = IO_OK;
2732 struct CommandList *c;
2733 struct ErrorInfo *ei;
2734
2735 c = cmd_alloc(h);
2736
2737
2738 /* fill_cmd can't fail here, no data buffer to map. */
2739 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
2740 scsi3addr, TYPE_MSG);
2741 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2742 if (rc) {
2743 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2744 goto out;
2745 }
2746 /* no unmap needed here because no data xfer. */
2747
2748 ei = c->err_info;
2749 if (ei->CommandStatus != 0) {
2750 hpsa_scsi_interpret_error(h, c);
2751 rc = -1;
2752 }
2753 out:
2754 cmd_free(h, c);
2755 return rc;
2756 }
2757
2758 static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2759 struct hpsa_scsi_dev_t *dev,
2760 unsigned char *scsi3addr)
2761 {
2762 int i;
2763 bool match = false;
2764 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2765 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2766
2767 if (hpsa_is_cmd_idle(c))
2768 return false;
2769
2770 switch (c->cmd_type) {
2771 case CMD_SCSI:
2772 case CMD_IOCTL_PEND:
2773 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2774 sizeof(c->Header.LUN.LunAddrBytes));
2775 break;
2776
2777 case CMD_IOACCEL1:
2778 case CMD_IOACCEL2:
2779 if (c->phys_disk == dev) {
2780 /* HBA mode match */
2781 match = true;
2782 } else {
2783 /* Possible RAID mode -- check each phys dev. */
2784 /* FIXME: Do we need to take out a lock here? If
2785 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2786 * instead. */
2787 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2788 /* FIXME: an alternate test might be
2789 *
2790 * match = dev->phys_disk[i]->ioaccel_handle
2791 * == c2->scsi_nexus; */
2792 match = dev->phys_disk[i] == c->phys_disk;
2793 }
2794 }
2795 break;
2796
2797 case IOACCEL2_TMF:
2798 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2799 match = dev->phys_disk[i]->ioaccel_handle ==
2800 le32_to_cpu(ac->it_nexus);
2801 }
2802 break;
2803
2804 case 0: /* The command is in the middle of being initialized. */
2805 match = false;
2806 break;
2807
2808 default:
2809 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2810 c->cmd_type);
2811 BUG();
2812 }
2813
2814 return match;
2815 }
2816
2817 static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2818 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2819 {
2820 int i;
2821 int rc = 0;
2822
2823 /* We can really only handle one reset at a time */
2824 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2825 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2826 return -EINTR;
2827 }
2828
2829 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2830
2831 for (i = 0; i < h->nr_cmds; i++) {
2832 struct CommandList *c = h->cmd_pool + i;
2833 int refcount = atomic_inc_return(&c->refcount);
2834
2835 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2836 unsigned long flags;
2837
2838 /*
2839 * Mark the target command as having a reset pending,
2840 * then lock a lock so that the command cannot complete
2841 * while we're considering it. If the command is not
2842 * idle then count it; otherwise revoke the event.
2843 */
2844 c->reset_pending = dev;
2845 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2846 if (!hpsa_is_cmd_idle(c))
2847 atomic_inc(&dev->reset_cmds_out);
2848 else
2849 c->reset_pending = NULL;
2850 spin_unlock_irqrestore(&h->lock, flags);
2851 }
2852
2853 cmd_free(h, c);
2854 }
2855
2856 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2857 if (!rc)
2858 wait_event(h->event_sync_wait_queue,
2859 atomic_read(&dev->reset_cmds_out) == 0 ||
2860 lockup_detected(h));
2861
2862 if (unlikely(lockup_detected(h))) {
2863 dev_warn(&h->pdev->dev,
2864 "Controller lockup detected during reset wait\n");
2865 rc = -ENODEV;
2866 }
2867
2868 if (unlikely(rc))
2869 atomic_set(&dev->reset_cmds_out, 0);
2870
2871 mutex_unlock(&h->reset_mutex);
2872 return rc;
2873 }
2874
2875 static void hpsa_get_raid_level(struct ctlr_info *h,
2876 unsigned char *scsi3addr, unsigned char *raid_level)
2877 {
2878 int rc;
2879 unsigned char *buf;
2880
2881 *raid_level = RAID_UNKNOWN;
2882 buf = kzalloc(64, GFP_KERNEL);
2883 if (!buf)
2884 return;
2885 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
2886 if (rc == 0)
2887 *raid_level = buf[8];
2888 if (*raid_level > RAID_UNKNOWN)
2889 *raid_level = RAID_UNKNOWN;
2890 kfree(buf);
2891 return;
2892 }
2893
2894 #define HPSA_MAP_DEBUG
2895 #ifdef HPSA_MAP_DEBUG
2896 static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2897 struct raid_map_data *map_buff)
2898 {
2899 struct raid_map_disk_data *dd = &map_buff->data[0];
2900 int map, row, col;
2901 u16 map_cnt, row_cnt, disks_per_row;
2902
2903 if (rc != 0)
2904 return;
2905
2906 /* Show details only if debugging has been activated. */
2907 if (h->raid_offload_debug < 2)
2908 return;
2909
2910 dev_info(&h->pdev->dev, "structure_size = %u\n",
2911 le32_to_cpu(map_buff->structure_size));
2912 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2913 le32_to_cpu(map_buff->volume_blk_size));
2914 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2915 le64_to_cpu(map_buff->volume_blk_cnt));
2916 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2917 map_buff->phys_blk_shift);
2918 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2919 map_buff->parity_rotation_shift);
2920 dev_info(&h->pdev->dev, "strip_size = %u\n",
2921 le16_to_cpu(map_buff->strip_size));
2922 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2923 le64_to_cpu(map_buff->disk_starting_blk));
2924 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2925 le64_to_cpu(map_buff->disk_blk_cnt));
2926 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2927 le16_to_cpu(map_buff->data_disks_per_row));
2928 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2929 le16_to_cpu(map_buff->metadata_disks_per_row));
2930 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2931 le16_to_cpu(map_buff->row_cnt));
2932 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2933 le16_to_cpu(map_buff->layout_map_count));
2934 dev_info(&h->pdev->dev, "flags = 0x%x\n",
2935 le16_to_cpu(map_buff->flags));
2936 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2937 le16_to_cpu(map_buff->flags) &
2938 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
2939 dev_info(&h->pdev->dev, "dekindex = %u\n",
2940 le16_to_cpu(map_buff->dekindex));
2941 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2942 for (map = 0; map < map_cnt; map++) {
2943 dev_info(&h->pdev->dev, "Map%u:\n", map);
2944 row_cnt = le16_to_cpu(map_buff->row_cnt);
2945 for (row = 0; row < row_cnt; row++) {
2946 dev_info(&h->pdev->dev, " Row%u:\n", row);
2947 disks_per_row =
2948 le16_to_cpu(map_buff->data_disks_per_row);
2949 for (col = 0; col < disks_per_row; col++, dd++)
2950 dev_info(&h->pdev->dev,
2951 " D%02u: h=0x%04x xor=%u,%u\n",
2952 col, dd->ioaccel_handle,
2953 dd->xor_mult[0], dd->xor_mult[1]);
2954 disks_per_row =
2955 le16_to_cpu(map_buff->metadata_disks_per_row);
2956 for (col = 0; col < disks_per_row; col++, dd++)
2957 dev_info(&h->pdev->dev,
2958 " M%02u: h=0x%04x xor=%u,%u\n",
2959 col, dd->ioaccel_handle,
2960 dd->xor_mult[0], dd->xor_mult[1]);
2961 }
2962 }
2963 }
2964 #else
2965 static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2966 __attribute__((unused)) int rc,
2967 __attribute__((unused)) struct raid_map_data *map_buff)
2968 {
2969 }
2970 #endif
2971
2972 static int hpsa_get_raid_map(struct ctlr_info *h,
2973 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2974 {
2975 int rc = 0;
2976 struct CommandList *c;
2977 struct ErrorInfo *ei;
2978
2979 c = cmd_alloc(h);
2980
2981 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2982 sizeof(this_device->raid_map), 0,
2983 scsi3addr, TYPE_CMD)) {
2984 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2985 cmd_free(h, c);
2986 return -1;
2987 }
2988 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2989 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2990 if (rc)
2991 goto out;
2992 ei = c->err_info;
2993 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2994 hpsa_scsi_interpret_error(h, c);
2995 rc = -1;
2996 goto out;
2997 }
2998 cmd_free(h, c);
2999
3000 /* @todo in the future, dynamically allocate RAID map memory */
3001 if (le32_to_cpu(this_device->raid_map.structure_size) >
3002 sizeof(this_device->raid_map)) {
3003 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3004 rc = -1;
3005 }
3006 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3007 return rc;
3008 out:
3009 cmd_free(h, c);
3010 return rc;
3011 }
3012
3013 static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3014 unsigned char scsi3addr[], u16 bmic_device_index,
3015 struct bmic_identify_physical_device *buf, size_t bufsize)
3016 {
3017 int rc = IO_OK;
3018 struct CommandList *c;
3019 struct ErrorInfo *ei;
3020
3021 c = cmd_alloc(h);
3022 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3023 0, RAID_CTLR_LUNID, TYPE_CMD);
3024 if (rc)
3025 goto out;
3026
3027 c->Request.CDB[2] = bmic_device_index & 0xff;
3028 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3029
3030 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3031 NO_TIMEOUT);
3032 ei = c->err_info;
3033 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3034 hpsa_scsi_interpret_error(h, c);
3035 rc = -1;
3036 }
3037 out:
3038 cmd_free(h, c);
3039 return rc;
3040 }
3041
3042 static int hpsa_vpd_page_supported(struct ctlr_info *h,
3043 unsigned char scsi3addr[], u8 page)
3044 {
3045 int rc;
3046 int i;
3047 int pages;
3048 unsigned char *buf, bufsize;
3049
3050 buf = kzalloc(256, GFP_KERNEL);
3051 if (!buf)
3052 return 0;
3053
3054 /* Get the size of the page list first */
3055 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3056 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3057 buf, HPSA_VPD_HEADER_SZ);
3058 if (rc != 0)
3059 goto exit_unsupported;
3060 pages = buf[3];
3061 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3062 bufsize = pages + HPSA_VPD_HEADER_SZ;
3063 else
3064 bufsize = 255;
3065
3066 /* Get the whole VPD page list */
3067 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3068 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3069 buf, bufsize);
3070 if (rc != 0)
3071 goto exit_unsupported;
3072
3073 pages = buf[3];
3074 for (i = 1; i <= pages; i++)
3075 if (buf[3 + i] == page)
3076 goto exit_supported;
3077 exit_unsupported:
3078 kfree(buf);
3079 return 0;
3080 exit_supported:
3081 kfree(buf);
3082 return 1;
3083 }
3084
3085 static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3086 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3087 {
3088 int rc;
3089 unsigned char *buf;
3090 u8 ioaccel_status;
3091
3092 this_device->offload_config = 0;
3093 this_device->offload_enabled = 0;
3094 this_device->offload_to_be_enabled = 0;
3095
3096 buf = kzalloc(64, GFP_KERNEL);
3097 if (!buf)
3098 return;
3099 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3100 goto out;
3101 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3102 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
3103 if (rc != 0)
3104 goto out;
3105
3106 #define IOACCEL_STATUS_BYTE 4
3107 #define OFFLOAD_CONFIGURED_BIT 0x01
3108 #define OFFLOAD_ENABLED_BIT 0x02
3109 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3110 this_device->offload_config =
3111 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3112 if (this_device->offload_config) {
3113 this_device->offload_enabled =
3114 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3115 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3116 this_device->offload_enabled = 0;
3117 }
3118 this_device->offload_to_be_enabled = this_device->offload_enabled;
3119 out:
3120 kfree(buf);
3121 return;
3122 }
3123
3124 /* Get the device id from inquiry page 0x83 */
3125 static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3126 unsigned char *device_id, int buflen)
3127 {
3128 int rc;
3129 unsigned char *buf;
3130
3131 if (buflen > 16)
3132 buflen = 16;
3133 buf = kzalloc(64, GFP_KERNEL);
3134 if (!buf)
3135 return -ENOMEM;
3136 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
3137 if (rc == 0)
3138 memcpy(device_id, &buf[8], buflen);
3139 kfree(buf);
3140 return rc != 0;
3141 }
3142
3143 static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
3144 void *buf, int bufsize,
3145 int extended_response)
3146 {
3147 int rc = IO_OK;
3148 struct CommandList *c;
3149 unsigned char scsi3addr[8];
3150 struct ErrorInfo *ei;
3151
3152 c = cmd_alloc(h);
3153
3154 /* address the controller */
3155 memset(scsi3addr, 0, sizeof(scsi3addr));
3156 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3157 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3158 rc = -1;
3159 goto out;
3160 }
3161 if (extended_response)
3162 c->Request.CDB[1] = extended_response;
3163 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3164 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3165 if (rc)
3166 goto out;
3167 ei = c->err_info;
3168 if (ei->CommandStatus != 0 &&
3169 ei->CommandStatus != CMD_DATA_UNDERRUN) {
3170 hpsa_scsi_interpret_error(h, c);
3171 rc = -1;
3172 } else {
3173 struct ReportLUNdata *rld = buf;
3174
3175 if (rld->extended_response_flag != extended_response) {
3176 dev_err(&h->pdev->dev,
3177 "report luns requested format %u, got %u\n",
3178 extended_response,
3179 rld->extended_response_flag);
3180 rc = -1;
3181 }
3182 }
3183 out:
3184 cmd_free(h, c);
3185 return rc;
3186 }
3187
3188 static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
3189 struct ReportExtendedLUNdata *buf, int bufsize)
3190 {
3191 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3192 HPSA_REPORT_PHYS_EXTENDED);
3193 }
3194
3195 static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3196 struct ReportLUNdata *buf, int bufsize)
3197 {
3198 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3199 }
3200
3201 static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3202 int bus, int target, int lun)
3203 {
3204 device->bus = bus;
3205 device->target = target;
3206 device->lun = lun;
3207 }
3208
3209 /* Use VPD inquiry to get details of volume status */
3210 static int hpsa_get_volume_status(struct ctlr_info *h,
3211 unsigned char scsi3addr[])
3212 {
3213 int rc;
3214 int status;
3215 int size;
3216 unsigned char *buf;
3217
3218 buf = kzalloc(64, GFP_KERNEL);
3219 if (!buf)
3220 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3221
3222 /* Does controller have VPD for logical volume status? */
3223 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
3224 goto exit_failed;
3225
3226 /* Get the size of the VPD return buffer */
3227 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3228 buf, HPSA_VPD_HEADER_SZ);
3229 if (rc != 0)
3230 goto exit_failed;
3231 size = buf[3];
3232
3233 /* Now get the whole VPD buffer */
3234 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3235 buf, size + HPSA_VPD_HEADER_SZ);
3236 if (rc != 0)
3237 goto exit_failed;
3238 status = buf[4]; /* status byte */
3239
3240 kfree(buf);
3241 return status;
3242 exit_failed:
3243 kfree(buf);
3244 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3245 }
3246
3247 /* Determine offline status of a volume.
3248 * Return either:
3249 * 0 (not offline)
3250 * 0xff (offline for unknown reasons)
3251 * # (integer code indicating one of several NOT READY states
3252 * describing why a volume is to be kept offline)
3253 */
3254 static int hpsa_volume_offline(struct ctlr_info *h,
3255 unsigned char scsi3addr[])
3256 {
3257 struct CommandList *c;
3258 unsigned char *sense;
3259 u8 sense_key, asc, ascq;
3260 int sense_len;
3261 int rc, ldstat = 0;
3262 u16 cmd_status;
3263 u8 scsi_status;
3264 #define ASC_LUN_NOT_READY 0x04
3265 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3266 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3267
3268 c = cmd_alloc(h);
3269
3270 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
3271 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3272 if (rc) {
3273 cmd_free(h, c);
3274 return 0;
3275 }
3276 sense = c->err_info->SenseInfo;
3277 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3278 sense_len = sizeof(c->err_info->SenseInfo);
3279 else
3280 sense_len = c->err_info->SenseLen;
3281 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
3282 cmd_status = c->err_info->CommandStatus;
3283 scsi_status = c->err_info->ScsiStatus;
3284 cmd_free(h, c);
3285 /* Is the volume 'not ready'? */
3286 if (cmd_status != CMD_TARGET_STATUS ||
3287 scsi_status != SAM_STAT_CHECK_CONDITION ||
3288 sense_key != NOT_READY ||
3289 asc != ASC_LUN_NOT_READY) {
3290 return 0;
3291 }
3292
3293 /* Determine the reason for not ready state */
3294 ldstat = hpsa_get_volume_status(h, scsi3addr);
3295
3296 /* Keep volume offline in certain cases: */
3297 switch (ldstat) {
3298 case HPSA_LV_UNDERGOING_ERASE:
3299 case HPSA_LV_NOT_AVAILABLE:
3300 case HPSA_LV_UNDERGOING_RPI:
3301 case HPSA_LV_PENDING_RPI:
3302 case HPSA_LV_ENCRYPTED_NO_KEY:
3303 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3304 case HPSA_LV_UNDERGOING_ENCRYPTION:
3305 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3306 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3307 return ldstat;
3308 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3309 /* If VPD status page isn't available,
3310 * use ASC/ASCQ to determine state
3311 */
3312 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3313 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3314 return ldstat;
3315 break;
3316 default:
3317 break;
3318 }
3319 return 0;
3320 }
3321
3322 /*
3323 * Find out if a logical device supports aborts by simply trying one.
3324 * Smart Array may claim not to support aborts on logical drives, but
3325 * if a MSA2000 * is connected, the drives on that will be presented
3326 * by the Smart Array as logical drives, and aborts may be sent to
3327 * those devices successfully. So the simplest way to find out is
3328 * to simply try an abort and see how the device responds.
3329 */
3330 static int hpsa_device_supports_aborts(struct ctlr_info *h,
3331 unsigned char *scsi3addr)
3332 {
3333 struct CommandList *c;
3334 struct ErrorInfo *ei;
3335 int rc = 0;
3336
3337 u64 tag = (u64) -1; /* bogus tag */
3338
3339 /* Assume that physical devices support aborts */
3340 if (!is_logical_dev_addr_mode(scsi3addr))
3341 return 1;
3342
3343 c = cmd_alloc(h);
3344
3345 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3346 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3347 /* no unmap needed here because no data xfer. */
3348 ei = c->err_info;
3349 switch (ei->CommandStatus) {
3350 case CMD_INVALID:
3351 rc = 0;
3352 break;
3353 case CMD_UNABORTABLE:
3354 case CMD_ABORT_FAILED:
3355 rc = 1;
3356 break;
3357 case CMD_TMF_STATUS:
3358 rc = hpsa_evaluate_tmf_status(h, c);
3359 break;
3360 default:
3361 rc = 0;
3362 break;
3363 }
3364 cmd_free(h, c);
3365 return rc;
3366 }
3367
3368 static int hpsa_update_device_info(struct ctlr_info *h,
3369 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3370 unsigned char *is_OBDR_device)
3371 {
3372
3373 #define OBDR_SIG_OFFSET 43
3374 #define OBDR_TAPE_SIG "$DR-10"
3375 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3376 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3377
3378 unsigned char *inq_buff;
3379 unsigned char *obdr_sig;
3380 int rc = 0;
3381
3382 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
3383 if (!inq_buff) {
3384 rc = -ENOMEM;
3385 goto bail_out;
3386 }
3387
3388 /* Do an inquiry to the device to see what it is. */
3389 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3390 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3391 /* Inquiry failed (msg printed already) */
3392 dev_err(&h->pdev->dev,
3393 "hpsa_update_device_info: inquiry failed\n");
3394 rc = -EIO;
3395 goto bail_out;
3396 }
3397
3398 this_device->devtype = (inq_buff[0] & 0x1f);
3399 memcpy(this_device->scsi3addr, scsi3addr, 8);
3400 memcpy(this_device->vendor, &inq_buff[8],
3401 sizeof(this_device->vendor));
3402 memcpy(this_device->model, &inq_buff[16],
3403 sizeof(this_device->model));
3404 memset(this_device->device_id, 0,
3405 sizeof(this_device->device_id));
3406 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3407 sizeof(this_device->device_id));
3408
3409 if (this_device->devtype == TYPE_DISK &&
3410 is_logical_dev_addr_mode(scsi3addr)) {
3411 int volume_offline;
3412
3413 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
3414 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3415 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
3416 volume_offline = hpsa_volume_offline(h, scsi3addr);
3417 if (volume_offline < 0 || volume_offline > 0xff)
3418 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3419 this_device->volume_offline = volume_offline & 0xff;
3420 } else {
3421 this_device->raid_level = RAID_UNKNOWN;
3422 this_device->offload_config = 0;
3423 this_device->offload_enabled = 0;
3424 this_device->offload_to_be_enabled = 0;
3425 this_device->hba_ioaccel_enabled = 0;
3426 this_device->volume_offline = 0;
3427 this_device->queue_depth = h->nr_cmds;
3428 }
3429
3430 if (is_OBDR_device) {
3431 /* See if this is a One-Button-Disaster-Recovery device
3432 * by looking for "$DR-10" at offset 43 in inquiry data.
3433 */
3434 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3435 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3436 strncmp(obdr_sig, OBDR_TAPE_SIG,
3437 OBDR_SIG_LEN) == 0);
3438 }
3439 kfree(inq_buff);
3440 return 0;
3441
3442 bail_out:
3443 kfree(inq_buff);
3444 return rc;
3445 }
3446
3447 static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3448 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3449 {
3450 unsigned long flags;
3451 int rc, entry;
3452 /*
3453 * See if this device supports aborts. If we already know
3454 * the device, we already know if it supports aborts, otherwise
3455 * we have to find out if it supports aborts by trying one.
3456 */
3457 spin_lock_irqsave(&h->devlock, flags);
3458 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3459 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3460 entry >= 0 && entry < h->ndevices) {
3461 dev->supports_aborts = h->dev[entry]->supports_aborts;
3462 spin_unlock_irqrestore(&h->devlock, flags);
3463 } else {
3464 spin_unlock_irqrestore(&h->devlock, flags);
3465 dev->supports_aborts =
3466 hpsa_device_supports_aborts(h, scsi3addr);
3467 if (dev->supports_aborts < 0)
3468 dev->supports_aborts = 0;
3469 }
3470 }
3471
3472 static unsigned char *ext_target_model[] = {
3473 "MSA2012",
3474 "MSA2024",
3475 "MSA2312",
3476 "MSA2324",
3477 "P2000 G3 SAS",
3478 "MSA 2040 SAS",
3479 NULL,
3480 };
3481
3482 static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
3483 {
3484 int i;
3485
3486 for (i = 0; ext_target_model[i]; i++)
3487 if (strncmp(device->model, ext_target_model[i],
3488 strlen(ext_target_model[i])) == 0)
3489 return 1;
3490 return 0;
3491 }
3492
3493 /* Helper function to assign bus, target, lun mapping of devices.
3494 * Puts non-external target logical volumes on bus 0, external target logical
3495 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3496 * Logical drive target and lun are assigned at this time, but
3497 * physical device lun and target assignment are deferred (assigned
3498 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3499 */
3500 static void figure_bus_target_lun(struct ctlr_info *h,
3501 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
3502 {
3503 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3504
3505 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3506 /* physical device, target and lun filled in later */
3507 if (is_hba_lunid(lunaddrbytes))
3508 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
3509 else
3510 /* defer target, lun assignment for physical devices */
3511 hpsa_set_bus_target_lun(device, 2, -1, -1);
3512 return;
3513 }
3514 /* It's a logical device */
3515 if (is_ext_target(h, device)) {
3516 /* external target way, put logicals on bus 1
3517 * and match target/lun numbers box
3518 * reports, other smart array, bus 0, target 0, match lunid
3519 */
3520 hpsa_set_bus_target_lun(device,
3521 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3522 return;
3523 }
3524 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
3525 }
3526
3527 /*
3528 * If there is no lun 0 on a target, linux won't find any devices.
3529 * For the external targets (arrays), we have to manually detect the enclosure
3530 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3531 * it for some reason. *tmpdevice is the target we're adding,
3532 * this_device is a pointer into the current element of currentsd[]
3533 * that we're building up in update_scsi_devices(), below.
3534 * lunzerobits is a bitmap that tracks which targets already have a
3535 * lun 0 assigned.
3536 * Returns 1 if an enclosure was added, 0 if not.
3537 */
3538 static int add_ext_target_dev(struct ctlr_info *h,
3539 struct hpsa_scsi_dev_t *tmpdevice,
3540 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
3541 unsigned long lunzerobits[], int *n_ext_target_devs)
3542 {
3543 unsigned char scsi3addr[8];
3544
3545 if (test_bit(tmpdevice->target, lunzerobits))
3546 return 0; /* There is already a lun 0 on this target. */
3547
3548 if (!is_logical_dev_addr_mode(lunaddrbytes))
3549 return 0; /* It's the logical targets that may lack lun 0. */
3550
3551 if (!is_ext_target(h, tmpdevice))
3552 return 0; /* Only external target devices have this problem. */
3553
3554 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
3555 return 0;
3556
3557 memset(scsi3addr, 0, 8);
3558 scsi3addr[3] = tmpdevice->target;
3559 if (is_hba_lunid(scsi3addr))
3560 return 0; /* Don't add the RAID controller here. */
3561
3562 if (is_scsi_rev_5(h))
3563 return 0; /* p1210m doesn't need to do this. */
3564
3565 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
3566 dev_warn(&h->pdev->dev, "Maximum number of external "
3567 "target devices exceeded. Check your hardware "
3568 "configuration.");
3569 return 0;
3570 }
3571
3572 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
3573 return 0;
3574 (*n_ext_target_devs)++;
3575 hpsa_set_bus_target_lun(this_device,
3576 tmpdevice->bus, tmpdevice->target, 0);
3577 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
3578 set_bit(tmpdevice->target, lunzerobits);
3579 return 1;
3580 }
3581
3582 /*
3583 * Get address of physical disk used for an ioaccel2 mode command:
3584 * 1. Extract ioaccel2 handle from the command.
3585 * 2. Find a matching ioaccel2 handle from list of physical disks.
3586 * 3. Return:
3587 * 1 and set scsi3addr to address of matching physical
3588 * 0 if no matching physical disk was found.
3589 */
3590 static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3591 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3592 {
3593 struct io_accel2_cmd *c2 =
3594 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3595 unsigned long flags;
3596 int i;
3597
3598 spin_lock_irqsave(&h->devlock, flags);
3599 for (i = 0; i < h->ndevices; i++)
3600 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3601 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3602 sizeof(h->dev[i]->scsi3addr));
3603 spin_unlock_irqrestore(&h->devlock, flags);
3604 return 1;
3605 }
3606 spin_unlock_irqrestore(&h->devlock, flags);
3607 return 0;
3608 }
3609
3610 /*
3611 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3612 * logdev. The number of luns in physdev and logdev are returned in
3613 * *nphysicals and *nlogicals, respectively.
3614 * Returns 0 on success, -1 otherwise.
3615 */
3616 static int hpsa_gather_lun_info(struct ctlr_info *h,
3617 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
3618 struct ReportLUNdata *logdev, u32 *nlogicals)
3619 {
3620 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3621 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3622 return -1;
3623 }
3624 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
3625 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
3626 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3627 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
3628 *nphysicals = HPSA_MAX_PHYS_LUN;
3629 }
3630 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
3631 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3632 return -1;
3633 }
3634 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
3635 /* Reject Logicals in excess of our max capability. */
3636 if (*nlogicals > HPSA_MAX_LUN) {
3637 dev_warn(&h->pdev->dev,
3638 "maximum logical LUNs (%d) exceeded. "
3639 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3640 *nlogicals - HPSA_MAX_LUN);
3641 *nlogicals = HPSA_MAX_LUN;
3642 }
3643 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3644 dev_warn(&h->pdev->dev,
3645 "maximum logical + physical LUNs (%d) exceeded. "
3646 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3647 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3648 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3649 }
3650 return 0;
3651 }
3652
3653 static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3654 int i, int nphysicals, int nlogicals,
3655 struct ReportExtendedLUNdata *physdev_list,
3656 struct ReportLUNdata *logdev_list)
3657 {
3658 /* Helper function, figure out where the LUN ID info is coming from
3659 * given index i, lists of physical and logical devices, where in
3660 * the list the raid controller is supposed to appear (first or last)
3661 */
3662
3663 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3664 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3665
3666 if (i == raid_ctlr_position)
3667 return RAID_CTLR_LUNID;
3668
3669 if (i < logicals_start)
3670 return &physdev_list->LUN[i -
3671 (raid_ctlr_position == 0)].lunid[0];
3672
3673 if (i < last_device)
3674 return &logdev_list->LUN[i - nphysicals -
3675 (raid_ctlr_position == 0)][0];
3676 BUG();
3677 return NULL;
3678 }
3679
3680 /* get physical drive ioaccel handle and queue depth */
3681 static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3682 struct hpsa_scsi_dev_t *dev,
3683 struct ReportExtendedLUNdata *rlep, int rle_index,
3684 struct bmic_identify_physical_device *id_phys)
3685 {
3686 int rc;
3687 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3688
3689 dev->ioaccel_handle = rle->ioaccel_handle;
3690 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
3691 dev->hba_ioaccel_enabled = 1;
3692 memset(id_phys, 0, sizeof(*id_phys));
3693 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
3694 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
3695 sizeof(*id_phys));
3696 if (!rc)
3697 /* Reserve space for FW operations */
3698 #define DRIVE_CMDS_RESERVED_FOR_FW 2
3699 #define DRIVE_QUEUE_DEPTH 7
3700 dev->queue_depth =
3701 le16_to_cpu(id_phys->current_queue_depth_limit) -
3702 DRIVE_CMDS_RESERVED_FOR_FW;
3703 else
3704 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3705 }
3706
3707 static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
3708 struct ReportExtendedLUNdata *rlep, int rle_index,
3709 struct bmic_identify_physical_device *id_phys)
3710 {
3711 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3712
3713 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
3714 this_device->hba_ioaccel_enabled = 1;
3715
3716 memcpy(&this_device->active_path_index,
3717 &id_phys->active_path_number,
3718 sizeof(this_device->active_path_index));
3719 memcpy(&this_device->path_map,
3720 &id_phys->redundant_path_present_map,
3721 sizeof(this_device->path_map));
3722 memcpy(&this_device->box,
3723 &id_phys->alternate_paths_phys_box_on_port,
3724 sizeof(this_device->box));
3725 memcpy(&this_device->phys_connector,
3726 &id_phys->alternate_paths_phys_connector,
3727 sizeof(this_device->phys_connector));
3728 memcpy(&this_device->bay,
3729 &id_phys->phys_bay_in_box,
3730 sizeof(this_device->bay));
3731 }
3732
3733 static void hpsa_update_scsi_devices(struct ctlr_info *h)
3734 {
3735 /* the idea here is we could get notified
3736 * that some devices have changed, so we do a report
3737 * physical luns and report logical luns cmd, and adjust
3738 * our list of devices accordingly.
3739 *
3740 * The scsi3addr's of devices won't change so long as the
3741 * adapter is not reset. That means we can rescan and
3742 * tell which devices we already know about, vs. new
3743 * devices, vs. disappearing devices.
3744 */
3745 struct ReportExtendedLUNdata *physdev_list = NULL;
3746 struct ReportLUNdata *logdev_list = NULL;
3747 struct bmic_identify_physical_device *id_phys = NULL;
3748 u32 nphysicals = 0;
3749 u32 nlogicals = 0;
3750 u32 ndev_allocated = 0;
3751 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3752 int ncurrent = 0;
3753 int i, n_ext_target_devs, ndevs_to_allocate;
3754 int raid_ctlr_position;
3755 bool physical_device;
3756 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
3757
3758 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
3759 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3760 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
3761 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
3762 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3763
3764 if (!currentsd || !physdev_list || !logdev_list ||
3765 !tmpdevice || !id_phys) {
3766 dev_err(&h->pdev->dev, "out of memory\n");
3767 goto out;
3768 }
3769 memset(lunzerobits, 0, sizeof(lunzerobits));
3770
3771 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
3772
3773 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3774 logdev_list, &nlogicals)) {
3775 h->drv_req_rescan = 1;
3776 goto out;
3777 }
3778
3779 /* We might see up to the maximum number of logical and physical disks
3780 * plus external target devices, and a device for the local RAID
3781 * controller.
3782 */
3783 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
3784
3785 /* Allocate the per device structures */
3786 for (i = 0; i < ndevs_to_allocate; i++) {
3787 if (i >= HPSA_MAX_DEVICES) {
3788 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3789 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3790 ndevs_to_allocate - HPSA_MAX_DEVICES);
3791 break;
3792 }
3793
3794 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3795 if (!currentsd[i]) {
3796 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3797 __FILE__, __LINE__);
3798 h->drv_req_rescan = 1;
3799 goto out;
3800 }
3801 ndev_allocated++;
3802 }
3803
3804 if (is_scsi_rev_5(h))
3805 raid_ctlr_position = 0;
3806 else
3807 raid_ctlr_position = nphysicals + nlogicals;
3808
3809 /* adjust our table of devices */
3810 n_ext_target_devs = 0;
3811 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
3812 u8 *lunaddrbytes, is_OBDR = 0;
3813 int rc = 0;
3814 int phys_dev_index = i - (raid_ctlr_position == 0);
3815
3816 physical_device = i < nphysicals + (raid_ctlr_position == 0);
3817
3818 /* Figure out where the LUN ID info is coming from */
3819 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3820 i, nphysicals, nlogicals, physdev_list, logdev_list);
3821
3822 /* skip masked non-disk devices */
3823 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
3824 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
3825 continue;
3826
3827 /* Get device type, vendor, model, device id */
3828 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3829 &is_OBDR);
3830 if (rc == -ENOMEM) {
3831 dev_warn(&h->pdev->dev,
3832 "Out of memory, rescan deferred.\n");
3833 h->drv_req_rescan = 1;
3834 goto out;
3835 }
3836 if (rc) {
3837 dev_warn(&h->pdev->dev,
3838 "Inquiry failed, skipping device.\n");
3839 continue;
3840 }
3841
3842 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
3843 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
3844 this_device = currentsd[ncurrent];
3845
3846 /*
3847 * For external target devices, we have to insert a LUN 0 which
3848 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3849 * is nonetheless an enclosure device there. We have to
3850 * present that otherwise linux won't find anything if
3851 * there is no lun 0.
3852 */
3853 if (add_ext_target_dev(h, tmpdevice, this_device,
3854 lunaddrbytes, lunzerobits,
3855 &n_ext_target_devs)) {
3856 ncurrent++;
3857 this_device = currentsd[ncurrent];
3858 }
3859
3860 *this_device = *tmpdevice;
3861 this_device->physical_device = physical_device;
3862
3863 /*
3864 * Expose all devices except for physical devices that
3865 * are masked.
3866 */
3867 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
3868 this_device->expose_device = 0;
3869 else
3870 this_device->expose_device = 1;
3871
3872 switch (this_device->devtype) {
3873 case TYPE_ROM:
3874 /* We don't *really* support actual CD-ROM devices,
3875 * just "One Button Disaster Recovery" tape drive
3876 * which temporarily pretends to be a CD-ROM drive.
3877 * So we check that the device is really an OBDR tape
3878 * device by checking for "$DR-10" in bytes 43-48 of
3879 * the inquiry data.
3880 */
3881 if (is_OBDR)
3882 ncurrent++;
3883 break;
3884 case TYPE_DISK:
3885 if (this_device->physical_device) {
3886 /* The disk is in HBA mode. */
3887 /* Never use RAID mapper in HBA mode. */
3888 this_device->offload_enabled = 0;
3889 hpsa_get_ioaccel_drive_info(h, this_device,
3890 physdev_list, phys_dev_index, id_phys);
3891 hpsa_get_path_info(this_device,
3892 physdev_list, phys_dev_index, id_phys);
3893 }
3894 ncurrent++;
3895 break;
3896 case TYPE_TAPE:
3897 case TYPE_MEDIUM_CHANGER:
3898 case TYPE_ENCLOSURE:
3899 ncurrent++;
3900 break;
3901 case TYPE_RAID:
3902 /* Only present the Smartarray HBA as a RAID controller.
3903 * If it's a RAID controller other than the HBA itself
3904 * (an external RAID controller, MSA500 or similar)
3905 * don't present it.
3906 */
3907 if (!is_hba_lunid(lunaddrbytes))
3908 break;
3909 ncurrent++;
3910 break;
3911 default:
3912 break;
3913 }
3914 if (ncurrent >= HPSA_MAX_DEVICES)
3915 break;
3916 }
3917 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
3918 out:
3919 kfree(tmpdevice);
3920 for (i = 0; i < ndev_allocated; i++)
3921 kfree(currentsd[i]);
3922 kfree(currentsd);
3923 kfree(physdev_list);
3924 kfree(logdev_list);
3925 kfree(id_phys);
3926 }
3927
3928 static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3929 struct scatterlist *sg)
3930 {
3931 u64 addr64 = (u64) sg_dma_address(sg);
3932 unsigned int len = sg_dma_len(sg);
3933
3934 desc->Addr = cpu_to_le64(addr64);
3935 desc->Len = cpu_to_le32(len);
3936 desc->Ext = 0;
3937 }
3938
3939 /*
3940 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3941 * dma mapping and fills in the scatter gather entries of the
3942 * hpsa command, cp.
3943 */
3944 static int hpsa_scatter_gather(struct ctlr_info *h,
3945 struct CommandList *cp,
3946 struct scsi_cmnd *cmd)
3947 {
3948 struct scatterlist *sg;
3949 int use_sg, i, sg_limit, chained, last_sg;
3950 struct SGDescriptor *curr_sg;
3951
3952 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
3953
3954 use_sg = scsi_dma_map(cmd);
3955 if (use_sg < 0)
3956 return use_sg;
3957
3958 if (!use_sg)
3959 goto sglist_finished;
3960
3961 /*
3962 * If the number of entries is greater than the max for a single list,
3963 * then we have a chained list; we will set up all but one entry in the
3964 * first list (the last entry is saved for link information);
3965 * otherwise, we don't have a chained list and we'll set up at each of
3966 * the entries in the one list.
3967 */
3968 curr_sg = cp->SG;
3969 chained = use_sg > h->max_cmd_sg_entries;
3970 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3971 last_sg = scsi_sg_count(cmd) - 1;
3972 scsi_for_each_sg(cmd, sg, sg_limit, i) {
3973 hpsa_set_sg_descriptor(curr_sg, sg);
3974 curr_sg++;
3975 }
3976
3977 if (chained) {
3978 /*
3979 * Continue with the chained list. Set curr_sg to the chained
3980 * list. Modify the limit to the total count less the entries
3981 * we've already set up. Resume the scan at the list entry
3982 * where the previous loop left off.
3983 */
3984 curr_sg = h->cmd_sg_list[cp->cmdindex];
3985 sg_limit = use_sg - sg_limit;
3986 for_each_sg(sg, sg, sg_limit, i) {
3987 hpsa_set_sg_descriptor(curr_sg, sg);
3988 curr_sg++;
3989 }
3990 }
3991
3992 /* Back the pointer up to the last entry and mark it as "last". */
3993 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
3994
3995 if (use_sg + chained > h->maxSG)
3996 h->maxSG = use_sg + chained;
3997
3998 if (chained) {
3999 cp->Header.SGList = h->max_cmd_sg_entries;
4000 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
4001 if (hpsa_map_sg_chain_block(h, cp)) {
4002 scsi_dma_unmap(cmd);
4003 return -1;
4004 }
4005 return 0;
4006 }
4007
4008 sglist_finished:
4009
4010 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
4011 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
4012 return 0;
4013 }
4014
4015 #define IO_ACCEL_INELIGIBLE (1)
4016 static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4017 {
4018 int is_write = 0;
4019 u32 block;
4020 u32 block_cnt;
4021
4022 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4023 switch (cdb[0]) {
4024 case WRITE_6:
4025 case WRITE_12:
4026 is_write = 1;
4027 case READ_6:
4028 case READ_12:
4029 if (*cdb_len == 6) {
4030 block = get_unaligned_be16(&cdb[2]);
4031 block_cnt = cdb[4];
4032 if (block_cnt == 0)
4033 block_cnt = 256;
4034 } else {
4035 BUG_ON(*cdb_len != 12);
4036 block = get_unaligned_be32(&cdb[2]);
4037 block_cnt = get_unaligned_be32(&cdb[6]);
4038 }
4039 if (block_cnt > 0xffff)
4040 return IO_ACCEL_INELIGIBLE;
4041
4042 cdb[0] = is_write ? WRITE_10 : READ_10;
4043 cdb[1] = 0;
4044 cdb[2] = (u8) (block >> 24);
4045 cdb[3] = (u8) (block >> 16);
4046 cdb[4] = (u8) (block >> 8);
4047 cdb[5] = (u8) (block);
4048 cdb[6] = 0;
4049 cdb[7] = (u8) (block_cnt >> 8);
4050 cdb[8] = (u8) (block_cnt);
4051 cdb[9] = 0;
4052 *cdb_len = 10;
4053 break;
4054 }
4055 return 0;
4056 }
4057
4058 static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
4059 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
4060 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
4061 {
4062 struct scsi_cmnd *cmd = c->scsi_cmd;
4063 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4064 unsigned int len;
4065 unsigned int total_len = 0;
4066 struct scatterlist *sg;
4067 u64 addr64;
4068 int use_sg, i;
4069 struct SGDescriptor *curr_sg;
4070 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4071
4072 /* TODO: implement chaining support */
4073 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4074 atomic_dec(&phys_disk->ioaccel_cmds_out);
4075 return IO_ACCEL_INELIGIBLE;
4076 }
4077
4078 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4079
4080 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4081 atomic_dec(&phys_disk->ioaccel_cmds_out);
4082 return IO_ACCEL_INELIGIBLE;
4083 }
4084
4085 c->cmd_type = CMD_IOACCEL1;
4086
4087 /* Adjust the DMA address to point to the accelerated command buffer */
4088 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4089 (c->cmdindex * sizeof(*cp));
4090 BUG_ON(c->busaddr & 0x0000007F);
4091
4092 use_sg = scsi_dma_map(cmd);
4093 if (use_sg < 0) {
4094 atomic_dec(&phys_disk->ioaccel_cmds_out);
4095 return use_sg;
4096 }
4097
4098 if (use_sg) {
4099 curr_sg = cp->SG;
4100 scsi_for_each_sg(cmd, sg, use_sg, i) {
4101 addr64 = (u64) sg_dma_address(sg);
4102 len = sg_dma_len(sg);
4103 total_len += len;
4104 curr_sg->Addr = cpu_to_le64(addr64);
4105 curr_sg->Len = cpu_to_le32(len);
4106 curr_sg->Ext = cpu_to_le32(0);
4107 curr_sg++;
4108 }
4109 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
4110
4111 switch (cmd->sc_data_direction) {
4112 case DMA_TO_DEVICE:
4113 control |= IOACCEL1_CONTROL_DATA_OUT;
4114 break;
4115 case DMA_FROM_DEVICE:
4116 control |= IOACCEL1_CONTROL_DATA_IN;
4117 break;
4118 case DMA_NONE:
4119 control |= IOACCEL1_CONTROL_NODATAXFER;
4120 break;
4121 default:
4122 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4123 cmd->sc_data_direction);
4124 BUG();
4125 break;
4126 }
4127 } else {
4128 control |= IOACCEL1_CONTROL_NODATAXFER;
4129 }
4130
4131 c->Header.SGList = use_sg;
4132 /* Fill out the command structure to submit */
4133 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4134 cp->transfer_len = cpu_to_le32(total_len);
4135 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4136 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4137 cp->control = cpu_to_le32(control);
4138 memcpy(cp->CDB, cdb, cdb_len);
4139 memcpy(cp->CISS_LUN, scsi3addr, 8);
4140 /* Tag was already set at init time. */
4141 enqueue_cmd_and_start_io(h, c);
4142 return 0;
4143 }
4144
4145 /*
4146 * Queue a command directly to a device behind the controller using the
4147 * I/O accelerator path.
4148 */
4149 static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4150 struct CommandList *c)
4151 {
4152 struct scsi_cmnd *cmd = c->scsi_cmd;
4153 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4154
4155 c->phys_disk = dev;
4156
4157 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
4158 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
4159 }
4160
4161 /*
4162 * Set encryption parameters for the ioaccel2 request
4163 */
4164 static void set_encrypt_ioaccel2(struct ctlr_info *h,
4165 struct CommandList *c, struct io_accel2_cmd *cp)
4166 {
4167 struct scsi_cmnd *cmd = c->scsi_cmd;
4168 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4169 struct raid_map_data *map = &dev->raid_map;
4170 u64 first_block;
4171
4172 /* Are we doing encryption on this device */
4173 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
4174 return;
4175 /* Set the data encryption key index. */
4176 cp->dekindex = map->dekindex;
4177
4178 /* Set the encryption enable flag, encoded into direction field. */
4179 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4180
4181 /* Set encryption tweak values based on logical block address
4182 * If block size is 512, tweak value is LBA.
4183 * For other block sizes, tweak is (LBA * block size)/ 512)
4184 */
4185 switch (cmd->cmnd[0]) {
4186 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4187 case WRITE_6:
4188 case READ_6:
4189 first_block = get_unaligned_be16(&cmd->cmnd[2]);
4190 break;
4191 case WRITE_10:
4192 case READ_10:
4193 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4194 case WRITE_12:
4195 case READ_12:
4196 first_block = get_unaligned_be32(&cmd->cmnd[2]);
4197 break;
4198 case WRITE_16:
4199 case READ_16:
4200 first_block = get_unaligned_be64(&cmd->cmnd[2]);
4201 break;
4202 default:
4203 dev_err(&h->pdev->dev,
4204 "ERROR: %s: size (0x%x) not supported for encryption\n",
4205 __func__, cmd->cmnd[0]);
4206 BUG();
4207 break;
4208 }
4209
4210 if (le32_to_cpu(map->volume_blk_size) != 512)
4211 first_block = first_block *
4212 le32_to_cpu(map->volume_blk_size)/512;
4213
4214 cp->tweak_lower = cpu_to_le32(first_block);
4215 cp->tweak_upper = cpu_to_le32(first_block >> 32);
4216 }
4217
4218 static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4219 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
4220 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
4221 {
4222 struct scsi_cmnd *cmd = c->scsi_cmd;
4223 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4224 struct ioaccel2_sg_element *curr_sg;
4225 int use_sg, i;
4226 struct scatterlist *sg;
4227 u64 addr64;
4228 u32 len;
4229 u32 total_len = 0;
4230
4231 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
4232
4233 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4234 atomic_dec(&phys_disk->ioaccel_cmds_out);
4235 return IO_ACCEL_INELIGIBLE;
4236 }
4237
4238 c->cmd_type = CMD_IOACCEL2;
4239 /* Adjust the DMA address to point to the accelerated command buffer */
4240 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4241 (c->cmdindex * sizeof(*cp));
4242 BUG_ON(c->busaddr & 0x0000007F);
4243
4244 memset(cp, 0, sizeof(*cp));
4245 cp->IU_type = IOACCEL2_IU_TYPE;
4246
4247 use_sg = scsi_dma_map(cmd);
4248 if (use_sg < 0) {
4249 atomic_dec(&phys_disk->ioaccel_cmds_out);
4250 return use_sg;
4251 }
4252
4253 if (use_sg) {
4254 curr_sg = cp->sg;
4255 if (use_sg > h->ioaccel_maxsg) {
4256 addr64 = le64_to_cpu(
4257 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4258 curr_sg->address = cpu_to_le64(addr64);
4259 curr_sg->length = 0;
4260 curr_sg->reserved[0] = 0;
4261 curr_sg->reserved[1] = 0;
4262 curr_sg->reserved[2] = 0;
4263 curr_sg->chain_indicator = 0x80;
4264
4265 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4266 }
4267 scsi_for_each_sg(cmd, sg, use_sg, i) {
4268 addr64 = (u64) sg_dma_address(sg);
4269 len = sg_dma_len(sg);
4270 total_len += len;
4271 curr_sg->address = cpu_to_le64(addr64);
4272 curr_sg->length = cpu_to_le32(len);
4273 curr_sg->reserved[0] = 0;
4274 curr_sg->reserved[1] = 0;
4275 curr_sg->reserved[2] = 0;
4276 curr_sg->chain_indicator = 0;
4277 curr_sg++;
4278 }
4279
4280 switch (cmd->sc_data_direction) {
4281 case DMA_TO_DEVICE:
4282 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4283 cp->direction |= IOACCEL2_DIR_DATA_OUT;
4284 break;
4285 case DMA_FROM_DEVICE:
4286 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4287 cp->direction |= IOACCEL2_DIR_DATA_IN;
4288 break;
4289 case DMA_NONE:
4290 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4291 cp->direction |= IOACCEL2_DIR_NO_DATA;
4292 break;
4293 default:
4294 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4295 cmd->sc_data_direction);
4296 BUG();
4297 break;
4298 }
4299 } else {
4300 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4301 cp->direction |= IOACCEL2_DIR_NO_DATA;
4302 }
4303
4304 /* Set encryption parameters, if necessary */
4305 set_encrypt_ioaccel2(h, c, cp);
4306
4307 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
4308 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
4309 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
4310
4311 cp->data_len = cpu_to_le32(total_len);
4312 cp->err_ptr = cpu_to_le64(c->busaddr +
4313 offsetof(struct io_accel2_cmd, error_data));
4314 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
4315
4316 /* fill in sg elements */
4317 if (use_sg > h->ioaccel_maxsg) {
4318 cp->sg_count = 1;
4319 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
4320 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4321 atomic_dec(&phys_disk->ioaccel_cmds_out);
4322 scsi_dma_unmap(cmd);
4323 return -1;
4324 }
4325 } else
4326 cp->sg_count = (u8) use_sg;
4327
4328 enqueue_cmd_and_start_io(h, c);
4329 return 0;
4330 }
4331
4332 /*
4333 * Queue a command to the correct I/O accelerator path.
4334 */
4335 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4336 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
4337 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
4338 {
4339 /* Try to honor the device's queue depth */
4340 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4341 phys_disk->queue_depth) {
4342 atomic_dec(&phys_disk->ioaccel_cmds_out);
4343 return IO_ACCEL_INELIGIBLE;
4344 }
4345 if (h->transMethod & CFGTBL_Trans_io_accel1)
4346 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
4347 cdb, cdb_len, scsi3addr,
4348 phys_disk);
4349 else
4350 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
4351 cdb, cdb_len, scsi3addr,
4352 phys_disk);
4353 }
4354
4355 static void raid_map_helper(struct raid_map_data *map,
4356 int offload_to_mirror, u32 *map_index, u32 *current_group)
4357 {
4358 if (offload_to_mirror == 0) {
4359 /* use physical disk in the first mirrored group. */
4360 *map_index %= le16_to_cpu(map->data_disks_per_row);
4361 return;
4362 }
4363 do {
4364 /* determine mirror group that *map_index indicates */
4365 *current_group = *map_index /
4366 le16_to_cpu(map->data_disks_per_row);
4367 if (offload_to_mirror == *current_group)
4368 continue;
4369 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
4370 /* select map index from next group */
4371 *map_index += le16_to_cpu(map->data_disks_per_row);
4372 (*current_group)++;
4373 } else {
4374 /* select map index from first group */
4375 *map_index %= le16_to_cpu(map->data_disks_per_row);
4376 *current_group = 0;
4377 }
4378 } while (offload_to_mirror != *current_group);
4379 }
4380
4381 /*
4382 * Attempt to perform offload RAID mapping for a logical volume I/O.
4383 */
4384 static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4385 struct CommandList *c)
4386 {
4387 struct scsi_cmnd *cmd = c->scsi_cmd;
4388 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4389 struct raid_map_data *map = &dev->raid_map;
4390 struct raid_map_disk_data *dd = &map->data[0];
4391 int is_write = 0;
4392 u32 map_index;
4393 u64 first_block, last_block;
4394 u32 block_cnt;
4395 u32 blocks_per_row;
4396 u64 first_row, last_row;
4397 u32 first_row_offset, last_row_offset;
4398 u32 first_column, last_column;
4399 u64 r0_first_row, r0_last_row;
4400 u32 r5or6_blocks_per_row;
4401 u64 r5or6_first_row, r5or6_last_row;
4402 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4403 u32 r5or6_first_column, r5or6_last_column;
4404 u32 total_disks_per_row;
4405 u32 stripesize;
4406 u32 first_group, last_group, current_group;
4407 u32 map_row;
4408 u32 disk_handle;
4409 u64 disk_block;
4410 u32 disk_block_cnt;
4411 u8 cdb[16];
4412 u8 cdb_len;
4413 u16 strip_size;
4414 #if BITS_PER_LONG == 32
4415 u64 tmpdiv;
4416 #endif
4417 int offload_to_mirror;
4418
4419 /* check for valid opcode, get LBA and block count */
4420 switch (cmd->cmnd[0]) {
4421 case WRITE_6:
4422 is_write = 1;
4423 case READ_6:
4424 first_block = get_unaligned_be16(&cmd->cmnd[2]);
4425 block_cnt = cmd->cmnd[4];
4426 if (block_cnt == 0)
4427 block_cnt = 256;
4428 break;
4429 case WRITE_10:
4430 is_write = 1;
4431 case READ_10:
4432 first_block =
4433 (((u64) cmd->cmnd[2]) << 24) |
4434 (((u64) cmd->cmnd[3]) << 16) |
4435 (((u64) cmd->cmnd[4]) << 8) |
4436 cmd->cmnd[5];
4437 block_cnt =
4438 (((u32) cmd->cmnd[7]) << 8) |
4439 cmd->cmnd[8];
4440 break;
4441 case WRITE_12:
4442 is_write = 1;
4443 case READ_12:
4444 first_block =
4445 (((u64) cmd->cmnd[2]) << 24) |
4446 (((u64) cmd->cmnd[3]) << 16) |
4447 (((u64) cmd->cmnd[4]) << 8) |
4448 cmd->cmnd[5];
4449 block_cnt =
4450 (((u32) cmd->cmnd[6]) << 24) |
4451 (((u32) cmd->cmnd[7]) << 16) |
4452 (((u32) cmd->cmnd[8]) << 8) |
4453 cmd->cmnd[9];
4454 break;
4455 case WRITE_16:
4456 is_write = 1;
4457 case READ_16:
4458 first_block =
4459 (((u64) cmd->cmnd[2]) << 56) |
4460 (((u64) cmd->cmnd[3]) << 48) |
4461 (((u64) cmd->cmnd[4]) << 40) |
4462 (((u64) cmd->cmnd[5]) << 32) |
4463 (((u64) cmd->cmnd[6]) << 24) |
4464 (((u64) cmd->cmnd[7]) << 16) |
4465 (((u64) cmd->cmnd[8]) << 8) |
4466 cmd->cmnd[9];
4467 block_cnt =
4468 (((u32) cmd->cmnd[10]) << 24) |
4469 (((u32) cmd->cmnd[11]) << 16) |
4470 (((u32) cmd->cmnd[12]) << 8) |
4471 cmd->cmnd[13];
4472 break;
4473 default:
4474 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4475 }
4476 last_block = first_block + block_cnt - 1;
4477
4478 /* check for write to non-RAID-0 */
4479 if (is_write && dev->raid_level != 0)
4480 return IO_ACCEL_INELIGIBLE;
4481
4482 /* check for invalid block or wraparound */
4483 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4484 last_block < first_block)
4485 return IO_ACCEL_INELIGIBLE;
4486
4487 /* calculate stripe information for the request */
4488 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4489 le16_to_cpu(map->strip_size);
4490 strip_size = le16_to_cpu(map->strip_size);
4491 #if BITS_PER_LONG == 32
4492 tmpdiv = first_block;
4493 (void) do_div(tmpdiv, blocks_per_row);
4494 first_row = tmpdiv;
4495 tmpdiv = last_block;
4496 (void) do_div(tmpdiv, blocks_per_row);
4497 last_row = tmpdiv;
4498 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4499 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4500 tmpdiv = first_row_offset;
4501 (void) do_div(tmpdiv, strip_size);
4502 first_column = tmpdiv;
4503 tmpdiv = last_row_offset;
4504 (void) do_div(tmpdiv, strip_size);
4505 last_column = tmpdiv;
4506 #else
4507 first_row = first_block / blocks_per_row;
4508 last_row = last_block / blocks_per_row;
4509 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4510 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4511 first_column = first_row_offset / strip_size;
4512 last_column = last_row_offset / strip_size;
4513 #endif
4514
4515 /* if this isn't a single row/column then give to the controller */
4516 if ((first_row != last_row) || (first_column != last_column))
4517 return IO_ACCEL_INELIGIBLE;
4518
4519 /* proceeding with driver mapping */
4520 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4521 le16_to_cpu(map->metadata_disks_per_row);
4522 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
4523 le16_to_cpu(map->row_cnt);
4524 map_index = (map_row * total_disks_per_row) + first_column;
4525
4526 switch (dev->raid_level) {
4527 case HPSA_RAID_0:
4528 break; /* nothing special to do */
4529 case HPSA_RAID_1:
4530 /* Handles load balance across RAID 1 members.
4531 * (2-drive R1 and R10 with even # of drives.)
4532 * Appropriate for SSDs, not optimal for HDDs
4533 */
4534 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
4535 if (dev->offload_to_mirror)
4536 map_index += le16_to_cpu(map->data_disks_per_row);
4537 dev->offload_to_mirror = !dev->offload_to_mirror;
4538 break;
4539 case HPSA_RAID_ADM:
4540 /* Handles N-way mirrors (R1-ADM)
4541 * and R10 with # of drives divisible by 3.)
4542 */
4543 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
4544
4545 offload_to_mirror = dev->offload_to_mirror;
4546 raid_map_helper(map, offload_to_mirror,
4547 &map_index, &current_group);
4548 /* set mirror group to use next time */
4549 offload_to_mirror =
4550 (offload_to_mirror >=
4551 le16_to_cpu(map->layout_map_count) - 1)
4552 ? 0 : offload_to_mirror + 1;
4553 dev->offload_to_mirror = offload_to_mirror;
4554 /* Avoid direct use of dev->offload_to_mirror within this
4555 * function since multiple threads might simultaneously
4556 * increment it beyond the range of dev->layout_map_count -1.
4557 */
4558 break;
4559 case HPSA_RAID_5:
4560 case HPSA_RAID_6:
4561 if (le16_to_cpu(map->layout_map_count) <= 1)
4562 break;
4563
4564 /* Verify first and last block are in same RAID group */
4565 r5or6_blocks_per_row =
4566 le16_to_cpu(map->strip_size) *
4567 le16_to_cpu(map->data_disks_per_row);
4568 BUG_ON(r5or6_blocks_per_row == 0);
4569 stripesize = r5or6_blocks_per_row *
4570 le16_to_cpu(map->layout_map_count);
4571 #if BITS_PER_LONG == 32
4572 tmpdiv = first_block;
4573 first_group = do_div(tmpdiv, stripesize);
4574 tmpdiv = first_group;
4575 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4576 first_group = tmpdiv;
4577 tmpdiv = last_block;
4578 last_group = do_div(tmpdiv, stripesize);
4579 tmpdiv = last_group;
4580 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4581 last_group = tmpdiv;
4582 #else
4583 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4584 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
4585 #endif
4586 if (first_group != last_group)
4587 return IO_ACCEL_INELIGIBLE;
4588
4589 /* Verify request is in a single row of RAID 5/6 */
4590 #if BITS_PER_LONG == 32
4591 tmpdiv = first_block;
4592 (void) do_div(tmpdiv, stripesize);
4593 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4594 tmpdiv = last_block;
4595 (void) do_div(tmpdiv, stripesize);
4596 r5or6_last_row = r0_last_row = tmpdiv;
4597 #else
4598 first_row = r5or6_first_row = r0_first_row =
4599 first_block / stripesize;
4600 r5or6_last_row = r0_last_row = last_block / stripesize;
4601 #endif
4602 if (r5or6_first_row != r5or6_last_row)
4603 return IO_ACCEL_INELIGIBLE;
4604
4605
4606 /* Verify request is in a single column */
4607 #if BITS_PER_LONG == 32
4608 tmpdiv = first_block;
4609 first_row_offset = do_div(tmpdiv, stripesize);
4610 tmpdiv = first_row_offset;
4611 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4612 r5or6_first_row_offset = first_row_offset;
4613 tmpdiv = last_block;
4614 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4615 tmpdiv = r5or6_last_row_offset;
4616 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4617 tmpdiv = r5or6_first_row_offset;
4618 (void) do_div(tmpdiv, map->strip_size);
4619 first_column = r5or6_first_column = tmpdiv;
4620 tmpdiv = r5or6_last_row_offset;
4621 (void) do_div(tmpdiv, map->strip_size);
4622 r5or6_last_column = tmpdiv;
4623 #else
4624 first_row_offset = r5or6_first_row_offset =
4625 (u32)((first_block % stripesize) %
4626 r5or6_blocks_per_row);
4627
4628 r5or6_last_row_offset =
4629 (u32)((last_block % stripesize) %
4630 r5or6_blocks_per_row);
4631
4632 first_column = r5or6_first_column =
4633 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
4634 r5or6_last_column =
4635 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
4636 #endif
4637 if (r5or6_first_column != r5or6_last_column)
4638 return IO_ACCEL_INELIGIBLE;
4639
4640 /* Request is eligible */
4641 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
4642 le16_to_cpu(map->row_cnt);
4643
4644 map_index = (first_group *
4645 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
4646 (map_row * total_disks_per_row) + first_column;
4647 break;
4648 default:
4649 return IO_ACCEL_INELIGIBLE;
4650 }
4651
4652 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4653 return IO_ACCEL_INELIGIBLE;
4654
4655 c->phys_disk = dev->phys_disk[map_index];
4656
4657 disk_handle = dd[map_index].ioaccel_handle;
4658 disk_block = le64_to_cpu(map->disk_starting_blk) +
4659 first_row * le16_to_cpu(map->strip_size) +
4660 (first_row_offset - first_column *
4661 le16_to_cpu(map->strip_size));
4662 disk_block_cnt = block_cnt;
4663
4664 /* handle differing logical/physical block sizes */
4665 if (map->phys_blk_shift) {
4666 disk_block <<= map->phys_blk_shift;
4667 disk_block_cnt <<= map->phys_blk_shift;
4668 }
4669 BUG_ON(disk_block_cnt > 0xffff);
4670
4671 /* build the new CDB for the physical disk I/O */
4672 if (disk_block > 0xffffffff) {
4673 cdb[0] = is_write ? WRITE_16 : READ_16;
4674 cdb[1] = 0;
4675 cdb[2] = (u8) (disk_block >> 56);
4676 cdb[3] = (u8) (disk_block >> 48);
4677 cdb[4] = (u8) (disk_block >> 40);
4678 cdb[5] = (u8) (disk_block >> 32);
4679 cdb[6] = (u8) (disk_block >> 24);
4680 cdb[7] = (u8) (disk_block >> 16);
4681 cdb[8] = (u8) (disk_block >> 8);
4682 cdb[9] = (u8) (disk_block);
4683 cdb[10] = (u8) (disk_block_cnt >> 24);
4684 cdb[11] = (u8) (disk_block_cnt >> 16);
4685 cdb[12] = (u8) (disk_block_cnt >> 8);
4686 cdb[13] = (u8) (disk_block_cnt);
4687 cdb[14] = 0;
4688 cdb[15] = 0;
4689 cdb_len = 16;
4690 } else {
4691 cdb[0] = is_write ? WRITE_10 : READ_10;
4692 cdb[1] = 0;
4693 cdb[2] = (u8) (disk_block >> 24);
4694 cdb[3] = (u8) (disk_block >> 16);
4695 cdb[4] = (u8) (disk_block >> 8);
4696 cdb[5] = (u8) (disk_block);
4697 cdb[6] = 0;
4698 cdb[7] = (u8) (disk_block_cnt >> 8);
4699 cdb[8] = (u8) (disk_block_cnt);
4700 cdb[9] = 0;
4701 cdb_len = 10;
4702 }
4703 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
4704 dev->scsi3addr,
4705 dev->phys_disk[map_index]);
4706 }
4707
4708 /*
4709 * Submit commands down the "normal" RAID stack path
4710 * All callers to hpsa_ciss_submit must check lockup_detected
4711 * beforehand, before (opt.) and after calling cmd_alloc
4712 */
4713 static int hpsa_ciss_submit(struct ctlr_info *h,
4714 struct CommandList *c, struct scsi_cmnd *cmd,
4715 unsigned char scsi3addr[])
4716 {
4717 cmd->host_scribble = (unsigned char *) c;
4718 c->cmd_type = CMD_SCSI;
4719 c->scsi_cmd = cmd;
4720 c->Header.ReplyQueue = 0; /* unused in simple mode */
4721 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
4722 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
4723
4724 /* Fill in the request block... */
4725
4726 c->Request.Timeout = 0;
4727 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4728 c->Request.CDBLen = cmd->cmd_len;
4729 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
4730 switch (cmd->sc_data_direction) {
4731 case DMA_TO_DEVICE:
4732 c->Request.type_attr_dir =
4733 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
4734 break;
4735 case DMA_FROM_DEVICE:
4736 c->Request.type_attr_dir =
4737 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
4738 break;
4739 case DMA_NONE:
4740 c->Request.type_attr_dir =
4741 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
4742 break;
4743 case DMA_BIDIRECTIONAL:
4744 /* This can happen if a buggy application does a scsi passthru
4745 * and sets both inlen and outlen to non-zero. ( see
4746 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4747 */
4748
4749 c->Request.type_attr_dir =
4750 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
4751 /* This is technically wrong, and hpsa controllers should
4752 * reject it with CMD_INVALID, which is the most correct
4753 * response, but non-fibre backends appear to let it
4754 * slide by, and give the same results as if this field
4755 * were set correctly. Either way is acceptable for
4756 * our purposes here.
4757 */
4758
4759 break;
4760
4761 default:
4762 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4763 cmd->sc_data_direction);
4764 BUG();
4765 break;
4766 }
4767
4768 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
4769 hpsa_cmd_resolve_and_free(h, c);
4770 return SCSI_MLQUEUE_HOST_BUSY;
4771 }
4772 enqueue_cmd_and_start_io(h, c);
4773 /* the cmd'll come back via intr handler in complete_scsi_command() */
4774 return 0;
4775 }
4776
4777 static void hpsa_cmd_init(struct ctlr_info *h, int index,
4778 struct CommandList *c)
4779 {
4780 dma_addr_t cmd_dma_handle, err_dma_handle;
4781
4782 /* Zero out all of commandlist except the last field, refcount */
4783 memset(c, 0, offsetof(struct CommandList, refcount));
4784 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4785 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4786 c->err_info = h->errinfo_pool + index;
4787 memset(c->err_info, 0, sizeof(*c->err_info));
4788 err_dma_handle = h->errinfo_pool_dhandle
4789 + index * sizeof(*c->err_info);
4790 c->cmdindex = index;
4791 c->busaddr = (u32) cmd_dma_handle;
4792 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4793 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4794 c->h = h;
4795 c->scsi_cmd = SCSI_CMD_IDLE;
4796 }
4797
4798 static void hpsa_preinitialize_commands(struct ctlr_info *h)
4799 {
4800 int i;
4801
4802 for (i = 0; i < h->nr_cmds; i++) {
4803 struct CommandList *c = h->cmd_pool + i;
4804
4805 hpsa_cmd_init(h, i, c);
4806 atomic_set(&c->refcount, 0);
4807 }
4808 }
4809
4810 static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4811 struct CommandList *c)
4812 {
4813 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4814
4815 BUG_ON(c->cmdindex != index);
4816
4817 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4818 memset(c->err_info, 0, sizeof(*c->err_info));
4819 c->busaddr = (u32) cmd_dma_handle;
4820 }
4821
4822 static int hpsa_ioaccel_submit(struct ctlr_info *h,
4823 struct CommandList *c, struct scsi_cmnd *cmd,
4824 unsigned char *scsi3addr)
4825 {
4826 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4827 int rc = IO_ACCEL_INELIGIBLE;
4828
4829 cmd->host_scribble = (unsigned char *) c;
4830
4831 if (dev->offload_enabled) {
4832 hpsa_cmd_init(h, c->cmdindex, c);
4833 c->cmd_type = CMD_SCSI;
4834 c->scsi_cmd = cmd;
4835 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4836 if (rc < 0) /* scsi_dma_map failed. */
4837 rc = SCSI_MLQUEUE_HOST_BUSY;
4838 } else if (dev->hba_ioaccel_enabled) {
4839 hpsa_cmd_init(h, c->cmdindex, c);
4840 c->cmd_type = CMD_SCSI;
4841 c->scsi_cmd = cmd;
4842 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4843 if (rc < 0) /* scsi_dma_map failed. */
4844 rc = SCSI_MLQUEUE_HOST_BUSY;
4845 }
4846 return rc;
4847 }
4848
4849 static void hpsa_command_resubmit_worker(struct work_struct *work)
4850 {
4851 struct scsi_cmnd *cmd;
4852 struct hpsa_scsi_dev_t *dev;
4853 struct CommandList *c = container_of(work, struct CommandList, work);
4854
4855 cmd = c->scsi_cmd;
4856 dev = cmd->device->hostdata;
4857 if (!dev) {
4858 cmd->result = DID_NO_CONNECT << 16;
4859 return hpsa_cmd_free_and_done(c->h, c, cmd);
4860 }
4861 if (c->reset_pending)
4862 return hpsa_cmd_resolve_and_free(c->h, c);
4863 if (c->abort_pending)
4864 return hpsa_cmd_abort_and_free(c->h, c, cmd);
4865 if (c->cmd_type == CMD_IOACCEL2) {
4866 struct ctlr_info *h = c->h;
4867 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4868 int rc;
4869
4870 if (c2->error_data.serv_response ==
4871 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4872 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4873 if (rc == 0)
4874 return;
4875 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4876 /*
4877 * If we get here, it means dma mapping failed.
4878 * Try again via scsi mid layer, which will
4879 * then get SCSI_MLQUEUE_HOST_BUSY.
4880 */
4881 cmd->result = DID_IMM_RETRY << 16;
4882 return hpsa_cmd_free_and_done(h, c, cmd);
4883 }
4884 /* else, fall thru and resubmit down CISS path */
4885 }
4886 }
4887 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
4888 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4889 /*
4890 * If we get here, it means dma mapping failed. Try
4891 * again via scsi mid layer, which will then get
4892 * SCSI_MLQUEUE_HOST_BUSY.
4893 *
4894 * hpsa_ciss_submit will have already freed c
4895 * if it encountered a dma mapping failure.
4896 */
4897 cmd->result = DID_IMM_RETRY << 16;
4898 cmd->scsi_done(cmd);
4899 }
4900 }
4901
4902 /* Running in struct Scsi_Host->host_lock less mode */
4903 static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4904 {
4905 struct ctlr_info *h;
4906 struct hpsa_scsi_dev_t *dev;
4907 unsigned char scsi3addr[8];
4908 struct CommandList *c;
4909 int rc = 0;
4910
4911 /* Get the ptr to our adapter structure out of cmd->host. */
4912 h = sdev_to_hba(cmd->device);
4913
4914 BUG_ON(cmd->request->tag < 0);
4915
4916 dev = cmd->device->hostdata;
4917 if (!dev) {
4918 cmd->result = DID_NO_CONNECT << 16;
4919 cmd->scsi_done(cmd);
4920 return 0;
4921 }
4922
4923 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4924
4925 if (unlikely(lockup_detected(h))) {
4926 cmd->result = DID_NO_CONNECT << 16;
4927 cmd->scsi_done(cmd);
4928 return 0;
4929 }
4930 c = cmd_tagged_alloc(h, cmd);
4931
4932 /*
4933 * Call alternate submit routine for I/O accelerated commands.
4934 * Retries always go down the normal I/O path.
4935 */
4936 if (likely(cmd->retries == 0 &&
4937 cmd->request->cmd_type == REQ_TYPE_FS &&
4938 h->acciopath_status)) {
4939 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4940 if (rc == 0)
4941 return 0;
4942 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4943 hpsa_cmd_resolve_and_free(h, c);
4944 return SCSI_MLQUEUE_HOST_BUSY;
4945 }
4946 }
4947 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4948 }
4949
4950 static void hpsa_scan_complete(struct ctlr_info *h)
4951 {
4952 unsigned long flags;
4953
4954 spin_lock_irqsave(&h->scan_lock, flags);
4955 h->scan_finished = 1;
4956 wake_up_all(&h->scan_wait_queue);
4957 spin_unlock_irqrestore(&h->scan_lock, flags);
4958 }
4959
4960 static void hpsa_scan_start(struct Scsi_Host *sh)
4961 {
4962 struct ctlr_info *h = shost_to_hba(sh);
4963 unsigned long flags;
4964
4965 /*
4966 * Don't let rescans be initiated on a controller known to be locked
4967 * up. If the controller locks up *during* a rescan, that thread is
4968 * probably hosed, but at least we can prevent new rescan threads from
4969 * piling up on a locked up controller.
4970 */
4971 if (unlikely(lockup_detected(h)))
4972 return hpsa_scan_complete(h);
4973
4974 /* wait until any scan already in progress is finished. */
4975 while (1) {
4976 spin_lock_irqsave(&h->scan_lock, flags);
4977 if (h->scan_finished)
4978 break;
4979 spin_unlock_irqrestore(&h->scan_lock, flags);
4980 wait_event(h->scan_wait_queue, h->scan_finished);
4981 /* Note: We don't need to worry about a race between this
4982 * thread and driver unload because the midlayer will
4983 * have incremented the reference count, so unload won't
4984 * happen if we're in here.
4985 */
4986 }
4987 h->scan_finished = 0; /* mark scan as in progress */
4988 spin_unlock_irqrestore(&h->scan_lock, flags);
4989
4990 if (unlikely(lockup_detected(h)))
4991 return hpsa_scan_complete(h);
4992
4993 hpsa_update_scsi_devices(h);
4994
4995 hpsa_scan_complete(h);
4996 }
4997
4998 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4999 {
5000 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5001
5002 if (!logical_drive)
5003 return -ENODEV;
5004
5005 if (qdepth < 1)
5006 qdepth = 1;
5007 else if (qdepth > logical_drive->queue_depth)
5008 qdepth = logical_drive->queue_depth;
5009
5010 return scsi_change_queue_depth(sdev, qdepth);
5011 }
5012
5013 static int hpsa_scan_finished(struct Scsi_Host *sh,
5014 unsigned long elapsed_time)
5015 {
5016 struct ctlr_info *h = shost_to_hba(sh);
5017 unsigned long flags;
5018 int finished;
5019
5020 spin_lock_irqsave(&h->scan_lock, flags);
5021 finished = h->scan_finished;
5022 spin_unlock_irqrestore(&h->scan_lock, flags);
5023 return finished;
5024 }
5025
5026 static int hpsa_scsi_host_alloc(struct ctlr_info *h)
5027 {
5028 struct Scsi_Host *sh;
5029 int error;
5030
5031 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
5032 if (sh == NULL) {
5033 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5034 return -ENOMEM;
5035 }
5036
5037 sh->io_port = 0;
5038 sh->n_io_port = 0;
5039 sh->this_id = -1;
5040 sh->max_channel = 3;
5041 sh->max_cmd_len = MAX_COMMAND_SIZE;
5042 sh->max_lun = HPSA_MAX_LUN;
5043 sh->max_id = HPSA_MAX_LUN;
5044 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
5045 sh->cmd_per_lun = sh->can_queue;
5046 sh->sg_tablesize = h->maxsgentries;
5047 sh->hostdata[0] = (unsigned long) h;
5048 sh->irq = h->intr[h->intr_mode];
5049 sh->unique_id = sh->irq;
5050 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5051 if (error) {
5052 dev_err(&h->pdev->dev,
5053 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5054 __func__, h->ctlr);
5055 scsi_host_put(sh);
5056 return error;
5057 }
5058 h->scsi_host = sh;
5059 return 0;
5060 }
5061
5062 static int hpsa_scsi_add_host(struct ctlr_info *h)
5063 {
5064 int rv;
5065
5066 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5067 if (rv) {
5068 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5069 return rv;
5070 }
5071 scsi_scan_host(h->scsi_host);
5072 return 0;
5073 }
5074
5075 /*
5076 * The block layer has already gone to the trouble of picking out a unique,
5077 * small-integer tag for this request. We use an offset from that value as
5078 * an index to select our command block. (The offset allows us to reserve the
5079 * low-numbered entries for our own uses.)
5080 */
5081 static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5082 {
5083 int idx = scmd->request->tag;
5084
5085 if (idx < 0)
5086 return idx;
5087
5088 /* Offset to leave space for internal cmds. */
5089 return idx += HPSA_NRESERVED_CMDS;
5090 }
5091
5092 /*
5093 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5094 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5095 */
5096 static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5097 struct CommandList *c, unsigned char lunaddr[],
5098 int reply_queue)
5099 {
5100 int rc;
5101
5102 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5103 (void) fill_cmd(c, TEST_UNIT_READY, h,
5104 NULL, 0, 0, lunaddr, TYPE_CMD);
5105 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5106 if (rc)
5107 return rc;
5108 /* no unmap needed here because no data xfer. */
5109
5110 /* Check if the unit is already ready. */
5111 if (c->err_info->CommandStatus == CMD_SUCCESS)
5112 return 0;
5113
5114 /*
5115 * The first command sent after reset will receive "unit attention" to
5116 * indicate that the LUN has been reset...this is actually what we're
5117 * looking for (but, success is good too).
5118 */
5119 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5120 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5121 (c->err_info->SenseInfo[2] == NO_SENSE ||
5122 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5123 return 0;
5124
5125 return 1;
5126 }
5127
5128 /*
5129 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5130 * returns zero when the unit is ready, and non-zero when giving up.
5131 */
5132 static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5133 struct CommandList *c,
5134 unsigned char lunaddr[], int reply_queue)
5135 {
5136 int rc;
5137 int count = 0;
5138 int waittime = 1; /* seconds */
5139
5140 /* Send test unit ready until device ready, or give up. */
5141 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
5142
5143 /*
5144 * Wait for a bit. do this first, because if we send
5145 * the TUR right away, the reset will just abort it.
5146 */
5147 msleep(1000 * waittime);
5148
5149 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5150 if (!rc)
5151 break;
5152
5153 /* Increase wait time with each try, up to a point. */
5154 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
5155 waittime *= 2;
5156
5157 dev_warn(&h->pdev->dev,
5158 "waiting %d secs for device to become ready.\n",
5159 waittime);
5160 }
5161
5162 return rc;
5163 }
5164
5165 static int wait_for_device_to_become_ready(struct ctlr_info *h,
5166 unsigned char lunaddr[],
5167 int reply_queue)
5168 {
5169 int first_queue;
5170 int last_queue;
5171 int rq;
5172 int rc = 0;
5173 struct CommandList *c;
5174
5175 c = cmd_alloc(h);
5176
5177 /*
5178 * If no specific reply queue was requested, then send the TUR
5179 * repeatedly, requesting a reply on each reply queue; otherwise execute
5180 * the loop exactly once using only the specified queue.
5181 */
5182 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5183 first_queue = 0;
5184 last_queue = h->nreply_queues - 1;
5185 } else {
5186 first_queue = reply_queue;
5187 last_queue = reply_queue;
5188 }
5189
5190 for (rq = first_queue; rq <= last_queue; rq++) {
5191 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5192 if (rc)
5193 break;
5194 }
5195
5196 if (rc)
5197 dev_warn(&h->pdev->dev, "giving up on device.\n");
5198 else
5199 dev_warn(&h->pdev->dev, "device is ready.\n");
5200
5201 cmd_free(h, c);
5202 return rc;
5203 }
5204
5205 /* Need at least one of these error handlers to keep ../scsi/hosts.c from
5206 * complaining. Doing a host- or bus-reset can't do anything good here.
5207 */
5208 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5209 {
5210 int rc;
5211 struct ctlr_info *h;
5212 struct hpsa_scsi_dev_t *dev;
5213 u8 reset_type;
5214 char msg[48];
5215
5216 /* find the controller to which the command to be aborted was sent */
5217 h = sdev_to_hba(scsicmd->device);
5218 if (h == NULL) /* paranoia */
5219 return FAILED;
5220
5221 if (lockup_detected(h))
5222 return FAILED;
5223
5224 dev = scsicmd->device->hostdata;
5225 if (!dev) {
5226 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
5227 return FAILED;
5228 }
5229
5230 /* if controller locked up, we can guarantee command won't complete */
5231 if (lockup_detected(h)) {
5232 snprintf(msg, sizeof(msg),
5233 "cmd %d RESET FAILED, lockup detected",
5234 hpsa_get_cmd_index(scsicmd));
5235 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5236 return FAILED;
5237 }
5238
5239 /* this reset request might be the result of a lockup; check */
5240 if (detect_controller_lockup(h)) {
5241 snprintf(msg, sizeof(msg),
5242 "cmd %d RESET FAILED, new lockup detected",
5243 hpsa_get_cmd_index(scsicmd));
5244 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5245 return FAILED;
5246 }
5247
5248 /* Do not attempt on controller */
5249 if (is_hba_lunid(dev->scsi3addr))
5250 return SUCCESS;
5251
5252 if (is_logical_dev_addr_mode(dev->scsi3addr))
5253 reset_type = HPSA_DEVICE_RESET_MSG;
5254 else
5255 reset_type = HPSA_PHYS_TARGET_RESET;
5256
5257 sprintf(msg, "resetting %s",
5258 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5259 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5260
5261 h->reset_in_progress = 1;
5262
5263 /* send a reset to the SCSI LUN which the command was sent to */
5264 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
5265 DEFAULT_REPLY_QUEUE);
5266 sprintf(msg, "reset %s %s",
5267 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5268 rc == 0 ? "completed successfully" : "failed");
5269 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5270 h->reset_in_progress = 0;
5271 return rc == 0 ? SUCCESS : FAILED;
5272 }
5273
5274 static void swizzle_abort_tag(u8 *tag)
5275 {
5276 u8 original_tag[8];
5277
5278 memcpy(original_tag, tag, 8);
5279 tag[0] = original_tag[3];
5280 tag[1] = original_tag[2];
5281 tag[2] = original_tag[1];
5282 tag[3] = original_tag[0];
5283 tag[4] = original_tag[7];
5284 tag[5] = original_tag[6];
5285 tag[6] = original_tag[5];
5286 tag[7] = original_tag[4];
5287 }
5288
5289 static void hpsa_get_tag(struct ctlr_info *h,
5290 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
5291 {
5292 u64 tag;
5293 if (c->cmd_type == CMD_IOACCEL1) {
5294 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5295 &h->ioaccel_cmd_pool[c->cmdindex];
5296 tag = le64_to_cpu(cm1->tag);
5297 *tagupper = cpu_to_le32(tag >> 32);
5298 *taglower = cpu_to_le32(tag);
5299 return;
5300 }
5301 if (c->cmd_type == CMD_IOACCEL2) {
5302 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5303 &h->ioaccel2_cmd_pool[c->cmdindex];
5304 /* upper tag not used in ioaccel2 mode */
5305 memset(tagupper, 0, sizeof(*tagupper));
5306 *taglower = cm2->Tag;
5307 return;
5308 }
5309 tag = le64_to_cpu(c->Header.tag);
5310 *tagupper = cpu_to_le32(tag >> 32);
5311 *taglower = cpu_to_le32(tag);
5312 }
5313
5314 static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
5315 struct CommandList *abort, int reply_queue)
5316 {
5317 int rc = IO_OK;
5318 struct CommandList *c;
5319 struct ErrorInfo *ei;
5320 __le32 tagupper, taglower;
5321
5322 c = cmd_alloc(h);
5323
5324 /* fill_cmd can't fail here, no buffer to map */
5325 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
5326 0, 0, scsi3addr, TYPE_MSG);
5327 if (h->needs_abort_tags_swizzled)
5328 swizzle_abort_tag(&c->Request.CDB[4]);
5329 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5330 hpsa_get_tag(h, abort, &taglower, &tagupper);
5331 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
5332 __func__, tagupper, taglower);
5333 /* no unmap needed here because no data xfer. */
5334
5335 ei = c->err_info;
5336 switch (ei->CommandStatus) {
5337 case CMD_SUCCESS:
5338 break;
5339 case CMD_TMF_STATUS:
5340 rc = hpsa_evaluate_tmf_status(h, c);
5341 break;
5342 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5343 rc = -1;
5344 break;
5345 default:
5346 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
5347 __func__, tagupper, taglower);
5348 hpsa_scsi_interpret_error(h, c);
5349 rc = -1;
5350 break;
5351 }
5352 cmd_free(h, c);
5353 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5354 __func__, tagupper, taglower);
5355 return rc;
5356 }
5357
5358 static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5359 struct CommandList *command_to_abort, int reply_queue)
5360 {
5361 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5362 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5363 struct io_accel2_cmd *c2a =
5364 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
5365 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
5366 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5367
5368 /*
5369 * We're overlaying struct hpsa_tmf_struct on top of something which
5370 * was allocated as a struct io_accel2_cmd, so we better be sure it
5371 * actually fits, and doesn't overrun the error info space.
5372 */
5373 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5374 sizeof(struct io_accel2_cmd));
5375 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5376 offsetof(struct hpsa_tmf_struct, error_len) +
5377 sizeof(ac->error_len));
5378
5379 c->cmd_type = IOACCEL2_TMF;
5380 c->scsi_cmd = SCSI_CMD_BUSY;
5381
5382 /* Adjust the DMA address to point to the accelerated command buffer */
5383 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5384 (c->cmdindex * sizeof(struct io_accel2_cmd));
5385 BUG_ON(c->busaddr & 0x0000007F);
5386
5387 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5388 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5389 ac->reply_queue = reply_queue;
5390 ac->tmf = IOACCEL2_TMF_ABORT;
5391 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5392 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5393 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5394 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5395 ac->error_ptr = cpu_to_le64(c->busaddr +
5396 offsetof(struct io_accel2_cmd, error_data));
5397 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5398 }
5399
5400 /* ioaccel2 path firmware cannot handle abort task requests.
5401 * Change abort requests to physical target reset, and send to the
5402 * address of the physical disk used for the ioaccel 2 command.
5403 * Return 0 on success (IO_OK)
5404 * -1 on failure
5405 */
5406
5407 static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
5408 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
5409 {
5410 int rc = IO_OK;
5411 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5412 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5413 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5414 unsigned char *psa = &phys_scsi3addr[0];
5415
5416 /* Get a pointer to the hpsa logical device. */
5417 scmd = abort->scsi_cmd;
5418 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5419 if (dev == NULL) {
5420 dev_warn(&h->pdev->dev,
5421 "Cannot abort: no device pointer for command.\n");
5422 return -1; /* not abortable */
5423 }
5424
5425 if (h->raid_offload_debug > 0)
5426 dev_info(&h->pdev->dev,
5427 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5428 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
5429 "Reset as abort",
5430 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5431 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5432
5433 if (!dev->offload_enabled) {
5434 dev_warn(&h->pdev->dev,
5435 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5436 return -1; /* not abortable */
5437 }
5438
5439 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5440 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5441 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5442 return -1; /* not abortable */
5443 }
5444
5445 /* send the reset */
5446 if (h->raid_offload_debug > 0)
5447 dev_info(&h->pdev->dev,
5448 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5449 psa[0], psa[1], psa[2], psa[3],
5450 psa[4], psa[5], psa[6], psa[7]);
5451 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
5452 if (rc != 0) {
5453 dev_warn(&h->pdev->dev,
5454 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5455 psa[0], psa[1], psa[2], psa[3],
5456 psa[4], psa[5], psa[6], psa[7]);
5457 return rc; /* failed to reset */
5458 }
5459
5460 /* wait for device to recover */
5461 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
5462 dev_warn(&h->pdev->dev,
5463 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5464 psa[0], psa[1], psa[2], psa[3],
5465 psa[4], psa[5], psa[6], psa[7]);
5466 return -1; /* failed to recover */
5467 }
5468
5469 /* device recovered */
5470 dev_info(&h->pdev->dev,
5471 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5472 psa[0], psa[1], psa[2], psa[3],
5473 psa[4], psa[5], psa[6], psa[7]);
5474
5475 return rc; /* success */
5476 }
5477
5478 static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5479 struct CommandList *abort, int reply_queue)
5480 {
5481 int rc = IO_OK;
5482 struct CommandList *c;
5483 __le32 taglower, tagupper;
5484 struct hpsa_scsi_dev_t *dev;
5485 struct io_accel2_cmd *c2;
5486
5487 dev = abort->scsi_cmd->device->hostdata;
5488 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5489 return -1;
5490
5491 c = cmd_alloc(h);
5492 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5493 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5494 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5495 hpsa_get_tag(h, abort, &taglower, &tagupper);
5496 dev_dbg(&h->pdev->dev,
5497 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5498 __func__, tagupper, taglower);
5499 /* no unmap needed here because no data xfer. */
5500
5501 dev_dbg(&h->pdev->dev,
5502 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5503 __func__, tagupper, taglower, c2->error_data.serv_response);
5504 switch (c2->error_data.serv_response) {
5505 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5506 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5507 rc = 0;
5508 break;
5509 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5510 case IOACCEL2_SERV_RESPONSE_FAILURE:
5511 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5512 rc = -1;
5513 break;
5514 default:
5515 dev_warn(&h->pdev->dev,
5516 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5517 __func__, tagupper, taglower,
5518 c2->error_data.serv_response);
5519 rc = -1;
5520 }
5521 cmd_free(h, c);
5522 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5523 tagupper, taglower);
5524 return rc;
5525 }
5526
5527 static int hpsa_send_abort_both_ways(struct ctlr_info *h,
5528 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
5529 {
5530 /*
5531 * ioccelerator mode 2 commands should be aborted via the
5532 * accelerated path, since RAID path is unaware of these commands,
5533 * but not all underlying firmware can handle abort TMF.
5534 * Change abort to physical device reset when abort TMF is unsupported.
5535 */
5536 if (abort->cmd_type == CMD_IOACCEL2) {
5537 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5538 return hpsa_send_abort_ioaccel2(h, abort,
5539 reply_queue);
5540 else
5541 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
5542 abort, reply_queue);
5543 }
5544 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
5545 }
5546
5547 /* Find out which reply queue a command was meant to return on */
5548 static int hpsa_extract_reply_queue(struct ctlr_info *h,
5549 struct CommandList *c)
5550 {
5551 if (c->cmd_type == CMD_IOACCEL2)
5552 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5553 return c->Header.ReplyQueue;
5554 }
5555
5556 /*
5557 * Limit concurrency of abort commands to prevent
5558 * over-subscription of commands
5559 */
5560 static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5561 {
5562 #define ABORT_CMD_WAIT_MSECS 5000
5563 return !wait_event_timeout(h->abort_cmd_wait_queue,
5564 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5565 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5566 }
5567
5568 /* Send an abort for the specified command.
5569 * If the device and controller support it,
5570 * send a task abort request.
5571 */
5572 static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5573 {
5574
5575 int rc;
5576 struct ctlr_info *h;
5577 struct hpsa_scsi_dev_t *dev;
5578 struct CommandList *abort; /* pointer to command to be aborted */
5579 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5580 char msg[256]; /* For debug messaging. */
5581 int ml = 0;
5582 __le32 tagupper, taglower;
5583 int refcount, reply_queue;
5584
5585 if (sc == NULL)
5586 return FAILED;
5587
5588 if (sc->device == NULL)
5589 return FAILED;
5590
5591 /* Find the controller of the command to be aborted */
5592 h = sdev_to_hba(sc->device);
5593 if (h == NULL)
5594 return FAILED;
5595
5596 /* Find the device of the command to be aborted */
5597 dev = sc->device->hostdata;
5598 if (!dev) {
5599 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5600 msg);
5601 return FAILED;
5602 }
5603
5604 /* If controller locked up, we can guarantee command won't complete */
5605 if (lockup_detected(h)) {
5606 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5607 "ABORT FAILED, lockup detected");
5608 return FAILED;
5609 }
5610
5611 /* This is a good time to check if controller lockup has occurred */
5612 if (detect_controller_lockup(h)) {
5613 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5614 "ABORT FAILED, new lockup detected");
5615 return FAILED;
5616 }
5617
5618 /* Check that controller supports some kind of task abort */
5619 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5620 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5621 return FAILED;
5622
5623 memset(msg, 0, sizeof(msg));
5624 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
5625 h->scsi_host->host_no, sc->device->channel,
5626 sc->device->id, sc->device->lun,
5627 "Aborting command", sc);
5628
5629 /* Get SCSI command to be aborted */
5630 abort = (struct CommandList *) sc->host_scribble;
5631 if (abort == NULL) {
5632 /* This can happen if the command already completed. */
5633 return SUCCESS;
5634 }
5635 refcount = atomic_inc_return(&abort->refcount);
5636 if (refcount == 1) { /* Command is done already. */
5637 cmd_free(h, abort);
5638 return SUCCESS;
5639 }
5640
5641 /* Don't bother trying the abort if we know it won't work. */
5642 if (abort->cmd_type != CMD_IOACCEL2 &&
5643 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5644 cmd_free(h, abort);
5645 return FAILED;
5646 }
5647
5648 /*
5649 * Check that we're aborting the right command.
5650 * It's possible the CommandList already completed and got re-used.
5651 */
5652 if (abort->scsi_cmd != sc) {
5653 cmd_free(h, abort);
5654 return SUCCESS;
5655 }
5656
5657 abort->abort_pending = true;
5658 hpsa_get_tag(h, abort, &taglower, &tagupper);
5659 reply_queue = hpsa_extract_reply_queue(h, abort);
5660 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
5661 as = abort->scsi_cmd;
5662 if (as != NULL)
5663 ml += sprintf(msg+ml,
5664 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5665 as->cmd_len, as->cmnd[0], as->cmnd[1],
5666 as->serial_number);
5667 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
5668 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
5669
5670 /*
5671 * Command is in flight, or possibly already completed
5672 * by the firmware (but not to the scsi mid layer) but we can't
5673 * distinguish which. Send the abort down.
5674 */
5675 if (wait_for_available_abort_cmd(h)) {
5676 dev_warn(&h->pdev->dev,
5677 "%s FAILED, timeout waiting for an abort command to become available.\n",
5678 msg);
5679 cmd_free(h, abort);
5680 return FAILED;
5681 }
5682 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
5683 atomic_inc(&h->abort_cmds_available);
5684 wake_up_all(&h->abort_cmd_wait_queue);
5685 if (rc != 0) {
5686 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
5687 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5688 "FAILED to abort command");
5689 cmd_free(h, abort);
5690 return FAILED;
5691 }
5692 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
5693 wait_event(h->event_sync_wait_queue,
5694 abort->scsi_cmd != sc || lockup_detected(h));
5695 cmd_free(h, abort);
5696 return !lockup_detected(h) ? SUCCESS : FAILED;
5697 }
5698
5699 /*
5700 * For operations with an associated SCSI command, a command block is allocated
5701 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5702 * block request tag as an index into a table of entries. cmd_tagged_free() is
5703 * the complement, although cmd_free() may be called instead.
5704 */
5705 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5706 struct scsi_cmnd *scmd)
5707 {
5708 int idx = hpsa_get_cmd_index(scmd);
5709 struct CommandList *c = h->cmd_pool + idx;
5710
5711 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5712 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5713 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5714 /* The index value comes from the block layer, so if it's out of
5715 * bounds, it's probably not our bug.
5716 */
5717 BUG();
5718 }
5719
5720 atomic_inc(&c->refcount);
5721 if (unlikely(!hpsa_is_cmd_idle(c))) {
5722 /*
5723 * We expect that the SCSI layer will hand us a unique tag
5724 * value. Thus, there should never be a collision here between
5725 * two requests...because if the selected command isn't idle
5726 * then someone is going to be very disappointed.
5727 */
5728 dev_err(&h->pdev->dev,
5729 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5730 idx);
5731 if (c->scsi_cmd != NULL)
5732 scsi_print_command(c->scsi_cmd);
5733 scsi_print_command(scmd);
5734 }
5735
5736 hpsa_cmd_partial_init(h, idx, c);
5737 return c;
5738 }
5739
5740 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5741 {
5742 /*
5743 * Release our reference to the block. We don't need to do anything
5744 * else to free it, because it is accessed by index. (There's no point
5745 * in checking the result of the decrement, since we cannot guarantee
5746 * that there isn't a concurrent abort which is also accessing it.)
5747 */
5748 (void)atomic_dec(&c->refcount);
5749 }
5750
5751 /*
5752 * For operations that cannot sleep, a command block is allocated at init,
5753 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5754 * which ones are free or in use. Lock must be held when calling this.
5755 * cmd_free() is the complement.
5756 * This function never gives up and returns NULL. If it hangs,
5757 * another thread must call cmd_free() to free some tags.
5758 */
5759
5760 static struct CommandList *cmd_alloc(struct ctlr_info *h)
5761 {
5762 struct CommandList *c;
5763 int refcount, i;
5764 int offset = 0;
5765
5766 /*
5767 * There is some *extremely* small but non-zero chance that that
5768 * multiple threads could get in here, and one thread could
5769 * be scanning through the list of bits looking for a free
5770 * one, but the free ones are always behind him, and other
5771 * threads sneak in behind him and eat them before he can
5772 * get to them, so that while there is always a free one, a
5773 * very unlucky thread might be starved anyway, never able to
5774 * beat the other threads. In reality, this happens so
5775 * infrequently as to be indistinguishable from never.
5776 *
5777 * Note that we start allocating commands before the SCSI host structure
5778 * is initialized. Since the search starts at bit zero, this
5779 * all works, since we have at least one command structure available;
5780 * however, it means that the structures with the low indexes have to be
5781 * reserved for driver-initiated requests, while requests from the block
5782 * layer will use the higher indexes.
5783 */
5784
5785 for (;;) {
5786 i = find_next_zero_bit(h->cmd_pool_bits,
5787 HPSA_NRESERVED_CMDS,
5788 offset);
5789 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
5790 offset = 0;
5791 continue;
5792 }
5793 c = h->cmd_pool + i;
5794 refcount = atomic_inc_return(&c->refcount);
5795 if (unlikely(refcount > 1)) {
5796 cmd_free(h, c); /* already in use */
5797 offset = (i + 1) % HPSA_NRESERVED_CMDS;
5798 continue;
5799 }
5800 set_bit(i & (BITS_PER_LONG - 1),
5801 h->cmd_pool_bits + (i / BITS_PER_LONG));
5802 break; /* it's ours now. */
5803 }
5804 hpsa_cmd_partial_init(h, i, c);
5805 return c;
5806 }
5807
5808 /*
5809 * This is the complementary operation to cmd_alloc(). Note, however, in some
5810 * corner cases it may also be used to free blocks allocated by
5811 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5812 * the clear-bit is harmless.
5813 */
5814 static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5815 {
5816 if (atomic_dec_and_test(&c->refcount)) {
5817 int i;
5818
5819 i = c - h->cmd_pool;
5820 clear_bit(i & (BITS_PER_LONG - 1),
5821 h->cmd_pool_bits + (i / BITS_PER_LONG));
5822 }
5823 }
5824
5825 #ifdef CONFIG_COMPAT
5826
5827 static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5828 void __user *arg)
5829 {
5830 IOCTL32_Command_struct __user *arg32 =
5831 (IOCTL32_Command_struct __user *) arg;
5832 IOCTL_Command_struct arg64;
5833 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5834 int err;
5835 u32 cp;
5836
5837 memset(&arg64, 0, sizeof(arg64));
5838 err = 0;
5839 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5840 sizeof(arg64.LUN_info));
5841 err |= copy_from_user(&arg64.Request, &arg32->Request,
5842 sizeof(arg64.Request));
5843 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5844 sizeof(arg64.error_info));
5845 err |= get_user(arg64.buf_size, &arg32->buf_size);
5846 err |= get_user(cp, &arg32->buf);
5847 arg64.buf = compat_ptr(cp);
5848 err |= copy_to_user(p, &arg64, sizeof(arg64));
5849
5850 if (err)
5851 return -EFAULT;
5852
5853 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
5854 if (err)
5855 return err;
5856 err |= copy_in_user(&arg32->error_info, &p->error_info,
5857 sizeof(arg32->error_info));
5858 if (err)
5859 return -EFAULT;
5860 return err;
5861 }
5862
5863 static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
5864 int cmd, void __user *arg)
5865 {
5866 BIG_IOCTL32_Command_struct __user *arg32 =
5867 (BIG_IOCTL32_Command_struct __user *) arg;
5868 BIG_IOCTL_Command_struct arg64;
5869 BIG_IOCTL_Command_struct __user *p =
5870 compat_alloc_user_space(sizeof(arg64));
5871 int err;
5872 u32 cp;
5873
5874 memset(&arg64, 0, sizeof(arg64));
5875 err = 0;
5876 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5877 sizeof(arg64.LUN_info));
5878 err |= copy_from_user(&arg64.Request, &arg32->Request,
5879 sizeof(arg64.Request));
5880 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5881 sizeof(arg64.error_info));
5882 err |= get_user(arg64.buf_size, &arg32->buf_size);
5883 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5884 err |= get_user(cp, &arg32->buf);
5885 arg64.buf = compat_ptr(cp);
5886 err |= copy_to_user(p, &arg64, sizeof(arg64));
5887
5888 if (err)
5889 return -EFAULT;
5890
5891 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
5892 if (err)
5893 return err;
5894 err |= copy_in_user(&arg32->error_info, &p->error_info,
5895 sizeof(arg32->error_info));
5896 if (err)
5897 return -EFAULT;
5898 return err;
5899 }
5900
5901 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
5902 {
5903 switch (cmd) {
5904 case CCISS_GETPCIINFO:
5905 case CCISS_GETINTINFO:
5906 case CCISS_SETINTINFO:
5907 case CCISS_GETNODENAME:
5908 case CCISS_SETNODENAME:
5909 case CCISS_GETHEARTBEAT:
5910 case CCISS_GETBUSTYPES:
5911 case CCISS_GETFIRMVER:
5912 case CCISS_GETDRIVVER:
5913 case CCISS_REVALIDVOLS:
5914 case CCISS_DEREGDISK:
5915 case CCISS_REGNEWDISK:
5916 case CCISS_REGNEWD:
5917 case CCISS_RESCANDISK:
5918 case CCISS_GETLUNINFO:
5919 return hpsa_ioctl(dev, cmd, arg);
5920
5921 case CCISS_PASSTHRU32:
5922 return hpsa_ioctl32_passthru(dev, cmd, arg);
5923 case CCISS_BIG_PASSTHRU32:
5924 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5925
5926 default:
5927 return -ENOIOCTLCMD;
5928 }
5929 }
5930 #endif
5931
5932 static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5933 {
5934 struct hpsa_pci_info pciinfo;
5935
5936 if (!argp)
5937 return -EINVAL;
5938 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5939 pciinfo.bus = h->pdev->bus->number;
5940 pciinfo.dev_fn = h->pdev->devfn;
5941 pciinfo.board_id = h->board_id;
5942 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5943 return -EFAULT;
5944 return 0;
5945 }
5946
5947 static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5948 {
5949 DriverVer_type DriverVer;
5950 unsigned char vmaj, vmin, vsubmin;
5951 int rc;
5952
5953 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5954 &vmaj, &vmin, &vsubmin);
5955 if (rc != 3) {
5956 dev_info(&h->pdev->dev, "driver version string '%s' "
5957 "unrecognized.", HPSA_DRIVER_VERSION);
5958 vmaj = 0;
5959 vmin = 0;
5960 vsubmin = 0;
5961 }
5962 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5963 if (!argp)
5964 return -EINVAL;
5965 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5966 return -EFAULT;
5967 return 0;
5968 }
5969
5970 static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5971 {
5972 IOCTL_Command_struct iocommand;
5973 struct CommandList *c;
5974 char *buff = NULL;
5975 u64 temp64;
5976 int rc = 0;
5977
5978 if (!argp)
5979 return -EINVAL;
5980 if (!capable(CAP_SYS_RAWIO))
5981 return -EPERM;
5982 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5983 return -EFAULT;
5984 if ((iocommand.buf_size < 1) &&
5985 (iocommand.Request.Type.Direction != XFER_NONE)) {
5986 return -EINVAL;
5987 }
5988 if (iocommand.buf_size > 0) {
5989 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5990 if (buff == NULL)
5991 return -ENOMEM;
5992 if (iocommand.Request.Type.Direction & XFER_WRITE) {
5993 /* Copy the data into the buffer we created */
5994 if (copy_from_user(buff, iocommand.buf,
5995 iocommand.buf_size)) {
5996 rc = -EFAULT;
5997 goto out_kfree;
5998 }
5999 } else {
6000 memset(buff, 0, iocommand.buf_size);
6001 }
6002 }
6003 c = cmd_alloc(h);
6004
6005 /* Fill in the command type */
6006 c->cmd_type = CMD_IOCTL_PEND;
6007 c->scsi_cmd = SCSI_CMD_BUSY;
6008 /* Fill in Command Header */
6009 c->Header.ReplyQueue = 0; /* unused in simple mode */
6010 if (iocommand.buf_size > 0) { /* buffer to fill */
6011 c->Header.SGList = 1;
6012 c->Header.SGTotal = cpu_to_le16(1);
6013 } else { /* no buffers to fill */
6014 c->Header.SGList = 0;
6015 c->Header.SGTotal = cpu_to_le16(0);
6016 }
6017 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
6018
6019 /* Fill in Request block */
6020 memcpy(&c->Request, &iocommand.Request,
6021 sizeof(c->Request));
6022
6023 /* Fill in the scatter gather information */
6024 if (iocommand.buf_size > 0) {
6025 temp64 = pci_map_single(h->pdev, buff,
6026 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
6027 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6028 c->SG[0].Addr = cpu_to_le64(0);
6029 c->SG[0].Len = cpu_to_le32(0);
6030 rc = -ENOMEM;
6031 goto out;
6032 }
6033 c->SG[0].Addr = cpu_to_le64(temp64);
6034 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6035 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
6036 }
6037 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
6038 if (iocommand.buf_size > 0)
6039 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
6040 check_ioctl_unit_attention(h, c);
6041 if (rc) {
6042 rc = -EIO;
6043 goto out;
6044 }
6045
6046 /* Copy the error information out */
6047 memcpy(&iocommand.error_info, c->err_info,
6048 sizeof(iocommand.error_info));
6049 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
6050 rc = -EFAULT;
6051 goto out;
6052 }
6053 if ((iocommand.Request.Type.Direction & XFER_READ) &&
6054 iocommand.buf_size > 0) {
6055 /* Copy the data out of the buffer we created */
6056 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
6057 rc = -EFAULT;
6058 goto out;
6059 }
6060 }
6061 out:
6062 cmd_free(h, c);
6063 out_kfree:
6064 kfree(buff);
6065 return rc;
6066 }
6067
6068 static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6069 {
6070 BIG_IOCTL_Command_struct *ioc;
6071 struct CommandList *c;
6072 unsigned char **buff = NULL;
6073 int *buff_size = NULL;
6074 u64 temp64;
6075 BYTE sg_used = 0;
6076 int status = 0;
6077 u32 left;
6078 u32 sz;
6079 BYTE __user *data_ptr;
6080
6081 if (!argp)
6082 return -EINVAL;
6083 if (!capable(CAP_SYS_RAWIO))
6084 return -EPERM;
6085 ioc = (BIG_IOCTL_Command_struct *)
6086 kmalloc(sizeof(*ioc), GFP_KERNEL);
6087 if (!ioc) {
6088 status = -ENOMEM;
6089 goto cleanup1;
6090 }
6091 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6092 status = -EFAULT;
6093 goto cleanup1;
6094 }
6095 if ((ioc->buf_size < 1) &&
6096 (ioc->Request.Type.Direction != XFER_NONE)) {
6097 status = -EINVAL;
6098 goto cleanup1;
6099 }
6100 /* Check kmalloc limits using all SGs */
6101 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6102 status = -EINVAL;
6103 goto cleanup1;
6104 }
6105 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
6106 status = -EINVAL;
6107 goto cleanup1;
6108 }
6109 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
6110 if (!buff) {
6111 status = -ENOMEM;
6112 goto cleanup1;
6113 }
6114 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
6115 if (!buff_size) {
6116 status = -ENOMEM;
6117 goto cleanup1;
6118 }
6119 left = ioc->buf_size;
6120 data_ptr = ioc->buf;
6121 while (left) {
6122 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6123 buff_size[sg_used] = sz;
6124 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6125 if (buff[sg_used] == NULL) {
6126 status = -ENOMEM;
6127 goto cleanup1;
6128 }
6129 if (ioc->Request.Type.Direction & XFER_WRITE) {
6130 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
6131 status = -EFAULT;
6132 goto cleanup1;
6133 }
6134 } else
6135 memset(buff[sg_used], 0, sz);
6136 left -= sz;
6137 data_ptr += sz;
6138 sg_used++;
6139 }
6140 c = cmd_alloc(h);
6141
6142 c->cmd_type = CMD_IOCTL_PEND;
6143 c->scsi_cmd = SCSI_CMD_BUSY;
6144 c->Header.ReplyQueue = 0;
6145 c->Header.SGList = (u8) sg_used;
6146 c->Header.SGTotal = cpu_to_le16(sg_used);
6147 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
6148 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6149 if (ioc->buf_size > 0) {
6150 int i;
6151 for (i = 0; i < sg_used; i++) {
6152 temp64 = pci_map_single(h->pdev, buff[i],
6153 buff_size[i], PCI_DMA_BIDIRECTIONAL);
6154 if (dma_mapping_error(&h->pdev->dev,
6155 (dma_addr_t) temp64)) {
6156 c->SG[i].Addr = cpu_to_le64(0);
6157 c->SG[i].Len = cpu_to_le32(0);
6158 hpsa_pci_unmap(h->pdev, c, i,
6159 PCI_DMA_BIDIRECTIONAL);
6160 status = -ENOMEM;
6161 goto cleanup0;
6162 }
6163 c->SG[i].Addr = cpu_to_le64(temp64);
6164 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6165 c->SG[i].Ext = cpu_to_le32(0);
6166 }
6167 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
6168 }
6169 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
6170 if (sg_used)
6171 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
6172 check_ioctl_unit_attention(h, c);
6173 if (status) {
6174 status = -EIO;
6175 goto cleanup0;
6176 }
6177
6178 /* Copy the error information out */
6179 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6180 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
6181 status = -EFAULT;
6182 goto cleanup0;
6183 }
6184 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
6185 int i;
6186
6187 /* Copy the data out of the buffer we created */
6188 BYTE __user *ptr = ioc->buf;
6189 for (i = 0; i < sg_used; i++) {
6190 if (copy_to_user(ptr, buff[i], buff_size[i])) {
6191 status = -EFAULT;
6192 goto cleanup0;
6193 }
6194 ptr += buff_size[i];
6195 }
6196 }
6197 status = 0;
6198 cleanup0:
6199 cmd_free(h, c);
6200 cleanup1:
6201 if (buff) {
6202 int i;
6203
6204 for (i = 0; i < sg_used; i++)
6205 kfree(buff[i]);
6206 kfree(buff);
6207 }
6208 kfree(buff_size);
6209 kfree(ioc);
6210 return status;
6211 }
6212
6213 static void check_ioctl_unit_attention(struct ctlr_info *h,
6214 struct CommandList *c)
6215 {
6216 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6217 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6218 (void) check_for_unit_attention(h, c);
6219 }
6220
6221 /*
6222 * ioctl
6223 */
6224 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
6225 {
6226 struct ctlr_info *h;
6227 void __user *argp = (void __user *)arg;
6228 int rc;
6229
6230 h = sdev_to_hba(dev);
6231
6232 switch (cmd) {
6233 case CCISS_DEREGDISK:
6234 case CCISS_REGNEWDISK:
6235 case CCISS_REGNEWD:
6236 hpsa_scan_start(h->scsi_host);
6237 return 0;
6238 case CCISS_GETPCIINFO:
6239 return hpsa_getpciinfo_ioctl(h, argp);
6240 case CCISS_GETDRIVVER:
6241 return hpsa_getdrivver_ioctl(h, argp);
6242 case CCISS_PASSTHRU:
6243 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
6244 return -EAGAIN;
6245 rc = hpsa_passthru_ioctl(h, argp);
6246 atomic_inc(&h->passthru_cmds_avail);
6247 return rc;
6248 case CCISS_BIG_PASSTHRU:
6249 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
6250 return -EAGAIN;
6251 rc = hpsa_big_passthru_ioctl(h, argp);
6252 atomic_inc(&h->passthru_cmds_avail);
6253 return rc;
6254 default:
6255 return -ENOTTY;
6256 }
6257 }
6258
6259 static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6260 u8 reset_type)
6261 {
6262 struct CommandList *c;
6263
6264 c = cmd_alloc(h);
6265
6266 /* fill_cmd can't fail here, no data buffer to map */
6267 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
6268 RAID_CTLR_LUNID, TYPE_MSG);
6269 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6270 c->waiting = NULL;
6271 enqueue_cmd_and_start_io(h, c);
6272 /* Don't wait for completion, the reset won't complete. Don't free
6273 * the command either. This is the last command we will send before
6274 * re-initializing everything, so it doesn't matter and won't leak.
6275 */
6276 return;
6277 }
6278
6279 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
6280 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
6281 int cmd_type)
6282 {
6283 int pci_dir = XFER_NONE;
6284 u64 tag; /* for commands to be aborted */
6285
6286 c->cmd_type = CMD_IOCTL_PEND;
6287 c->scsi_cmd = SCSI_CMD_BUSY;
6288 c->Header.ReplyQueue = 0;
6289 if (buff != NULL && size > 0) {
6290 c->Header.SGList = 1;
6291 c->Header.SGTotal = cpu_to_le16(1);
6292 } else {
6293 c->Header.SGList = 0;
6294 c->Header.SGTotal = cpu_to_le16(0);
6295 }
6296 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6297
6298 if (cmd_type == TYPE_CMD) {
6299 switch (cmd) {
6300 case HPSA_INQUIRY:
6301 /* are we trying to read a vital product page */
6302 if (page_code & VPD_PAGE) {
6303 c->Request.CDB[1] = 0x01;
6304 c->Request.CDB[2] = (page_code & 0xff);
6305 }
6306 c->Request.CDBLen = 6;
6307 c->Request.type_attr_dir =
6308 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6309 c->Request.Timeout = 0;
6310 c->Request.CDB[0] = HPSA_INQUIRY;
6311 c->Request.CDB[4] = size & 0xFF;
6312 break;
6313 case HPSA_REPORT_LOG:
6314 case HPSA_REPORT_PHYS:
6315 /* Talking to controller so It's a physical command
6316 mode = 00 target = 0. Nothing to write.
6317 */
6318 c->Request.CDBLen = 12;
6319 c->Request.type_attr_dir =
6320 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6321 c->Request.Timeout = 0;
6322 c->Request.CDB[0] = cmd;
6323 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6324 c->Request.CDB[7] = (size >> 16) & 0xFF;
6325 c->Request.CDB[8] = (size >> 8) & 0xFF;
6326 c->Request.CDB[9] = size & 0xFF;
6327 break;
6328 case HPSA_CACHE_FLUSH:
6329 c->Request.CDBLen = 12;
6330 c->Request.type_attr_dir =
6331 TYPE_ATTR_DIR(cmd_type,
6332 ATTR_SIMPLE, XFER_WRITE);
6333 c->Request.Timeout = 0;
6334 c->Request.CDB[0] = BMIC_WRITE;
6335 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
6336 c->Request.CDB[7] = (size >> 8) & 0xFF;
6337 c->Request.CDB[8] = size & 0xFF;
6338 break;
6339 case TEST_UNIT_READY:
6340 c->Request.CDBLen = 6;
6341 c->Request.type_attr_dir =
6342 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6343 c->Request.Timeout = 0;
6344 break;
6345 case HPSA_GET_RAID_MAP:
6346 c->Request.CDBLen = 12;
6347 c->Request.type_attr_dir =
6348 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6349 c->Request.Timeout = 0;
6350 c->Request.CDB[0] = HPSA_CISS_READ;
6351 c->Request.CDB[1] = cmd;
6352 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6353 c->Request.CDB[7] = (size >> 16) & 0xFF;
6354 c->Request.CDB[8] = (size >> 8) & 0xFF;
6355 c->Request.CDB[9] = size & 0xFF;
6356 break;
6357 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6358 c->Request.CDBLen = 10;
6359 c->Request.type_attr_dir =
6360 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6361 c->Request.Timeout = 0;
6362 c->Request.CDB[0] = BMIC_READ;
6363 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6364 c->Request.CDB[7] = (size >> 16) & 0xFF;
6365 c->Request.CDB[8] = (size >> 8) & 0xFF;
6366 break;
6367 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6368 c->Request.CDBLen = 10;
6369 c->Request.type_attr_dir =
6370 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6371 c->Request.Timeout = 0;
6372 c->Request.CDB[0] = BMIC_READ;
6373 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6374 c->Request.CDB[7] = (size >> 16) & 0xFF;
6375 c->Request.CDB[8] = (size >> 8) & 0XFF;
6376 break;
6377 default:
6378 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6379 BUG();
6380 return -1;
6381 }
6382 } else if (cmd_type == TYPE_MSG) {
6383 switch (cmd) {
6384
6385 case HPSA_PHYS_TARGET_RESET:
6386 c->Request.CDBLen = 16;
6387 c->Request.type_attr_dir =
6388 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6389 c->Request.Timeout = 0; /* Don't time out */
6390 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6391 c->Request.CDB[0] = HPSA_RESET;
6392 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6393 /* Physical target reset needs no control bytes 4-7*/
6394 c->Request.CDB[4] = 0x00;
6395 c->Request.CDB[5] = 0x00;
6396 c->Request.CDB[6] = 0x00;
6397 c->Request.CDB[7] = 0x00;
6398 break;
6399 case HPSA_DEVICE_RESET_MSG:
6400 c->Request.CDBLen = 16;
6401 c->Request.type_attr_dir =
6402 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6403 c->Request.Timeout = 0; /* Don't time out */
6404 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6405 c->Request.CDB[0] = cmd;
6406 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
6407 /* If bytes 4-7 are zero, it means reset the */
6408 /* LunID device */
6409 c->Request.CDB[4] = 0x00;
6410 c->Request.CDB[5] = 0x00;
6411 c->Request.CDB[6] = 0x00;
6412 c->Request.CDB[7] = 0x00;
6413 break;
6414 case HPSA_ABORT_MSG:
6415 memcpy(&tag, buff, sizeof(tag));
6416 dev_dbg(&h->pdev->dev,
6417 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6418 tag, c->Header.tag);
6419 c->Request.CDBLen = 16;
6420 c->Request.type_attr_dir =
6421 TYPE_ATTR_DIR(cmd_type,
6422 ATTR_SIMPLE, XFER_WRITE);
6423 c->Request.Timeout = 0; /* Don't time out */
6424 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6425 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6426 c->Request.CDB[2] = 0x00; /* reserved */
6427 c->Request.CDB[3] = 0x00; /* reserved */
6428 /* Tag to abort goes in CDB[4]-CDB[11] */
6429 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
6430 c->Request.CDB[12] = 0x00; /* reserved */
6431 c->Request.CDB[13] = 0x00; /* reserved */
6432 c->Request.CDB[14] = 0x00; /* reserved */
6433 c->Request.CDB[15] = 0x00; /* reserved */
6434 break;
6435 default:
6436 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6437 cmd);
6438 BUG();
6439 }
6440 } else {
6441 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6442 BUG();
6443 }
6444
6445 switch (GET_DIR(c->Request.type_attr_dir)) {
6446 case XFER_READ:
6447 pci_dir = PCI_DMA_FROMDEVICE;
6448 break;
6449 case XFER_WRITE:
6450 pci_dir = PCI_DMA_TODEVICE;
6451 break;
6452 case XFER_NONE:
6453 pci_dir = PCI_DMA_NONE;
6454 break;
6455 default:
6456 pci_dir = PCI_DMA_BIDIRECTIONAL;
6457 }
6458 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6459 return -1;
6460 return 0;
6461 }
6462
6463 /*
6464 * Map (physical) PCI mem into (virtual) kernel space
6465 */
6466 static void __iomem *remap_pci_mem(ulong base, ulong size)
6467 {
6468 ulong page_base = ((ulong) base) & PAGE_MASK;
6469 ulong page_offs = ((ulong) base) - page_base;
6470 void __iomem *page_remapped = ioremap_nocache(page_base,
6471 page_offs + size);
6472
6473 return page_remapped ? (page_remapped + page_offs) : NULL;
6474 }
6475
6476 static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
6477 {
6478 return h->access.command_completed(h, q);
6479 }
6480
6481 static inline bool interrupt_pending(struct ctlr_info *h)
6482 {
6483 return h->access.intr_pending(h);
6484 }
6485
6486 static inline long interrupt_not_for_us(struct ctlr_info *h)
6487 {
6488 return (h->access.intr_pending(h) == 0) ||
6489 (h->interrupts_enabled == 0);
6490 }
6491
6492 static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6493 u32 raw_tag)
6494 {
6495 if (unlikely(tag_index >= h->nr_cmds)) {
6496 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6497 return 1;
6498 }
6499 return 0;
6500 }
6501
6502 static inline void finish_cmd(struct CommandList *c)
6503 {
6504 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
6505 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6506 || c->cmd_type == CMD_IOACCEL2))
6507 complete_scsi_command(c);
6508 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
6509 complete(c->waiting);
6510 }
6511
6512 /* process completion of an indexed ("direct lookup") command */
6513 static inline void process_indexed_cmd(struct ctlr_info *h,
6514 u32 raw_tag)
6515 {
6516 u32 tag_index;
6517 struct CommandList *c;
6518
6519 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
6520 if (!bad_tag(h, tag_index, raw_tag)) {
6521 c = h->cmd_pool + tag_index;
6522 finish_cmd(c);
6523 }
6524 }
6525
6526 /* Some controllers, like p400, will give us one interrupt
6527 * after a soft reset, even if we turned interrupts off.
6528 * Only need to check for this in the hpsa_xxx_discard_completions
6529 * functions.
6530 */
6531 static int ignore_bogus_interrupt(struct ctlr_info *h)
6532 {
6533 if (likely(!reset_devices))
6534 return 0;
6535
6536 if (likely(h->interrupts_enabled))
6537 return 0;
6538
6539 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6540 "(known firmware bug.) Ignoring.\n");
6541
6542 return 1;
6543 }
6544
6545 /*
6546 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6547 * Relies on (h-q[x] == x) being true for x such that
6548 * 0 <= x < MAX_REPLY_QUEUES.
6549 */
6550 static struct ctlr_info *queue_to_hba(u8 *queue)
6551 {
6552 return container_of((queue - *queue), struct ctlr_info, q[0]);
6553 }
6554
6555 static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6556 {
6557 struct ctlr_info *h = queue_to_hba(queue);
6558 u8 q = *(u8 *) queue;
6559 u32 raw_tag;
6560
6561 if (ignore_bogus_interrupt(h))
6562 return IRQ_NONE;
6563
6564 if (interrupt_not_for_us(h))
6565 return IRQ_NONE;
6566 h->last_intr_timestamp = get_jiffies_64();
6567 while (interrupt_pending(h)) {
6568 raw_tag = get_next_completion(h, q);
6569 while (raw_tag != FIFO_EMPTY)
6570 raw_tag = next_command(h, q);
6571 }
6572 return IRQ_HANDLED;
6573 }
6574
6575 static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
6576 {
6577 struct ctlr_info *h = queue_to_hba(queue);
6578 u32 raw_tag;
6579 u8 q = *(u8 *) queue;
6580
6581 if (ignore_bogus_interrupt(h))
6582 return IRQ_NONE;
6583
6584 h->last_intr_timestamp = get_jiffies_64();
6585 raw_tag = get_next_completion(h, q);
6586 while (raw_tag != FIFO_EMPTY)
6587 raw_tag = next_command(h, q);
6588 return IRQ_HANDLED;
6589 }
6590
6591 static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
6592 {
6593 struct ctlr_info *h = queue_to_hba((u8 *) queue);
6594 u32 raw_tag;
6595 u8 q = *(u8 *) queue;
6596
6597 if (interrupt_not_for_us(h))
6598 return IRQ_NONE;
6599 h->last_intr_timestamp = get_jiffies_64();
6600 while (interrupt_pending(h)) {
6601 raw_tag = get_next_completion(h, q);
6602 while (raw_tag != FIFO_EMPTY) {
6603 process_indexed_cmd(h, raw_tag);
6604 raw_tag = next_command(h, q);
6605 }
6606 }
6607 return IRQ_HANDLED;
6608 }
6609
6610 static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
6611 {
6612 struct ctlr_info *h = queue_to_hba(queue);
6613 u32 raw_tag;
6614 u8 q = *(u8 *) queue;
6615
6616 h->last_intr_timestamp = get_jiffies_64();
6617 raw_tag = get_next_completion(h, q);
6618 while (raw_tag != FIFO_EMPTY) {
6619 process_indexed_cmd(h, raw_tag);
6620 raw_tag = next_command(h, q);
6621 }
6622 return IRQ_HANDLED;
6623 }
6624
6625 /* Send a message CDB to the firmware. Careful, this only works
6626 * in simple mode, not performant mode due to the tag lookup.
6627 * We only ever use this immediately after a controller reset.
6628 */
6629 static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6630 unsigned char type)
6631 {
6632 struct Command {
6633 struct CommandListHeader CommandHeader;
6634 struct RequestBlock Request;
6635 struct ErrDescriptor ErrorDescriptor;
6636 };
6637 struct Command *cmd;
6638 static const size_t cmd_sz = sizeof(*cmd) +
6639 sizeof(cmd->ErrorDescriptor);
6640 dma_addr_t paddr64;
6641 __le32 paddr32;
6642 u32 tag;
6643 void __iomem *vaddr;
6644 int i, err;
6645
6646 vaddr = pci_ioremap_bar(pdev, 0);
6647 if (vaddr == NULL)
6648 return -ENOMEM;
6649
6650 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6651 * CCISS commands, so they must be allocated from the lower 4GiB of
6652 * memory.
6653 */
6654 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6655 if (err) {
6656 iounmap(vaddr);
6657 return err;
6658 }
6659
6660 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6661 if (cmd == NULL) {
6662 iounmap(vaddr);
6663 return -ENOMEM;
6664 }
6665
6666 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6667 * although there's no guarantee, we assume that the address is at
6668 * least 4-byte aligned (most likely, it's page-aligned).
6669 */
6670 paddr32 = cpu_to_le32(paddr64);
6671
6672 cmd->CommandHeader.ReplyQueue = 0;
6673 cmd->CommandHeader.SGList = 0;
6674 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
6675 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
6676 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6677
6678 cmd->Request.CDBLen = 16;
6679 cmd->Request.type_attr_dir =
6680 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
6681 cmd->Request.Timeout = 0; /* Don't time out */
6682 cmd->Request.CDB[0] = opcode;
6683 cmd->Request.CDB[1] = type;
6684 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
6685 cmd->ErrorDescriptor.Addr =
6686 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
6687 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
6688
6689 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
6690
6691 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6692 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
6693 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
6694 break;
6695 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6696 }
6697
6698 iounmap(vaddr);
6699
6700 /* we leak the DMA buffer here ... no choice since the controller could
6701 * still complete the command.
6702 */
6703 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6704 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6705 opcode, type);
6706 return -ETIMEDOUT;
6707 }
6708
6709 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6710
6711 if (tag & HPSA_ERROR_BIT) {
6712 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6713 opcode, type);
6714 return -EIO;
6715 }
6716
6717 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6718 opcode, type);
6719 return 0;
6720 }
6721
6722 #define hpsa_noop(p) hpsa_message(p, 3, 0)
6723
6724 static int hpsa_controller_hard_reset(struct pci_dev *pdev,
6725 void __iomem *vaddr, u32 use_doorbell)
6726 {
6727
6728 if (use_doorbell) {
6729 /* For everything after the P600, the PCI power state method
6730 * of resetting the controller doesn't work, so we have this
6731 * other way using the doorbell register.
6732 */
6733 dev_info(&pdev->dev, "using doorbell to reset controller\n");
6734 writel(use_doorbell, vaddr + SA5_DOORBELL);
6735
6736 /* PMC hardware guys tell us we need a 10 second delay after
6737 * doorbell reset and before any attempt to talk to the board
6738 * at all to ensure that this actually works and doesn't fall
6739 * over in some weird corner cases.
6740 */
6741 msleep(10000);
6742 } else { /* Try to do it the PCI power state way */
6743
6744 /* Quoting from the Open CISS Specification: "The Power
6745 * Management Control/Status Register (CSR) controls the power
6746 * state of the device. The normal operating state is D0,
6747 * CSR=00h. The software off state is D3, CSR=03h. To reset
6748 * the controller, place the interface device in D3 then to D0,
6749 * this causes a secondary PCI reset which will reset the
6750 * controller." */
6751
6752 int rc = 0;
6753
6754 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
6755
6756 /* enter the D3hot power management state */
6757 rc = pci_set_power_state(pdev, PCI_D3hot);
6758 if (rc)
6759 return rc;
6760
6761 msleep(500);
6762
6763 /* enter the D0 power management state */
6764 rc = pci_set_power_state(pdev, PCI_D0);
6765 if (rc)
6766 return rc;
6767
6768 /*
6769 * The P600 requires a small delay when changing states.
6770 * Otherwise we may think the board did not reset and we bail.
6771 * This for kdump only and is particular to the P600.
6772 */
6773 msleep(500);
6774 }
6775 return 0;
6776 }
6777
6778 static void init_driver_version(char *driver_version, int len)
6779 {
6780 memset(driver_version, 0, len);
6781 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
6782 }
6783
6784 static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
6785 {
6786 char *driver_version;
6787 int i, size = sizeof(cfgtable->driver_version);
6788
6789 driver_version = kmalloc(size, GFP_KERNEL);
6790 if (!driver_version)
6791 return -ENOMEM;
6792
6793 init_driver_version(driver_version, size);
6794 for (i = 0; i < size; i++)
6795 writeb(driver_version[i], &cfgtable->driver_version[i]);
6796 kfree(driver_version);
6797 return 0;
6798 }
6799
6800 static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6801 unsigned char *driver_ver)
6802 {
6803 int i;
6804
6805 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6806 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6807 }
6808
6809 static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
6810 {
6811
6812 char *driver_ver, *old_driver_ver;
6813 int rc, size = sizeof(cfgtable->driver_version);
6814
6815 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6816 if (!old_driver_ver)
6817 return -ENOMEM;
6818 driver_ver = old_driver_ver + size;
6819
6820 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6821 * should have been changed, otherwise we know the reset failed.
6822 */
6823 init_driver_version(old_driver_ver, size);
6824 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6825 rc = !memcmp(driver_ver, old_driver_ver, size);
6826 kfree(old_driver_ver);
6827 return rc;
6828 }
6829 /* This does a hard reset of the controller using PCI power management
6830 * states or the using the doorbell register.
6831 */
6832 static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
6833 {
6834 u64 cfg_offset;
6835 u32 cfg_base_addr;
6836 u64 cfg_base_addr_index;
6837 void __iomem *vaddr;
6838 unsigned long paddr;
6839 u32 misc_fw_support;
6840 int rc;
6841 struct CfgTable __iomem *cfgtable;
6842 u32 use_doorbell;
6843 u16 command_register;
6844
6845 /* For controllers as old as the P600, this is very nearly
6846 * the same thing as
6847 *
6848 * pci_save_state(pci_dev);
6849 * pci_set_power_state(pci_dev, PCI_D3hot);
6850 * pci_set_power_state(pci_dev, PCI_D0);
6851 * pci_restore_state(pci_dev);
6852 *
6853 * For controllers newer than the P600, the pci power state
6854 * method of resetting doesn't work so we have another way
6855 * using the doorbell register.
6856 */
6857
6858 if (!ctlr_is_resettable(board_id)) {
6859 dev_warn(&pdev->dev, "Controller not resettable\n");
6860 return -ENODEV;
6861 }
6862
6863 /* if controller is soft- but not hard resettable... */
6864 if (!ctlr_is_hard_resettable(board_id))
6865 return -ENOTSUPP; /* try soft reset later. */
6866
6867 /* Save the PCI command register */
6868 pci_read_config_word(pdev, 4, &command_register);
6869 pci_save_state(pdev);
6870
6871 /* find the first memory BAR, so we can find the cfg table */
6872 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6873 if (rc)
6874 return rc;
6875 vaddr = remap_pci_mem(paddr, 0x250);
6876 if (!vaddr)
6877 return -ENOMEM;
6878
6879 /* find cfgtable in order to check if reset via doorbell is supported */
6880 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6881 &cfg_base_addr_index, &cfg_offset);
6882 if (rc)
6883 goto unmap_vaddr;
6884 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6885 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6886 if (!cfgtable) {
6887 rc = -ENOMEM;
6888 goto unmap_vaddr;
6889 }
6890 rc = write_driver_ver_to_cfgtable(cfgtable);
6891 if (rc)
6892 goto unmap_cfgtable;
6893
6894 /* If reset via doorbell register is supported, use that.
6895 * There are two such methods. Favor the newest method.
6896 */
6897 misc_fw_support = readl(&cfgtable->misc_fw_support);
6898 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6899 if (use_doorbell) {
6900 use_doorbell = DOORBELL_CTLR_RESET2;
6901 } else {
6902 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6903 if (use_doorbell) {
6904 dev_warn(&pdev->dev,
6905 "Soft reset not supported. Firmware update is required.\n");
6906 rc = -ENOTSUPP; /* try soft reset */
6907 goto unmap_cfgtable;
6908 }
6909 }
6910
6911 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6912 if (rc)
6913 goto unmap_cfgtable;
6914
6915 pci_restore_state(pdev);
6916 pci_write_config_word(pdev, 4, command_register);
6917
6918 /* Some devices (notably the HP Smart Array 5i Controller)
6919 need a little pause here */
6920 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6921
6922 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6923 if (rc) {
6924 dev_warn(&pdev->dev,
6925 "Failed waiting for board to become ready after hard reset\n");
6926 goto unmap_cfgtable;
6927 }
6928
6929 rc = controller_reset_failed(vaddr);
6930 if (rc < 0)
6931 goto unmap_cfgtable;
6932 if (rc) {
6933 dev_warn(&pdev->dev, "Unable to successfully reset "
6934 "controller. Will try soft reset.\n");
6935 rc = -ENOTSUPP;
6936 } else {
6937 dev_info(&pdev->dev, "board ready after hard reset.\n");
6938 }
6939
6940 unmap_cfgtable:
6941 iounmap(cfgtable);
6942
6943 unmap_vaddr:
6944 iounmap(vaddr);
6945 return rc;
6946 }
6947
6948 /*
6949 * We cannot read the structure directly, for portability we must use
6950 * the io functions.
6951 * This is for debug only.
6952 */
6953 static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
6954 {
6955 #ifdef HPSA_DEBUG
6956 int i;
6957 char temp_name[17];
6958
6959 dev_info(dev, "Controller Configuration information\n");
6960 dev_info(dev, "------------------------------------\n");
6961 for (i = 0; i < 4; i++)
6962 temp_name[i] = readb(&(tb->Signature[i]));
6963 temp_name[4] = '\0';
6964 dev_info(dev, " Signature = %s\n", temp_name);
6965 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6966 dev_info(dev, " Transport methods supported = 0x%x\n",
6967 readl(&(tb->TransportSupport)));
6968 dev_info(dev, " Transport methods active = 0x%x\n",
6969 readl(&(tb->TransportActive)));
6970 dev_info(dev, " Requested transport Method = 0x%x\n",
6971 readl(&(tb->HostWrite.TransportRequest)));
6972 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6973 readl(&(tb->HostWrite.CoalIntDelay)));
6974 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6975 readl(&(tb->HostWrite.CoalIntCount)));
6976 dev_info(dev, " Max outstanding commands = %d\n",
6977 readl(&(tb->CmdsOutMax)));
6978 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6979 for (i = 0; i < 16; i++)
6980 temp_name[i] = readb(&(tb->ServerName[i]));
6981 temp_name[16] = '\0';
6982 dev_info(dev, " Server Name = %s\n", temp_name);
6983 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6984 readl(&(tb->HeartBeat)));
6985 #endif /* HPSA_DEBUG */
6986 }
6987
6988 static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6989 {
6990 int i, offset, mem_type, bar_type;
6991
6992 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6993 return 0;
6994 offset = 0;
6995 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6996 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6997 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6998 offset += 4;
6999 else {
7000 mem_type = pci_resource_flags(pdev, i) &
7001 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7002 switch (mem_type) {
7003 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7004 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7005 offset += 4; /* 32 bit */
7006 break;
7007 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7008 offset += 8;
7009 break;
7010 default: /* reserved in PCI 2.2 */
7011 dev_warn(&pdev->dev,
7012 "base address is invalid\n");
7013 return -1;
7014 break;
7015 }
7016 }
7017 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7018 return i + 1;
7019 }
7020 return -1;
7021 }
7022
7023 static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7024 {
7025 if (h->msix_vector) {
7026 if (h->pdev->msix_enabled)
7027 pci_disable_msix(h->pdev);
7028 h->msix_vector = 0;
7029 } else if (h->msi_vector) {
7030 if (h->pdev->msi_enabled)
7031 pci_disable_msi(h->pdev);
7032 h->msi_vector = 0;
7033 }
7034 }
7035
7036 /* If MSI/MSI-X is supported by the kernel we will try to enable it on
7037 * controllers that are capable. If not, we use legacy INTx mode.
7038 */
7039 static void hpsa_interrupt_mode(struct ctlr_info *h)
7040 {
7041 #ifdef CONFIG_PCI_MSI
7042 int err, i;
7043 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7044
7045 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7046 hpsa_msix_entries[i].vector = 0;
7047 hpsa_msix_entries[i].entry = i;
7048 }
7049
7050 /* Some boards advertise MSI but don't really support it */
7051 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7052 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
7053 goto default_int_mode;
7054 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
7055 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
7056 h->msix_vector = MAX_REPLY_QUEUES;
7057 if (h->msix_vector > num_online_cpus())
7058 h->msix_vector = num_online_cpus();
7059 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7060 1, h->msix_vector);
7061 if (err < 0) {
7062 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7063 h->msix_vector = 0;
7064 goto single_msi_mode;
7065 } else if (err < h->msix_vector) {
7066 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
7067 "available\n", err);
7068 }
7069 h->msix_vector = err;
7070 for (i = 0; i < h->msix_vector; i++)
7071 h->intr[i] = hpsa_msix_entries[i].vector;
7072 return;
7073 }
7074 single_msi_mode:
7075 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
7076 dev_info(&h->pdev->dev, "MSI capable controller\n");
7077 if (!pci_enable_msi(h->pdev))
7078 h->msi_vector = 1;
7079 else
7080 dev_warn(&h->pdev->dev, "MSI init failed\n");
7081 }
7082 default_int_mode:
7083 #endif /* CONFIG_PCI_MSI */
7084 /* if we get here we're going to use the default interrupt mode */
7085 h->intr[h->intr_mode] = h->pdev->irq;
7086 }
7087
7088 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
7089 {
7090 int i;
7091 u32 subsystem_vendor_id, subsystem_device_id;
7092
7093 subsystem_vendor_id = pdev->subsystem_vendor;
7094 subsystem_device_id = pdev->subsystem_device;
7095 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7096 subsystem_vendor_id;
7097
7098 for (i = 0; i < ARRAY_SIZE(products); i++)
7099 if (*board_id == products[i].board_id)
7100 return i;
7101
7102 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7103 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7104 !hpsa_allow_any) {
7105 dev_warn(&pdev->dev, "unrecognized board ID: "
7106 "0x%08x, ignoring.\n", *board_id);
7107 return -ENODEV;
7108 }
7109 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7110 }
7111
7112 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7113 unsigned long *memory_bar)
7114 {
7115 int i;
7116
7117 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
7118 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
7119 /* addressing mode bits already removed */
7120 *memory_bar = pci_resource_start(pdev, i);
7121 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
7122 *memory_bar);
7123 return 0;
7124 }
7125 dev_warn(&pdev->dev, "no memory BAR found\n");
7126 return -ENODEV;
7127 }
7128
7129 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7130 int wait_for_ready)
7131 {
7132 int i, iterations;
7133 u32 scratchpad;
7134 if (wait_for_ready)
7135 iterations = HPSA_BOARD_READY_ITERATIONS;
7136 else
7137 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
7138
7139 for (i = 0; i < iterations; i++) {
7140 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7141 if (wait_for_ready) {
7142 if (scratchpad == HPSA_FIRMWARE_READY)
7143 return 0;
7144 } else {
7145 if (scratchpad != HPSA_FIRMWARE_READY)
7146 return 0;
7147 }
7148 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7149 }
7150 dev_warn(&pdev->dev, "board not ready, timed out.\n");
7151 return -ENODEV;
7152 }
7153
7154 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7155 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7156 u64 *cfg_offset)
7157 {
7158 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7159 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7160 *cfg_base_addr &= (u32) 0x0000ffff;
7161 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7162 if (*cfg_base_addr_index == -1) {
7163 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7164 return -ENODEV;
7165 }
7166 return 0;
7167 }
7168
7169 static void hpsa_free_cfgtables(struct ctlr_info *h)
7170 {
7171 if (h->transtable) {
7172 iounmap(h->transtable);
7173 h->transtable = NULL;
7174 }
7175 if (h->cfgtable) {
7176 iounmap(h->cfgtable);
7177 h->cfgtable = NULL;
7178 }
7179 }
7180
7181 /* Find and map CISS config table and transfer table
7182 + * several items must be unmapped (freed) later
7183 + * */
7184 static int hpsa_find_cfgtables(struct ctlr_info *h)
7185 {
7186 u64 cfg_offset;
7187 u32 cfg_base_addr;
7188 u64 cfg_base_addr_index;
7189 u32 trans_offset;
7190 int rc;
7191
7192 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7193 &cfg_base_addr_index, &cfg_offset);
7194 if (rc)
7195 return rc;
7196 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
7197 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
7198 if (!h->cfgtable) {
7199 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
7200 return -ENOMEM;
7201 }
7202 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7203 if (rc)
7204 return rc;
7205 /* Find performant mode table. */
7206 trans_offset = readl(&h->cfgtable->TransMethodOffset);
7207 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7208 cfg_base_addr_index)+cfg_offset+trans_offset,
7209 sizeof(*h->transtable));
7210 if (!h->transtable) {
7211 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7212 hpsa_free_cfgtables(h);
7213 return -ENOMEM;
7214 }
7215 return 0;
7216 }
7217
7218 static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
7219 {
7220 #define MIN_MAX_COMMANDS 16
7221 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7222
7223 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
7224
7225 /* Limit commands in memory limited kdump scenario. */
7226 if (reset_devices && h->max_commands > 32)
7227 h->max_commands = 32;
7228
7229 if (h->max_commands < MIN_MAX_COMMANDS) {
7230 dev_warn(&h->pdev->dev,
7231 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7232 h->max_commands,
7233 MIN_MAX_COMMANDS);
7234 h->max_commands = MIN_MAX_COMMANDS;
7235 }
7236 }
7237
7238 /* If the controller reports that the total max sg entries is greater than 512,
7239 * then we know that chained SG blocks work. (Original smart arrays did not
7240 * support chained SG blocks and would return zero for max sg entries.)
7241 */
7242 static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7243 {
7244 return h->maxsgentries > 512;
7245 }
7246
7247 /* Interrogate the hardware for some limits:
7248 * max commands, max SG elements without chaining, and with chaining,
7249 * SG chain block size, etc.
7250 */
7251 static void hpsa_find_board_params(struct ctlr_info *h)
7252 {
7253 hpsa_get_max_perf_mode_cmds(h);
7254 h->nr_cmds = h->max_commands;
7255 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
7256 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
7257 if (hpsa_supports_chained_sg_blocks(h)) {
7258 /* Limit in-command s/g elements to 32 save dma'able memory. */
7259 h->max_cmd_sg_entries = 32;
7260 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
7261 h->maxsgentries--; /* save one for chain pointer */
7262 } else {
7263 /*
7264 * Original smart arrays supported at most 31 s/g entries
7265 * embedded inline in the command (trying to use more
7266 * would lock up the controller)
7267 */
7268 h->max_cmd_sg_entries = 31;
7269 h->maxsgentries = 31; /* default to traditional values */
7270 h->chainsize = 0;
7271 }
7272
7273 /* Find out what task management functions are supported and cache */
7274 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
7275 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7276 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7277 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7278 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
7279 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7280 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
7281 }
7282
7283 static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7284 {
7285 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
7286 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
7287 return false;
7288 }
7289 return true;
7290 }
7291
7292 static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
7293 {
7294 u32 driver_support;
7295
7296 driver_support = readl(&(h->cfgtable->driver_support));
7297 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7298 #ifdef CONFIG_X86
7299 driver_support |= ENABLE_SCSI_PREFETCH;
7300 #endif
7301 driver_support |= ENABLE_UNIT_ATTN;
7302 writel(driver_support, &(h->cfgtable->driver_support));
7303 }
7304
7305 /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7306 * in a prefetch beyond physical memory.
7307 */
7308 static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7309 {
7310 u32 dma_prefetch;
7311
7312 if (h->board_id != 0x3225103C)
7313 return;
7314 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7315 dma_prefetch |= 0x8000;
7316 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7317 }
7318
7319 static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
7320 {
7321 int i;
7322 u32 doorbell_value;
7323 unsigned long flags;
7324 /* wait until the clear_event_notify bit 6 is cleared by controller. */
7325 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
7326 spin_lock_irqsave(&h->lock, flags);
7327 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7328 spin_unlock_irqrestore(&h->lock, flags);
7329 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
7330 goto done;
7331 /* delay and try again */
7332 msleep(CLEAR_EVENT_WAIT_INTERVAL);
7333 }
7334 return -ENODEV;
7335 done:
7336 return 0;
7337 }
7338
7339 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
7340 {
7341 int i;
7342 u32 doorbell_value;
7343 unsigned long flags;
7344
7345 /* under certain very rare conditions, this can take awhile.
7346 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7347 * as we enter this code.)
7348 */
7349 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
7350 if (h->remove_in_progress)
7351 goto done;
7352 spin_lock_irqsave(&h->lock, flags);
7353 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7354 spin_unlock_irqrestore(&h->lock, flags);
7355 if (!(doorbell_value & CFGTBL_ChangeReq))
7356 goto done;
7357 /* delay and try again */
7358 msleep(MODE_CHANGE_WAIT_INTERVAL);
7359 }
7360 return -ENODEV;
7361 done:
7362 return 0;
7363 }
7364
7365 /* return -ENODEV or other reason on error, 0 on success */
7366 static int hpsa_enter_simple_mode(struct ctlr_info *h)
7367 {
7368 u32 trans_support;
7369
7370 trans_support = readl(&(h->cfgtable->TransportSupport));
7371 if (!(trans_support & SIMPLE_MODE))
7372 return -ENOTSUPP;
7373
7374 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
7375
7376 /* Update the field, and then ring the doorbell */
7377 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
7378 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
7379 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7380 if (hpsa_wait_for_mode_change_ack(h))
7381 goto error;
7382 print_cfg_table(&h->pdev->dev, h->cfgtable);
7383 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7384 goto error;
7385 h->transMethod = CFGTBL_Trans_Simple;
7386 return 0;
7387 error:
7388 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
7389 return -ENODEV;
7390 }
7391
7392 /* free items allocated or mapped by hpsa_pci_init */
7393 static void hpsa_free_pci_init(struct ctlr_info *h)
7394 {
7395 hpsa_free_cfgtables(h); /* pci_init 4 */
7396 iounmap(h->vaddr); /* pci_init 3 */
7397 h->vaddr = NULL;
7398 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
7399 /*
7400 * call pci_disable_device before pci_release_regions per
7401 * Documentation/PCI/pci.txt
7402 */
7403 pci_disable_device(h->pdev); /* pci_init 1 */
7404 pci_release_regions(h->pdev); /* pci_init 2 */
7405 }
7406
7407 /* several items must be freed later */
7408 static int hpsa_pci_init(struct ctlr_info *h)
7409 {
7410 int prod_index, err;
7411
7412 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7413 if (prod_index < 0)
7414 return prod_index;
7415 h->product_name = products[prod_index].product_name;
7416 h->access = *(products[prod_index].access);
7417
7418 h->needs_abort_tags_swizzled =
7419 ctlr_needs_abort_tags_swizzled(h->board_id);
7420
7421 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7422 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7423
7424 err = pci_enable_device(h->pdev);
7425 if (err) {
7426 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
7427 pci_disable_device(h->pdev);
7428 return err;
7429 }
7430
7431 err = pci_request_regions(h->pdev, HPSA);
7432 if (err) {
7433 dev_err(&h->pdev->dev,
7434 "failed to obtain PCI resources\n");
7435 pci_disable_device(h->pdev);
7436 return err;
7437 }
7438
7439 pci_set_master(h->pdev);
7440
7441 hpsa_interrupt_mode(h);
7442 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
7443 if (err)
7444 goto clean2; /* intmode+region, pci */
7445 h->vaddr = remap_pci_mem(h->paddr, 0x250);
7446 if (!h->vaddr) {
7447 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
7448 err = -ENOMEM;
7449 goto clean2; /* intmode+region, pci */
7450 }
7451 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7452 if (err)
7453 goto clean3; /* vaddr, intmode+region, pci */
7454 err = hpsa_find_cfgtables(h);
7455 if (err)
7456 goto clean3; /* vaddr, intmode+region, pci */
7457 hpsa_find_board_params(h);
7458
7459 if (!hpsa_CISS_signature_present(h)) {
7460 err = -ENODEV;
7461 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
7462 }
7463 hpsa_set_driver_support_bits(h);
7464 hpsa_p600_dma_prefetch_quirk(h);
7465 err = hpsa_enter_simple_mode(h);
7466 if (err)
7467 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
7468 return 0;
7469
7470 clean4: /* cfgtables, vaddr, intmode+region, pci */
7471 hpsa_free_cfgtables(h);
7472 clean3: /* vaddr, intmode+region, pci */
7473 iounmap(h->vaddr);
7474 h->vaddr = NULL;
7475 clean2: /* intmode+region, pci */
7476 hpsa_disable_interrupt_mode(h);
7477 /*
7478 * call pci_disable_device before pci_release_regions per
7479 * Documentation/PCI/pci.txt
7480 */
7481 pci_disable_device(h->pdev);
7482 pci_release_regions(h->pdev);
7483 return err;
7484 }
7485
7486 static void hpsa_hba_inquiry(struct ctlr_info *h)
7487 {
7488 int rc;
7489
7490 #define HBA_INQUIRY_BYTE_COUNT 64
7491 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7492 if (!h->hba_inquiry_data)
7493 return;
7494 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7495 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7496 if (rc != 0) {
7497 kfree(h->hba_inquiry_data);
7498 h->hba_inquiry_data = NULL;
7499 }
7500 }
7501
7502 static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
7503 {
7504 int rc, i;
7505 void __iomem *vaddr;
7506
7507 if (!reset_devices)
7508 return 0;
7509
7510 /* kdump kernel is loading, we don't know in which state is
7511 * the pci interface. The dev->enable_cnt is equal zero
7512 * so we call enable+disable, wait a while and switch it on.
7513 */
7514 rc = pci_enable_device(pdev);
7515 if (rc) {
7516 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7517 return -ENODEV;
7518 }
7519 pci_disable_device(pdev);
7520 msleep(260); /* a randomly chosen number */
7521 rc = pci_enable_device(pdev);
7522 if (rc) {
7523 dev_warn(&pdev->dev, "failed to enable device.\n");
7524 return -ENODEV;
7525 }
7526
7527 pci_set_master(pdev);
7528
7529 vaddr = pci_ioremap_bar(pdev, 0);
7530 if (vaddr == NULL) {
7531 rc = -ENOMEM;
7532 goto out_disable;
7533 }
7534 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7535 iounmap(vaddr);
7536
7537 /* Reset the controller with a PCI power-cycle or via doorbell */
7538 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
7539
7540 /* -ENOTSUPP here means we cannot reset the controller
7541 * but it's already (and still) up and running in
7542 * "performant mode". Or, it might be 640x, which can't reset
7543 * due to concerns about shared bbwc between 6402/6404 pair.
7544 */
7545 if (rc)
7546 goto out_disable;
7547
7548 /* Now try to get the controller to respond to a no-op */
7549 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
7550 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7551 if (hpsa_noop(pdev) == 0)
7552 break;
7553 else
7554 dev_warn(&pdev->dev, "no-op failed%s\n",
7555 (i < 11 ? "; re-trying" : ""));
7556 }
7557
7558 out_disable:
7559
7560 pci_disable_device(pdev);
7561 return rc;
7562 }
7563
7564 static void hpsa_free_cmd_pool(struct ctlr_info *h)
7565 {
7566 kfree(h->cmd_pool_bits);
7567 h->cmd_pool_bits = NULL;
7568 if (h->cmd_pool) {
7569 pci_free_consistent(h->pdev,
7570 h->nr_cmds * sizeof(struct CommandList),
7571 h->cmd_pool,
7572 h->cmd_pool_dhandle);
7573 h->cmd_pool = NULL;
7574 h->cmd_pool_dhandle = 0;
7575 }
7576 if (h->errinfo_pool) {
7577 pci_free_consistent(h->pdev,
7578 h->nr_cmds * sizeof(struct ErrorInfo),
7579 h->errinfo_pool,
7580 h->errinfo_pool_dhandle);
7581 h->errinfo_pool = NULL;
7582 h->errinfo_pool_dhandle = 0;
7583 }
7584 }
7585
7586 static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
7587 {
7588 h->cmd_pool_bits = kzalloc(
7589 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7590 sizeof(unsigned long), GFP_KERNEL);
7591 h->cmd_pool = pci_alloc_consistent(h->pdev,
7592 h->nr_cmds * sizeof(*h->cmd_pool),
7593 &(h->cmd_pool_dhandle));
7594 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7595 h->nr_cmds * sizeof(*h->errinfo_pool),
7596 &(h->errinfo_pool_dhandle));
7597 if ((h->cmd_pool_bits == NULL)
7598 || (h->cmd_pool == NULL)
7599 || (h->errinfo_pool == NULL)) {
7600 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
7601 goto clean_up;
7602 }
7603 hpsa_preinitialize_commands(h);
7604 return 0;
7605 clean_up:
7606 hpsa_free_cmd_pool(h);
7607 return -ENOMEM;
7608 }
7609
7610 static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7611 {
7612 int i, cpu;
7613
7614 cpu = cpumask_first(cpu_online_mask);
7615 for (i = 0; i < h->msix_vector; i++) {
7616 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
7617 cpu = cpumask_next(cpu, cpu_online_mask);
7618 }
7619 }
7620
7621 /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7622 static void hpsa_free_irqs(struct ctlr_info *h)
7623 {
7624 int i;
7625
7626 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7627 /* Single reply queue, only one irq to free */
7628 i = h->intr_mode;
7629 irq_set_affinity_hint(h->intr[i], NULL);
7630 free_irq(h->intr[i], &h->q[i]);
7631 h->q[i] = 0;
7632 return;
7633 }
7634
7635 for (i = 0; i < h->msix_vector; i++) {
7636 irq_set_affinity_hint(h->intr[i], NULL);
7637 free_irq(h->intr[i], &h->q[i]);
7638 h->q[i] = 0;
7639 }
7640 for (; i < MAX_REPLY_QUEUES; i++)
7641 h->q[i] = 0;
7642 }
7643
7644 /* returns 0 on success; cleans up and returns -Enn on error */
7645 static int hpsa_request_irqs(struct ctlr_info *h,
7646 irqreturn_t (*msixhandler)(int, void *),
7647 irqreturn_t (*intxhandler)(int, void *))
7648 {
7649 int rc, i;
7650
7651 /*
7652 * initialize h->q[x] = x so that interrupt handlers know which
7653 * queue to process.
7654 */
7655 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7656 h->q[i] = (u8) i;
7657
7658 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
7659 /* If performant mode and MSI-X, use multiple reply queues */
7660 for (i = 0; i < h->msix_vector; i++) {
7661 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
7662 rc = request_irq(h->intr[i], msixhandler,
7663 0, h->intrname[i],
7664 &h->q[i]);
7665 if (rc) {
7666 int j;
7667
7668 dev_err(&h->pdev->dev,
7669 "failed to get irq %d for %s\n",
7670 h->intr[i], h->devname);
7671 for (j = 0; j < i; j++) {
7672 free_irq(h->intr[j], &h->q[j]);
7673 h->q[j] = 0;
7674 }
7675 for (; j < MAX_REPLY_QUEUES; j++)
7676 h->q[j] = 0;
7677 return rc;
7678 }
7679 }
7680 hpsa_irq_affinity_hints(h);
7681 } else {
7682 /* Use single reply pool */
7683 if (h->msix_vector > 0 || h->msi_vector) {
7684 if (h->msix_vector)
7685 sprintf(h->intrname[h->intr_mode],
7686 "%s-msix", h->devname);
7687 else
7688 sprintf(h->intrname[h->intr_mode],
7689 "%s-msi", h->devname);
7690 rc = request_irq(h->intr[h->intr_mode],
7691 msixhandler, 0,
7692 h->intrname[h->intr_mode],
7693 &h->q[h->intr_mode]);
7694 } else {
7695 sprintf(h->intrname[h->intr_mode],
7696 "%s-intx", h->devname);
7697 rc = request_irq(h->intr[h->intr_mode],
7698 intxhandler, IRQF_SHARED,
7699 h->intrname[h->intr_mode],
7700 &h->q[h->intr_mode]);
7701 }
7702 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
7703 }
7704 if (rc) {
7705 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
7706 h->intr[h->intr_mode], h->devname);
7707 hpsa_free_irqs(h);
7708 return -ENODEV;
7709 }
7710 return 0;
7711 }
7712
7713 static int hpsa_kdump_soft_reset(struct ctlr_info *h)
7714 {
7715 int rc;
7716 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
7717
7718 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
7719 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7720 if (rc) {
7721 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
7722 return rc;
7723 }
7724
7725 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
7726 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7727 if (rc) {
7728 dev_warn(&h->pdev->dev, "Board failed to become ready "
7729 "after soft reset.\n");
7730 return rc;
7731 }
7732
7733 return 0;
7734 }
7735
7736 static void hpsa_free_reply_queues(struct ctlr_info *h)
7737 {
7738 int i;
7739
7740 for (i = 0; i < h->nreply_queues; i++) {
7741 if (!h->reply_queue[i].head)
7742 continue;
7743 pci_free_consistent(h->pdev,
7744 h->reply_queue_size,
7745 h->reply_queue[i].head,
7746 h->reply_queue[i].busaddr);
7747 h->reply_queue[i].head = NULL;
7748 h->reply_queue[i].busaddr = 0;
7749 }
7750 h->reply_queue_size = 0;
7751 }
7752
7753 static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7754 {
7755 hpsa_free_performant_mode(h); /* init_one 7 */
7756 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7757 hpsa_free_cmd_pool(h); /* init_one 5 */
7758 hpsa_free_irqs(h); /* init_one 4 */
7759 scsi_host_put(h->scsi_host); /* init_one 3 */
7760 h->scsi_host = NULL; /* init_one 3 */
7761 hpsa_free_pci_init(h); /* init_one 2_5 */
7762 free_percpu(h->lockup_detected); /* init_one 2 */
7763 h->lockup_detected = NULL; /* init_one 2 */
7764 if (h->resubmit_wq) {
7765 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7766 h->resubmit_wq = NULL;
7767 }
7768 if (h->rescan_ctlr_wq) {
7769 destroy_workqueue(h->rescan_ctlr_wq);
7770 h->rescan_ctlr_wq = NULL;
7771 }
7772 kfree(h); /* init_one 1 */
7773 }
7774
7775 /* Called when controller lockup detected. */
7776 static void fail_all_outstanding_cmds(struct ctlr_info *h)
7777 {
7778 int i, refcount;
7779 struct CommandList *c;
7780 int failcount = 0;
7781
7782 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
7783 for (i = 0; i < h->nr_cmds; i++) {
7784 c = h->cmd_pool + i;
7785 refcount = atomic_inc_return(&c->refcount);
7786 if (refcount > 1) {
7787 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
7788 finish_cmd(c);
7789 atomic_dec(&h->commands_outstanding);
7790 failcount++;
7791 }
7792 cmd_free(h, c);
7793 }
7794 dev_warn(&h->pdev->dev,
7795 "failed %d commands in fail_all\n", failcount);
7796 }
7797
7798 static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7799 {
7800 int cpu;
7801
7802 for_each_online_cpu(cpu) {
7803 u32 *lockup_detected;
7804 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7805 *lockup_detected = value;
7806 }
7807 wmb(); /* be sure the per-cpu variables are out to memory */
7808 }
7809
7810 static void controller_lockup_detected(struct ctlr_info *h)
7811 {
7812 unsigned long flags;
7813 u32 lockup_detected;
7814
7815 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7816 spin_lock_irqsave(&h->lock, flags);
7817 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7818 if (!lockup_detected) {
7819 /* no heartbeat, but controller gave us a zero. */
7820 dev_warn(&h->pdev->dev,
7821 "lockup detected after %d but scratchpad register is zero\n",
7822 h->heartbeat_sample_interval / HZ);
7823 lockup_detected = 0xffffffff;
7824 }
7825 set_lockup_detected_for_all_cpus(h, lockup_detected);
7826 spin_unlock_irqrestore(&h->lock, flags);
7827 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7828 lockup_detected, h->heartbeat_sample_interval / HZ);
7829 pci_disable_device(h->pdev);
7830 fail_all_outstanding_cmds(h);
7831 }
7832
7833 static int detect_controller_lockup(struct ctlr_info *h)
7834 {
7835 u64 now;
7836 u32 heartbeat;
7837 unsigned long flags;
7838
7839 now = get_jiffies_64();
7840 /* If we've received an interrupt recently, we're ok. */
7841 if (time_after64(h->last_intr_timestamp +
7842 (h->heartbeat_sample_interval), now))
7843 return false;
7844
7845 /*
7846 * If we've already checked the heartbeat recently, we're ok.
7847 * This could happen if someone sends us a signal. We
7848 * otherwise don't care about signals in this thread.
7849 */
7850 if (time_after64(h->last_heartbeat_timestamp +
7851 (h->heartbeat_sample_interval), now))
7852 return false;
7853
7854 /* If heartbeat has not changed since we last looked, we're not ok. */
7855 spin_lock_irqsave(&h->lock, flags);
7856 heartbeat = readl(&h->cfgtable->HeartBeat);
7857 spin_unlock_irqrestore(&h->lock, flags);
7858 if (h->last_heartbeat == heartbeat) {
7859 controller_lockup_detected(h);
7860 return true;
7861 }
7862
7863 /* We're ok. */
7864 h->last_heartbeat = heartbeat;
7865 h->last_heartbeat_timestamp = now;
7866 return false;
7867 }
7868
7869 static void hpsa_ack_ctlr_events(struct ctlr_info *h)
7870 {
7871 int i;
7872 char *event_type;
7873
7874 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7875 return;
7876
7877 /* Ask the controller to clear the events we're handling. */
7878 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7879 | CFGTBL_Trans_io_accel2)) &&
7880 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7881 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7882
7883 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7884 event_type = "state change";
7885 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7886 event_type = "configuration change";
7887 /* Stop sending new RAID offload reqs via the IO accelerator */
7888 scsi_block_requests(h->scsi_host);
7889 for (i = 0; i < h->ndevices; i++)
7890 h->dev[i]->offload_enabled = 0;
7891 hpsa_drain_accel_commands(h);
7892 /* Set 'accelerator path config change' bit */
7893 dev_warn(&h->pdev->dev,
7894 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7895 h->events, event_type);
7896 writel(h->events, &(h->cfgtable->clear_event_notify));
7897 /* Set the "clear event notify field update" bit 6 */
7898 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7899 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7900 hpsa_wait_for_clear_event_notify_ack(h);
7901 scsi_unblock_requests(h->scsi_host);
7902 } else {
7903 /* Acknowledge controller notification events. */
7904 writel(h->events, &(h->cfgtable->clear_event_notify));
7905 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7906 hpsa_wait_for_clear_event_notify_ack(h);
7907 #if 0
7908 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7909 hpsa_wait_for_mode_change_ack(h);
7910 #endif
7911 }
7912 return;
7913 }
7914
7915 /* Check a register on the controller to see if there are configuration
7916 * changes (added/changed/removed logical drives, etc.) which mean that
7917 * we should rescan the controller for devices.
7918 * Also check flag for driver-initiated rescan.
7919 */
7920 static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
7921 {
7922 if (h->drv_req_rescan) {
7923 h->drv_req_rescan = 0;
7924 return 1;
7925 }
7926
7927 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7928 return 0;
7929
7930 h->events = readl(&(h->cfgtable->event_notify));
7931 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7932 }
7933
7934 /*
7935 * Check if any of the offline devices have become ready
7936 */
7937 static int hpsa_offline_devices_ready(struct ctlr_info *h)
7938 {
7939 unsigned long flags;
7940 struct offline_device_entry *d;
7941 struct list_head *this, *tmp;
7942
7943 spin_lock_irqsave(&h->offline_device_lock, flags);
7944 list_for_each_safe(this, tmp, &h->offline_device_list) {
7945 d = list_entry(this, struct offline_device_entry,
7946 offline_list);
7947 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7948 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7949 spin_lock_irqsave(&h->offline_device_lock, flags);
7950 list_del(&d->offline_list);
7951 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7952 return 1;
7953 }
7954 spin_lock_irqsave(&h->offline_device_lock, flags);
7955 }
7956 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7957 return 0;
7958 }
7959
7960 static void hpsa_rescan_ctlr_worker(struct work_struct *work)
7961 {
7962 unsigned long flags;
7963 struct ctlr_info *h = container_of(to_delayed_work(work),
7964 struct ctlr_info, rescan_ctlr_work);
7965
7966
7967 if (h->remove_in_progress)
7968 return;
7969
7970 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7971 scsi_host_get(h->scsi_host);
7972 hpsa_ack_ctlr_events(h);
7973 hpsa_scan_start(h->scsi_host);
7974 scsi_host_put(h->scsi_host);
7975 }
7976 spin_lock_irqsave(&h->lock, flags);
7977 if (!h->remove_in_progress)
7978 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7979 h->heartbeat_sample_interval);
7980 spin_unlock_irqrestore(&h->lock, flags);
7981 }
7982
7983 static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7984 {
7985 unsigned long flags;
7986 struct ctlr_info *h = container_of(to_delayed_work(work),
7987 struct ctlr_info, monitor_ctlr_work);
7988
7989 detect_controller_lockup(h);
7990 if (lockup_detected(h))
7991 return;
7992
7993 spin_lock_irqsave(&h->lock, flags);
7994 if (!h->remove_in_progress)
7995 schedule_delayed_work(&h->monitor_ctlr_work,
7996 h->heartbeat_sample_interval);
7997 spin_unlock_irqrestore(&h->lock, flags);
7998 }
7999
8000 static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8001 char *name)
8002 {
8003 struct workqueue_struct *wq = NULL;
8004
8005 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
8006 if (!wq)
8007 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8008
8009 return wq;
8010 }
8011
8012 static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8013 {
8014 int dac, rc;
8015 struct ctlr_info *h;
8016 int try_soft_reset = 0;
8017 unsigned long flags;
8018 u32 board_id;
8019
8020 if (number_of_controllers == 0)
8021 printk(KERN_INFO DRIVER_NAME "\n");
8022
8023 rc = hpsa_lookup_board_id(pdev, &board_id);
8024 if (rc < 0) {
8025 dev_warn(&pdev->dev, "Board ID not found\n");
8026 return rc;
8027 }
8028
8029 rc = hpsa_init_reset_devices(pdev, board_id);
8030 if (rc) {
8031 if (rc != -ENOTSUPP)
8032 return rc;
8033 /* If the reset fails in a particular way (it has no way to do
8034 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8035 * a soft reset once we get the controller configured up to the
8036 * point that it can accept a command.
8037 */
8038 try_soft_reset = 1;
8039 rc = 0;
8040 }
8041
8042 reinit_after_soft_reset:
8043
8044 /* Command structures must be aligned on a 32-byte boundary because
8045 * the 5 lower bits of the address are used by the hardware. and by
8046 * the driver. See comments in hpsa.h for more info.
8047 */
8048 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
8049 h = kzalloc(sizeof(*h), GFP_KERNEL);
8050 if (!h) {
8051 dev_err(&pdev->dev, "Failed to allocate controller head\n");
8052 return -ENOMEM;
8053 }
8054
8055 h->pdev = pdev;
8056
8057 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
8058 INIT_LIST_HEAD(&h->offline_device_list);
8059 spin_lock_init(&h->lock);
8060 spin_lock_init(&h->offline_device_lock);
8061 spin_lock_init(&h->scan_lock);
8062 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
8063 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
8064
8065 /* Allocate and clear per-cpu variable lockup_detected */
8066 h->lockup_detected = alloc_percpu(u32);
8067 if (!h->lockup_detected) {
8068 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
8069 rc = -ENOMEM;
8070 goto clean1; /* aer/h */
8071 }
8072 set_lockup_detected_for_all_cpus(h, 0);
8073
8074 rc = hpsa_pci_init(h);
8075 if (rc)
8076 goto clean2; /* lu, aer/h */
8077
8078 /* relies on h-> settings made by hpsa_pci_init, including
8079 * interrupt_mode h->intr */
8080 rc = hpsa_scsi_host_alloc(h);
8081 if (rc)
8082 goto clean2_5; /* pci, lu, aer/h */
8083
8084 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
8085 h->ctlr = number_of_controllers;
8086 number_of_controllers++;
8087
8088 /* configure PCI DMA stuff */
8089 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8090 if (rc == 0) {
8091 dac = 1;
8092 } else {
8093 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8094 if (rc == 0) {
8095 dac = 0;
8096 } else {
8097 dev_err(&pdev->dev, "no suitable DMA available\n");
8098 goto clean3; /* shost, pci, lu, aer/h */
8099 }
8100 }
8101
8102 /* make sure the board interrupts are off */
8103 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8104
8105 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8106 if (rc)
8107 goto clean3; /* shost, pci, lu, aer/h */
8108 rc = hpsa_alloc_cmd_pool(h);
8109 if (rc)
8110 goto clean4; /* irq, shost, pci, lu, aer/h */
8111 rc = hpsa_alloc_sg_chain_blocks(h);
8112 if (rc)
8113 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
8114 init_waitqueue_head(&h->scan_wait_queue);
8115 init_waitqueue_head(&h->abort_cmd_wait_queue);
8116 init_waitqueue_head(&h->event_sync_wait_queue);
8117 mutex_init(&h->reset_mutex);
8118 h->scan_finished = 1; /* no scan currently in progress */
8119
8120 pci_set_drvdata(pdev, h);
8121 h->ndevices = 0;
8122
8123 spin_lock_init(&h->devlock);
8124 rc = hpsa_put_ctlr_into_performant_mode(h);
8125 if (rc)
8126 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8127
8128 /* hook into SCSI subsystem */
8129 rc = hpsa_scsi_add_host(h);
8130 if (rc)
8131 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8132
8133 /* create the resubmit workqueue */
8134 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8135 if (!h->rescan_ctlr_wq) {
8136 rc = -ENOMEM;
8137 goto clean7;
8138 }
8139
8140 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8141 if (!h->resubmit_wq) {
8142 rc = -ENOMEM;
8143 goto clean7; /* aer/h */
8144 }
8145
8146 /*
8147 * At this point, the controller is ready to take commands.
8148 * Now, if reset_devices and the hard reset didn't work, try
8149 * the soft reset and see if that works.
8150 */
8151 if (try_soft_reset) {
8152
8153 /* This is kind of gross. We may or may not get a completion
8154 * from the soft reset command, and if we do, then the value
8155 * from the fifo may or may not be valid. So, we wait 10 secs
8156 * after the reset throwing away any completions we get during
8157 * that time. Unregister the interrupt handler and register
8158 * fake ones to scoop up any residual completions.
8159 */
8160 spin_lock_irqsave(&h->lock, flags);
8161 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8162 spin_unlock_irqrestore(&h->lock, flags);
8163 hpsa_free_irqs(h);
8164 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
8165 hpsa_intx_discard_completions);
8166 if (rc) {
8167 dev_warn(&h->pdev->dev,
8168 "Failed to request_irq after soft reset.\n");
8169 /*
8170 * cannot goto clean7 or free_irqs will be called
8171 * again. Instead, do its work
8172 */
8173 hpsa_free_performant_mode(h); /* clean7 */
8174 hpsa_free_sg_chain_blocks(h); /* clean6 */
8175 hpsa_free_cmd_pool(h); /* clean5 */
8176 /*
8177 * skip hpsa_free_irqs(h) clean4 since that
8178 * was just called before request_irqs failed
8179 */
8180 goto clean3;
8181 }
8182
8183 rc = hpsa_kdump_soft_reset(h);
8184 if (rc)
8185 /* Neither hard nor soft reset worked, we're hosed. */
8186 goto clean7;
8187
8188 dev_info(&h->pdev->dev, "Board READY.\n");
8189 dev_info(&h->pdev->dev,
8190 "Waiting for stale completions to drain.\n");
8191 h->access.set_intr_mask(h, HPSA_INTR_ON);
8192 msleep(10000);
8193 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8194
8195 rc = controller_reset_failed(h->cfgtable);
8196 if (rc)
8197 dev_info(&h->pdev->dev,
8198 "Soft reset appears to have failed.\n");
8199
8200 /* since the controller's reset, we have to go back and re-init
8201 * everything. Easiest to just forget what we've done and do it
8202 * all over again.
8203 */
8204 hpsa_undo_allocations_after_kdump_soft_reset(h);
8205 try_soft_reset = 0;
8206 if (rc)
8207 /* don't goto clean, we already unallocated */
8208 return -ENODEV;
8209
8210 goto reinit_after_soft_reset;
8211 }
8212
8213 /* Enable Accelerated IO path at driver layer */
8214 h->acciopath_status = 1;
8215
8216
8217 /* Turn the interrupts on so we can service requests */
8218 h->access.set_intr_mask(h, HPSA_INTR_ON);
8219
8220 hpsa_hba_inquiry(h);
8221
8222 /* Monitor the controller for firmware lockups */
8223 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8224 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8225 schedule_delayed_work(&h->monitor_ctlr_work,
8226 h->heartbeat_sample_interval);
8227 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8228 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8229 h->heartbeat_sample_interval);
8230 return 0;
8231
8232 clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8233 hpsa_free_performant_mode(h);
8234 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8235 clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
8236 hpsa_free_sg_chain_blocks(h);
8237 clean5: /* cmd, irq, shost, pci, lu, aer/h */
8238 hpsa_free_cmd_pool(h);
8239 clean4: /* irq, shost, pci, lu, aer/h */
8240 hpsa_free_irqs(h);
8241 clean3: /* shost, pci, lu, aer/h */
8242 scsi_host_put(h->scsi_host);
8243 h->scsi_host = NULL;
8244 clean2_5: /* pci, lu, aer/h */
8245 hpsa_free_pci_init(h);
8246 clean2: /* lu, aer/h */
8247 if (h->lockup_detected) {
8248 free_percpu(h->lockup_detected);
8249 h->lockup_detected = NULL;
8250 }
8251 clean1: /* wq/aer/h */
8252 if (h->resubmit_wq) {
8253 destroy_workqueue(h->resubmit_wq);
8254 h->resubmit_wq = NULL;
8255 }
8256 if (h->rescan_ctlr_wq) {
8257 destroy_workqueue(h->rescan_ctlr_wq);
8258 h->rescan_ctlr_wq = NULL;
8259 }
8260 kfree(h);
8261 return rc;
8262 }
8263
8264 static void hpsa_flush_cache(struct ctlr_info *h)
8265 {
8266 char *flush_buf;
8267 struct CommandList *c;
8268 int rc;
8269
8270 if (unlikely(lockup_detected(h)))
8271 return;
8272 flush_buf = kzalloc(4, GFP_KERNEL);
8273 if (!flush_buf)
8274 return;
8275
8276 c = cmd_alloc(h);
8277
8278 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8279 RAID_CTLR_LUNID, TYPE_CMD)) {
8280 goto out;
8281 }
8282 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8283 PCI_DMA_TODEVICE, NO_TIMEOUT);
8284 if (rc)
8285 goto out;
8286 if (c->err_info->CommandStatus != 0)
8287 out:
8288 dev_warn(&h->pdev->dev,
8289 "error flushing cache on controller\n");
8290 cmd_free(h, c);
8291 kfree(flush_buf);
8292 }
8293
8294 static void hpsa_shutdown(struct pci_dev *pdev)
8295 {
8296 struct ctlr_info *h;
8297
8298 h = pci_get_drvdata(pdev);
8299 /* Turn board interrupts off and send the flush cache command
8300 * sendcmd will turn off interrupt, and send the flush...
8301 * To write all data in the battery backed cache to disks
8302 */
8303 hpsa_flush_cache(h);
8304 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8305 hpsa_free_irqs(h); /* init_one 4 */
8306 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
8307 }
8308
8309 static void hpsa_free_device_info(struct ctlr_info *h)
8310 {
8311 int i;
8312
8313 for (i = 0; i < h->ndevices; i++) {
8314 kfree(h->dev[i]);
8315 h->dev[i] = NULL;
8316 }
8317 }
8318
8319 static void hpsa_remove_one(struct pci_dev *pdev)
8320 {
8321 struct ctlr_info *h;
8322 unsigned long flags;
8323
8324 if (pci_get_drvdata(pdev) == NULL) {
8325 dev_err(&pdev->dev, "unable to remove device\n");
8326 return;
8327 }
8328 h = pci_get_drvdata(pdev);
8329
8330 /* Get rid of any controller monitoring work items */
8331 spin_lock_irqsave(&h->lock, flags);
8332 h->remove_in_progress = 1;
8333 spin_unlock_irqrestore(&h->lock, flags);
8334 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8335 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8336 destroy_workqueue(h->rescan_ctlr_wq);
8337 destroy_workqueue(h->resubmit_wq);
8338
8339 /*
8340 * Call before disabling interrupts.
8341 * scsi_remove_host can trigger I/O operations especially
8342 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8343 * operations which cannot complete and will hang the system.
8344 */
8345 if (h->scsi_host)
8346 scsi_remove_host(h->scsi_host); /* init_one 8 */
8347 /* includes hpsa_free_irqs - init_one 4 */
8348 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
8349 hpsa_shutdown(pdev);
8350
8351 hpsa_free_device_info(h); /* scan */
8352
8353 kfree(h->hba_inquiry_data); /* init_one 10 */
8354 h->hba_inquiry_data = NULL; /* init_one 10 */
8355 hpsa_free_ioaccel2_sg_chain_blocks(h);
8356 hpsa_free_performant_mode(h); /* init_one 7 */
8357 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8358 hpsa_free_cmd_pool(h); /* init_one 5 */
8359
8360 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
8361
8362 scsi_host_put(h->scsi_host); /* init_one 3 */
8363 h->scsi_host = NULL; /* init_one 3 */
8364
8365 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
8366 hpsa_free_pci_init(h); /* init_one 2.5 */
8367
8368 free_percpu(h->lockup_detected); /* init_one 2 */
8369 h->lockup_detected = NULL; /* init_one 2 */
8370 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8371 kfree(h); /* init_one 1 */
8372 }
8373
8374 static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8375 __attribute__((unused)) pm_message_t state)
8376 {
8377 return -ENOSYS;
8378 }
8379
8380 static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8381 {
8382 return -ENOSYS;
8383 }
8384
8385 static struct pci_driver hpsa_pci_driver = {
8386 .name = HPSA,
8387 .probe = hpsa_init_one,
8388 .remove = hpsa_remove_one,
8389 .id_table = hpsa_pci_device_id, /* id_table */
8390 .shutdown = hpsa_shutdown,
8391 .suspend = hpsa_suspend,
8392 .resume = hpsa_resume,
8393 };
8394
8395 /* Fill in bucket_map[], given nsgs (the max number of
8396 * scatter gather elements supported) and bucket[],
8397 * which is an array of 8 integers. The bucket[] array
8398 * contains 8 different DMA transfer sizes (in 16
8399 * byte increments) which the controller uses to fetch
8400 * commands. This function fills in bucket_map[], which
8401 * maps a given number of scatter gather elements to one of
8402 * the 8 DMA transfer sizes. The point of it is to allow the
8403 * controller to only do as much DMA as needed to fetch the
8404 * command, with the DMA transfer size encoded in the lower
8405 * bits of the command address.
8406 */
8407 static void calc_bucket_map(int bucket[], int num_buckets,
8408 int nsgs, int min_blocks, u32 *bucket_map)
8409 {
8410 int i, j, b, size;
8411
8412 /* Note, bucket_map must have nsgs+1 entries. */
8413 for (i = 0; i <= nsgs; i++) {
8414 /* Compute size of a command with i SG entries */
8415 size = i + min_blocks;
8416 b = num_buckets; /* Assume the biggest bucket */
8417 /* Find the bucket that is just big enough */
8418 for (j = 0; j < num_buckets; j++) {
8419 if (bucket[j] >= size) {
8420 b = j;
8421 break;
8422 }
8423 }
8424 /* for a command with i SG entries, use bucket b. */
8425 bucket_map[i] = b;
8426 }
8427 }
8428
8429 /*
8430 * return -ENODEV on err, 0 on success (or no action)
8431 * allocates numerous items that must be freed later
8432 */
8433 static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
8434 {
8435 int i;
8436 unsigned long register_value;
8437 unsigned long transMethod = CFGTBL_Trans_Performant |
8438 (trans_support & CFGTBL_Trans_use_short_tags) |
8439 CFGTBL_Trans_enable_directed_msix |
8440 (trans_support & (CFGTBL_Trans_io_accel1 |
8441 CFGTBL_Trans_io_accel2));
8442 struct access_method access = SA5_performant_access;
8443
8444 /* This is a bit complicated. There are 8 registers on
8445 * the controller which we write to to tell it 8 different
8446 * sizes of commands which there may be. It's a way of
8447 * reducing the DMA done to fetch each command. Encoded into
8448 * each command's tag are 3 bits which communicate to the controller
8449 * which of the eight sizes that command fits within. The size of
8450 * each command depends on how many scatter gather entries there are.
8451 * Each SG entry requires 16 bytes. The eight registers are programmed
8452 * with the number of 16-byte blocks a command of that size requires.
8453 * The smallest command possible requires 5 such 16 byte blocks.
8454 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
8455 * blocks. Note, this only extends to the SG entries contained
8456 * within the command block, and does not extend to chained blocks
8457 * of SG elements. bft[] contains the eight values we write to
8458 * the registers. They are not evenly distributed, but have more
8459 * sizes for small commands, and fewer sizes for larger commands.
8460 */
8461 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
8462 #define MIN_IOACCEL2_BFT_ENTRY 5
8463 #define HPSA_IOACCEL2_HEADER_SZ 4
8464 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8465 13, 14, 15, 16, 17, 18, 19,
8466 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8467 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8468 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8469 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8470 16 * MIN_IOACCEL2_BFT_ENTRY);
8471 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
8472 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
8473 /* 5 = 1 s/g entry or 4k
8474 * 6 = 2 s/g entry or 8k
8475 * 8 = 4 s/g entry or 16k
8476 * 10 = 6 s/g entry or 24k
8477 */
8478
8479 /* If the controller supports either ioaccel method then
8480 * we can also use the RAID stack submit path that does not
8481 * perform the superfluous readl() after each command submission.
8482 */
8483 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8484 access = SA5_performant_access_no_read;
8485
8486 /* Controller spec: zero out this buffer. */
8487 for (i = 0; i < h->nreply_queues; i++)
8488 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
8489
8490 bft[7] = SG_ENTRIES_IN_CMD + 4;
8491 calc_bucket_map(bft, ARRAY_SIZE(bft),
8492 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
8493 for (i = 0; i < 8; i++)
8494 writel(bft[i], &h->transtable->BlockFetch[i]);
8495
8496 /* size of controller ring buffer */
8497 writel(h->max_commands, &h->transtable->RepQSize);
8498 writel(h->nreply_queues, &h->transtable->RepQCount);
8499 writel(0, &h->transtable->RepQCtrAddrLow32);
8500 writel(0, &h->transtable->RepQCtrAddrHigh32);
8501
8502 for (i = 0; i < h->nreply_queues; i++) {
8503 writel(0, &h->transtable->RepQAddr[i].upper);
8504 writel(h->reply_queue[i].busaddr,
8505 &h->transtable->RepQAddr[i].lower);
8506 }
8507
8508 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
8509 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8510 /*
8511 * enable outbound interrupt coalescing in accelerator mode;
8512 */
8513 if (trans_support & CFGTBL_Trans_io_accel1) {
8514 access = SA5_ioaccel_mode1_access;
8515 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8516 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8517 } else {
8518 if (trans_support & CFGTBL_Trans_io_accel2) {
8519 access = SA5_ioaccel_mode2_access;
8520 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8521 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8522 }
8523 }
8524 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8525 if (hpsa_wait_for_mode_change_ack(h)) {
8526 dev_err(&h->pdev->dev,
8527 "performant mode problem - doorbell timeout\n");
8528 return -ENODEV;
8529 }
8530 register_value = readl(&(h->cfgtable->TransportActive));
8531 if (!(register_value & CFGTBL_Trans_Performant)) {
8532 dev_err(&h->pdev->dev,
8533 "performant mode problem - transport not active\n");
8534 return -ENODEV;
8535 }
8536 /* Change the access methods to the performant access methods */
8537 h->access = access;
8538 h->transMethod = transMethod;
8539
8540 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8541 (trans_support & CFGTBL_Trans_io_accel2)))
8542 return 0;
8543
8544 if (trans_support & CFGTBL_Trans_io_accel1) {
8545 /* Set up I/O accelerator mode */
8546 for (i = 0; i < h->nreply_queues; i++) {
8547 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8548 h->reply_queue[i].current_entry =
8549 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8550 }
8551 bft[7] = h->ioaccel_maxsg + 8;
8552 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8553 h->ioaccel1_blockFetchTable);
8554
8555 /* initialize all reply queue entries to unused */
8556 for (i = 0; i < h->nreply_queues; i++)
8557 memset(h->reply_queue[i].head,
8558 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8559 h->reply_queue_size);
8560
8561 /* set all the constant fields in the accelerator command
8562 * frames once at init time to save CPU cycles later.
8563 */
8564 for (i = 0; i < h->nr_cmds; i++) {
8565 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8566
8567 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8568 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8569 (i * sizeof(struct ErrorInfo)));
8570 cp->err_info_len = sizeof(struct ErrorInfo);
8571 cp->sgl_offset = IOACCEL1_SGLOFFSET;
8572 cp->host_context_flags =
8573 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
8574 cp->timeout_sec = 0;
8575 cp->ReplyQueue = 0;
8576 cp->tag =
8577 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
8578 cp->host_addr =
8579 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
8580 (i * sizeof(struct io_accel1_cmd)));
8581 }
8582 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8583 u64 cfg_offset, cfg_base_addr_index;
8584 u32 bft2_offset, cfg_base_addr;
8585 int rc;
8586
8587 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8588 &cfg_base_addr_index, &cfg_offset);
8589 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8590 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8591 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8592 4, h->ioaccel2_blockFetchTable);
8593 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8594 BUILD_BUG_ON(offsetof(struct CfgTable,
8595 io_accel_request_size_offset) != 0xb8);
8596 h->ioaccel2_bft2_regs =
8597 remap_pci_mem(pci_resource_start(h->pdev,
8598 cfg_base_addr_index) +
8599 cfg_offset + bft2_offset,
8600 ARRAY_SIZE(bft2) *
8601 sizeof(*h->ioaccel2_bft2_regs));
8602 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8603 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
8604 }
8605 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8606 if (hpsa_wait_for_mode_change_ack(h)) {
8607 dev_err(&h->pdev->dev,
8608 "performant mode problem - enabling ioaccel mode\n");
8609 return -ENODEV;
8610 }
8611 return 0;
8612 }
8613
8614 /* Free ioaccel1 mode command blocks and block fetch table */
8615 static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8616 {
8617 if (h->ioaccel_cmd_pool) {
8618 pci_free_consistent(h->pdev,
8619 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8620 h->ioaccel_cmd_pool,
8621 h->ioaccel_cmd_pool_dhandle);
8622 h->ioaccel_cmd_pool = NULL;
8623 h->ioaccel_cmd_pool_dhandle = 0;
8624 }
8625 kfree(h->ioaccel1_blockFetchTable);
8626 h->ioaccel1_blockFetchTable = NULL;
8627 }
8628
8629 /* Allocate ioaccel1 mode command blocks and block fetch table */
8630 static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8631 {
8632 h->ioaccel_maxsg =
8633 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8634 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8635 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8636
8637 /* Command structures must be aligned on a 128-byte boundary
8638 * because the 7 lower bits of the address are used by the
8639 * hardware.
8640 */
8641 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8642 IOACCEL1_COMMANDLIST_ALIGNMENT);
8643 h->ioaccel_cmd_pool =
8644 pci_alloc_consistent(h->pdev,
8645 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8646 &(h->ioaccel_cmd_pool_dhandle));
8647
8648 h->ioaccel1_blockFetchTable =
8649 kmalloc(((h->ioaccel_maxsg + 1) *
8650 sizeof(u32)), GFP_KERNEL);
8651
8652 if ((h->ioaccel_cmd_pool == NULL) ||
8653 (h->ioaccel1_blockFetchTable == NULL))
8654 goto clean_up;
8655
8656 memset(h->ioaccel_cmd_pool, 0,
8657 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8658 return 0;
8659
8660 clean_up:
8661 hpsa_free_ioaccel1_cmd_and_bft(h);
8662 return -ENOMEM;
8663 }
8664
8665 /* Free ioaccel2 mode command blocks and block fetch table */
8666 static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8667 {
8668 hpsa_free_ioaccel2_sg_chain_blocks(h);
8669
8670 if (h->ioaccel2_cmd_pool) {
8671 pci_free_consistent(h->pdev,
8672 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8673 h->ioaccel2_cmd_pool,
8674 h->ioaccel2_cmd_pool_dhandle);
8675 h->ioaccel2_cmd_pool = NULL;
8676 h->ioaccel2_cmd_pool_dhandle = 0;
8677 }
8678 kfree(h->ioaccel2_blockFetchTable);
8679 h->ioaccel2_blockFetchTable = NULL;
8680 }
8681
8682 /* Allocate ioaccel2 mode command blocks and block fetch table */
8683 static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8684 {
8685 int rc;
8686
8687 /* Allocate ioaccel2 mode command blocks and block fetch table */
8688
8689 h->ioaccel_maxsg =
8690 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8691 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8692 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8693
8694 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8695 IOACCEL2_COMMANDLIST_ALIGNMENT);
8696 h->ioaccel2_cmd_pool =
8697 pci_alloc_consistent(h->pdev,
8698 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8699 &(h->ioaccel2_cmd_pool_dhandle));
8700
8701 h->ioaccel2_blockFetchTable =
8702 kmalloc(((h->ioaccel_maxsg + 1) *
8703 sizeof(u32)), GFP_KERNEL);
8704
8705 if ((h->ioaccel2_cmd_pool == NULL) ||
8706 (h->ioaccel2_blockFetchTable == NULL)) {
8707 rc = -ENOMEM;
8708 goto clean_up;
8709 }
8710
8711 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8712 if (rc)
8713 goto clean_up;
8714
8715 memset(h->ioaccel2_cmd_pool, 0,
8716 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8717 return 0;
8718
8719 clean_up:
8720 hpsa_free_ioaccel2_cmd_and_bft(h);
8721 return rc;
8722 }
8723
8724 /* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8725 static void hpsa_free_performant_mode(struct ctlr_info *h)
8726 {
8727 kfree(h->blockFetchTable);
8728 h->blockFetchTable = NULL;
8729 hpsa_free_reply_queues(h);
8730 hpsa_free_ioaccel1_cmd_and_bft(h);
8731 hpsa_free_ioaccel2_cmd_and_bft(h);
8732 }
8733
8734 /* return -ENODEV on error, 0 on success (or no action)
8735 * allocates numerous items that must be freed later
8736 */
8737 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
8738 {
8739 u32 trans_support;
8740 unsigned long transMethod = CFGTBL_Trans_Performant |
8741 CFGTBL_Trans_use_short_tags;
8742 int i, rc;
8743
8744 if (hpsa_simple_mode)
8745 return 0;
8746
8747 trans_support = readl(&(h->cfgtable->TransportSupport));
8748 if (!(trans_support & PERFORMANT_MODE))
8749 return 0;
8750
8751 /* Check for I/O accelerator mode support */
8752 if (trans_support & CFGTBL_Trans_io_accel1) {
8753 transMethod |= CFGTBL_Trans_io_accel1 |
8754 CFGTBL_Trans_enable_directed_msix;
8755 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8756 if (rc)
8757 return rc;
8758 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8759 transMethod |= CFGTBL_Trans_io_accel2 |
8760 CFGTBL_Trans_enable_directed_msix;
8761 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8762 if (rc)
8763 return rc;
8764 }
8765
8766 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
8767 hpsa_get_max_perf_mode_cmds(h);
8768 /* Performant mode ring buffer and supporting data structures */
8769 h->reply_queue_size = h->max_commands * sizeof(u64);
8770
8771 for (i = 0; i < h->nreply_queues; i++) {
8772 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8773 h->reply_queue_size,
8774 &(h->reply_queue[i].busaddr));
8775 if (!h->reply_queue[i].head) {
8776 rc = -ENOMEM;
8777 goto clean1; /* rq, ioaccel */
8778 }
8779 h->reply_queue[i].size = h->max_commands;
8780 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8781 h->reply_queue[i].current_entry = 0;
8782 }
8783
8784 /* Need a block fetch table for performant mode */
8785 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
8786 sizeof(u32)), GFP_KERNEL);
8787 if (!h->blockFetchTable) {
8788 rc = -ENOMEM;
8789 goto clean1; /* rq, ioaccel */
8790 }
8791
8792 rc = hpsa_enter_performant_mode(h, trans_support);
8793 if (rc)
8794 goto clean2; /* bft, rq, ioaccel */
8795 return 0;
8796
8797 clean2: /* bft, rq, ioaccel */
8798 kfree(h->blockFetchTable);
8799 h->blockFetchTable = NULL;
8800 clean1: /* rq, ioaccel */
8801 hpsa_free_reply_queues(h);
8802 hpsa_free_ioaccel1_cmd_and_bft(h);
8803 hpsa_free_ioaccel2_cmd_and_bft(h);
8804 return rc;
8805 }
8806
8807 static int is_accelerated_cmd(struct CommandList *c)
8808 {
8809 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8810 }
8811
8812 static void hpsa_drain_accel_commands(struct ctlr_info *h)
8813 {
8814 struct CommandList *c = NULL;
8815 int i, accel_cmds_out;
8816 int refcount;
8817
8818 do { /* wait for all outstanding ioaccel commands to drain out */
8819 accel_cmds_out = 0;
8820 for (i = 0; i < h->nr_cmds; i++) {
8821 c = h->cmd_pool + i;
8822 refcount = atomic_inc_return(&c->refcount);
8823 if (refcount > 1) /* Command is allocated */
8824 accel_cmds_out += is_accelerated_cmd(c);
8825 cmd_free(h, c);
8826 }
8827 if (accel_cmds_out <= 0)
8828 break;
8829 msleep(100);
8830 } while (1);
8831 }
8832
8833 /*
8834 * This is it. Register the PCI driver information for the cards we control
8835 * the OS will call our registered routines when it finds one of our cards.
8836 */
8837 static int __init hpsa_init(void)
8838 {
8839 return pci_register_driver(&hpsa_pci_driver);
8840 }
8841
8842 static void __exit hpsa_cleanup(void)
8843 {
8844 pci_unregister_driver(&hpsa_pci_driver);
8845 }
8846
8847 static void __attribute__((unused)) verify_offsets(void)
8848 {
8849 #define VERIFY_OFFSET(member, offset) \
8850 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8851
8852 VERIFY_OFFSET(structure_size, 0);
8853 VERIFY_OFFSET(volume_blk_size, 4);
8854 VERIFY_OFFSET(volume_blk_cnt, 8);
8855 VERIFY_OFFSET(phys_blk_shift, 16);
8856 VERIFY_OFFSET(parity_rotation_shift, 17);
8857 VERIFY_OFFSET(strip_size, 18);
8858 VERIFY_OFFSET(disk_starting_blk, 20);
8859 VERIFY_OFFSET(disk_blk_cnt, 28);
8860 VERIFY_OFFSET(data_disks_per_row, 36);
8861 VERIFY_OFFSET(metadata_disks_per_row, 38);
8862 VERIFY_OFFSET(row_cnt, 40);
8863 VERIFY_OFFSET(layout_map_count, 42);
8864 VERIFY_OFFSET(flags, 44);
8865 VERIFY_OFFSET(dekindex, 46);
8866 /* VERIFY_OFFSET(reserved, 48 */
8867 VERIFY_OFFSET(data, 64);
8868
8869 #undef VERIFY_OFFSET
8870
8871 #define VERIFY_OFFSET(member, offset) \
8872 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8873
8874 VERIFY_OFFSET(IU_type, 0);
8875 VERIFY_OFFSET(direction, 1);
8876 VERIFY_OFFSET(reply_queue, 2);
8877 /* VERIFY_OFFSET(reserved1, 3); */
8878 VERIFY_OFFSET(scsi_nexus, 4);
8879 VERIFY_OFFSET(Tag, 8);
8880 VERIFY_OFFSET(cdb, 16);
8881 VERIFY_OFFSET(cciss_lun, 32);
8882 VERIFY_OFFSET(data_len, 40);
8883 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8884 VERIFY_OFFSET(sg_count, 45);
8885 /* VERIFY_OFFSET(reserved3 */
8886 VERIFY_OFFSET(err_ptr, 48);
8887 VERIFY_OFFSET(err_len, 56);
8888 /* VERIFY_OFFSET(reserved4 */
8889 VERIFY_OFFSET(sg, 64);
8890
8891 #undef VERIFY_OFFSET
8892
8893 #define VERIFY_OFFSET(member, offset) \
8894 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8895
8896 VERIFY_OFFSET(dev_handle, 0x00);
8897 VERIFY_OFFSET(reserved1, 0x02);
8898 VERIFY_OFFSET(function, 0x03);
8899 VERIFY_OFFSET(reserved2, 0x04);
8900 VERIFY_OFFSET(err_info, 0x0C);
8901 VERIFY_OFFSET(reserved3, 0x10);
8902 VERIFY_OFFSET(err_info_len, 0x12);
8903 VERIFY_OFFSET(reserved4, 0x13);
8904 VERIFY_OFFSET(sgl_offset, 0x14);
8905 VERIFY_OFFSET(reserved5, 0x15);
8906 VERIFY_OFFSET(transfer_len, 0x1C);
8907 VERIFY_OFFSET(reserved6, 0x20);
8908 VERIFY_OFFSET(io_flags, 0x24);
8909 VERIFY_OFFSET(reserved7, 0x26);
8910 VERIFY_OFFSET(LUN, 0x34);
8911 VERIFY_OFFSET(control, 0x3C);
8912 VERIFY_OFFSET(CDB, 0x40);
8913 VERIFY_OFFSET(reserved8, 0x50);
8914 VERIFY_OFFSET(host_context_flags, 0x60);
8915 VERIFY_OFFSET(timeout_sec, 0x62);
8916 VERIFY_OFFSET(ReplyQueue, 0x64);
8917 VERIFY_OFFSET(reserved9, 0x65);
8918 VERIFY_OFFSET(tag, 0x68);
8919 VERIFY_OFFSET(host_addr, 0x70);
8920 VERIFY_OFFSET(CISS_LUN, 0x78);
8921 VERIFY_OFFSET(SG, 0x78 + 8);
8922 #undef VERIFY_OFFSET
8923 }
8924
8925 module_init(hpsa_init);
8926 module_exit(hpsa_cleanup);
Michael's Linux tree.