2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
46 static ulong logging_level
= PM8001_FAIL_LOGGING
| PM8001_IOERR_LOGGING
|
47 PM8001_EVENT_LOGGING
| PM8001_INIT_LOGGING
;
48 module_param(logging_level
, ulong
, 0644);
49 MODULE_PARM_DESC(logging_level
, " bits for enabling logging info.");
51 static ulong link_rate
= LINKRATE_15
| LINKRATE_30
| LINKRATE_60
| LINKRATE_120
;
52 module_param(link_rate
, ulong
, 0644);
53 MODULE_PARM_DESC(link_rate
, "Enable link rate.\n"
54 " 1: Link rate 1.5G\n"
55 " 2: Link rate 3.0G\n"
56 " 4: Link rate 6.0G\n"
57 " 8: Link rate 12.0G\n");
59 bool pm8001_use_msix
= true;
60 module_param_named(use_msix
, pm8001_use_msix
, bool, 0444);
61 MODULE_PARM_DESC(zoned
, "Use MSIX interrupts. Default: true");
63 static bool pm8001_use_tasklet
= true;
64 module_param_named(use_tasklet
, pm8001_use_tasklet
, bool, 0444);
65 MODULE_PARM_DESC(zoned
, "Use MSIX interrupts. Default: true");
67 static bool pm8001_read_wwn
= true;
68 module_param_named(read_wwn
, pm8001_read_wwn
, bool, 0444);
69 MODULE_PARM_DESC(zoned
, "Get WWN from the controller. Default: true");
71 static struct scsi_transport_template
*pm8001_stt
;
72 static int pm8001_init_ccb_tag(struct pm8001_hba_info
*);
75 * chip info structure to identify chip key functionality as
76 * encryption available/not, no of ports, hw specific function ref
78 static const struct pm8001_chip_info pm8001_chips
[] = {
79 [chip_8001
] = {0, 8, &pm8001_8001_dispatch
,},
80 [chip_8008
] = {0, 8, &pm8001_80xx_dispatch
,},
81 [chip_8009
] = {1, 8, &pm8001_80xx_dispatch
,},
82 [chip_8018
] = {0, 16, &pm8001_80xx_dispatch
,},
83 [chip_8019
] = {1, 16, &pm8001_80xx_dispatch
,},
84 [chip_8074
] = {0, 8, &pm8001_80xx_dispatch
,},
85 [chip_8076
] = {0, 16, &pm8001_80xx_dispatch
,},
86 [chip_8077
] = {0, 16, &pm8001_80xx_dispatch
,},
87 [chip_8006
] = {0, 16, &pm8001_80xx_dispatch
,},
88 [chip_8070
] = {0, 8, &pm8001_80xx_dispatch
,},
89 [chip_8072
] = {0, 16, &pm8001_80xx_dispatch
,},
95 struct workqueue_struct
*pm8001_wq
;
97 static void pm8001_map_queues(struct Scsi_Host
*shost
)
99 struct sas_ha_struct
*sha
= SHOST_TO_SAS_HA(shost
);
100 struct pm8001_hba_info
*pm8001_ha
= sha
->lldd_ha
;
101 struct blk_mq_queue_map
*qmap
= &shost
->tag_set
.map
[HCTX_TYPE_DEFAULT
];
103 if (pm8001_ha
->number_of_intr
> 1)
104 blk_mq_pci_map_queues(qmap
, pm8001_ha
->pdev
, 1);
106 return blk_mq_map_queues(qmap
);
110 * The main structure which LLDD must register for scsi core.
112 static const struct scsi_host_template pm8001_sht
= {
113 .module
= THIS_MODULE
,
115 .proc_name
= DRV_NAME
,
116 .queuecommand
= sas_queuecommand
,
117 .dma_need_drain
= ata_scsi_dma_need_drain
,
118 .target_alloc
= sas_target_alloc
,
119 .slave_configure
= sas_slave_configure
,
120 .scan_finished
= pm8001_scan_finished
,
121 .scan_start
= pm8001_scan_start
,
122 .change_queue_depth
= sas_change_queue_depth
,
123 .bios_param
= sas_bios_param
,
126 .sg_tablesize
= PM8001_MAX_DMA_SG
,
127 .max_sectors
= SCSI_DEFAULT_MAX_SECTORS
,
128 .eh_device_reset_handler
= sas_eh_device_reset_handler
,
129 .eh_target_reset_handler
= sas_eh_target_reset_handler
,
130 .slave_alloc
= sas_slave_alloc
,
131 .target_destroy
= sas_target_destroy
,
134 .compat_ioctl
= sas_ioctl
,
136 .shost_groups
= pm8001_host_groups
,
137 .track_queue_depth
= 1,
139 .map_queues
= pm8001_map_queues
,
143 * Sas layer call this function to execute specific task.
145 static struct sas_domain_function_template pm8001_transport_ops
= {
146 .lldd_dev_found
= pm8001_dev_found
,
147 .lldd_dev_gone
= pm8001_dev_gone
,
149 .lldd_execute_task
= pm8001_queue_command
,
150 .lldd_control_phy
= pm8001_phy_control
,
152 .lldd_abort_task
= pm8001_abort_task
,
153 .lldd_abort_task_set
= sas_abort_task_set
,
154 .lldd_clear_task_set
= pm8001_clear_task_set
,
155 .lldd_I_T_nexus_reset
= pm8001_I_T_nexus_reset
,
156 .lldd_lu_reset
= pm8001_lu_reset
,
157 .lldd_query_task
= pm8001_query_task
,
158 .lldd_port_formed
= pm8001_port_formed
,
159 .lldd_tmf_exec_complete
= pm8001_setds_completion
,
160 .lldd_tmf_aborted
= pm8001_tmf_aborted
,
164 * pm8001_phy_init - initiate our adapter phys
165 * @pm8001_ha: our hba structure.
168 static void pm8001_phy_init(struct pm8001_hba_info
*pm8001_ha
, int phy_id
)
170 struct pm8001_phy
*phy
= &pm8001_ha
->phy
[phy_id
];
171 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
172 phy
->phy_state
= PHY_LINK_DISABLE
;
173 phy
->pm8001_ha
= pm8001_ha
;
174 phy
->minimum_linkrate
= SAS_LINK_RATE_1_5_GBPS
;
175 phy
->maximum_linkrate
= SAS_LINK_RATE_6_0_GBPS
;
176 sas_phy
->enabled
= (phy_id
< pm8001_ha
->chip
->n_phy
) ? 1 : 0;
177 sas_phy
->iproto
= SAS_PROTOCOL_ALL
;
179 sas_phy
->role
= PHY_ROLE_INITIATOR
;
180 sas_phy
->oob_mode
= OOB_NOT_CONNECTED
;
181 sas_phy
->linkrate
= SAS_LINK_RATE_UNKNOWN
;
182 sas_phy
->id
= phy_id
;
183 sas_phy
->sas_addr
= (u8
*)&phy
->dev_sas_addr
;
184 sas_phy
->frame_rcvd
= &phy
->frame_rcvd
[0];
185 sas_phy
->ha
= (struct sas_ha_struct
*)pm8001_ha
->shost
->hostdata
;
186 sas_phy
->lldd_phy
= phy
;
190 * pm8001_free - free hba
191 * @pm8001_ha: our hba structure.
193 static void pm8001_free(struct pm8001_hba_info
*pm8001_ha
)
200 for (i
= 0; i
< USI_MAX_MEMCNT
; i
++) {
201 if (pm8001_ha
->memoryMap
.region
[i
].virt_ptr
!= NULL
) {
202 dma_free_coherent(&pm8001_ha
->pdev
->dev
,
203 (pm8001_ha
->memoryMap
.region
[i
].total_len
+
204 pm8001_ha
->memoryMap
.region
[i
].alignment
),
205 pm8001_ha
->memoryMap
.region
[i
].virt_ptr
,
206 pm8001_ha
->memoryMap
.region
[i
].phys_addr
);
209 PM8001_CHIP_DISP
->chip_iounmap(pm8001_ha
);
210 flush_workqueue(pm8001_wq
);
211 bitmap_free(pm8001_ha
->rsvd_tags
);
216 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
217 * @opaque: the passed general host adapter struct
218 * Note: pm8001_tasklet is common for pm8001 & pm80xx
220 static void pm8001_tasklet(unsigned long opaque
)
222 struct isr_param
*irq_vector
= (struct isr_param
*)opaque
;
223 struct pm8001_hba_info
*pm8001_ha
= irq_vector
->drv_inst
;
225 if (WARN_ON_ONCE(!pm8001_ha
))
228 PM8001_CHIP_DISP
->isr(pm8001_ha
, irq_vector
->irq_id
);
231 static void pm8001_init_tasklet(struct pm8001_hba_info
*pm8001_ha
)
235 if (!pm8001_use_tasklet
)
238 /* Tasklet for non msi-x interrupt handler */
239 if ((!pm8001_ha
->pdev
->msix_cap
|| !pci_msi_enabled()) ||
240 (pm8001_ha
->chip_id
== chip_8001
)) {
241 tasklet_init(&pm8001_ha
->tasklet
[0], pm8001_tasklet
,
242 (unsigned long)&(pm8001_ha
->irq_vector
[0]));
245 for (i
= 0; i
< PM8001_MAX_MSIX_VEC
; i
++)
246 tasklet_init(&pm8001_ha
->tasklet
[i
], pm8001_tasklet
,
247 (unsigned long)&(pm8001_ha
->irq_vector
[i
]));
250 static void pm8001_kill_tasklet(struct pm8001_hba_info
*pm8001_ha
)
254 if (!pm8001_use_tasklet
)
257 /* For non-msix and msix interrupts */
258 if ((!pm8001_ha
->pdev
->msix_cap
|| !pci_msi_enabled()) ||
259 (pm8001_ha
->chip_id
== chip_8001
)) {
260 tasklet_kill(&pm8001_ha
->tasklet
[0]);
264 for (i
= 0; i
< PM8001_MAX_MSIX_VEC
; i
++)
265 tasklet_kill(&pm8001_ha
->tasklet
[i
]);
268 static irqreturn_t
pm8001_handle_irq(struct pm8001_hba_info
*pm8001_ha
,
271 if (unlikely(!pm8001_ha
))
274 if (!PM8001_CHIP_DISP
->is_our_interrupt(pm8001_ha
))
277 if (!pm8001_use_tasklet
)
278 return PM8001_CHIP_DISP
->isr(pm8001_ha
, irq
);
280 tasklet_schedule(&pm8001_ha
->tasklet
[irq
]);
285 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
286 * It obtains the vector number and calls the equivalent bottom
287 * half or services directly.
288 * @irq: interrupt number
289 * @opaque: the passed outbound queue/vector. Host structure is
290 * retrieved from the same.
292 static irqreturn_t
pm8001_interrupt_handler_msix(int irq
, void *opaque
)
294 struct isr_param
*irq_vector
= (struct isr_param
*)opaque
;
295 struct pm8001_hba_info
*pm8001_ha
= irq_vector
->drv_inst
;
297 return pm8001_handle_irq(pm8001_ha
, irq_vector
->irq_id
);
301 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
302 * @irq: interrupt number
303 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
306 static irqreturn_t
pm8001_interrupt_handler_intx(int irq
, void *dev_id
)
308 struct sas_ha_struct
*sha
= dev_id
;
309 struct pm8001_hba_info
*pm8001_ha
= sha
->lldd_ha
;
311 return pm8001_handle_irq(pm8001_ha
, 0);
314 static u32
pm8001_request_irq(struct pm8001_hba_info
*pm8001_ha
);
315 static void pm8001_free_irq(struct pm8001_hba_info
*pm8001_ha
);
318 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
319 * @pm8001_ha: our hba structure.
320 * @ent: PCI device ID structure to match on
322 static int pm8001_alloc(struct pm8001_hba_info
*pm8001_ha
,
323 const struct pci_device_id
*ent
)
325 int i
, count
= 0, rc
= 0;
326 u32 ci_offset
, ib_offset
, ob_offset
, pi_offset
;
327 struct inbound_queue_table
*ibq
;
328 struct outbound_queue_table
*obq
;
330 spin_lock_init(&pm8001_ha
->lock
);
331 spin_lock_init(&pm8001_ha
->bitmap_lock
);
332 pm8001_dbg(pm8001_ha
, INIT
, "pm8001_alloc: PHY:%x\n",
333 pm8001_ha
->chip
->n_phy
);
335 /* Request Interrupt */
336 rc
= pm8001_request_irq(pm8001_ha
);
340 count
= pm8001_ha
->max_q_num
;
341 /* Queues are chosen based on the number of cores/msix availability */
342 ib_offset
= pm8001_ha
->ib_offset
= USI_MAX_MEMCNT_BASE
;
343 ci_offset
= pm8001_ha
->ci_offset
= ib_offset
+ count
;
344 ob_offset
= pm8001_ha
->ob_offset
= ci_offset
+ count
;
345 pi_offset
= pm8001_ha
->pi_offset
= ob_offset
+ count
;
346 pm8001_ha
->max_memcnt
= pi_offset
+ count
;
348 for (i
= 0; i
< pm8001_ha
->chip
->n_phy
; i
++) {
349 pm8001_phy_init(pm8001_ha
, i
);
350 pm8001_ha
->port
[i
].wide_port_phymap
= 0;
351 pm8001_ha
->port
[i
].port_attached
= 0;
352 pm8001_ha
->port
[i
].port_state
= 0;
353 INIT_LIST_HEAD(&pm8001_ha
->port
[i
].list
);
356 /* MPI Memory region 1 for AAP Event Log for fw */
357 pm8001_ha
->memoryMap
.region
[AAP1
].num_elements
= 1;
358 pm8001_ha
->memoryMap
.region
[AAP1
].element_size
= PM8001_EVENT_LOG_SIZE
;
359 pm8001_ha
->memoryMap
.region
[AAP1
].total_len
= PM8001_EVENT_LOG_SIZE
;
360 pm8001_ha
->memoryMap
.region
[AAP1
].alignment
= 32;
362 /* MPI Memory region 2 for IOP Event Log for fw */
363 pm8001_ha
->memoryMap
.region
[IOP
].num_elements
= 1;
364 pm8001_ha
->memoryMap
.region
[IOP
].element_size
= PM8001_EVENT_LOG_SIZE
;
365 pm8001_ha
->memoryMap
.region
[IOP
].total_len
= PM8001_EVENT_LOG_SIZE
;
366 pm8001_ha
->memoryMap
.region
[IOP
].alignment
= 32;
368 for (i
= 0; i
< count
; i
++) {
369 ibq
= &pm8001_ha
->inbnd_q_tbl
[i
];
370 spin_lock_init(&ibq
->iq_lock
);
371 /* MPI Memory region 3 for consumer Index of inbound queues */
372 pm8001_ha
->memoryMap
.region
[ci_offset
+i
].num_elements
= 1;
373 pm8001_ha
->memoryMap
.region
[ci_offset
+i
].element_size
= 4;
374 pm8001_ha
->memoryMap
.region
[ci_offset
+i
].total_len
= 4;
375 pm8001_ha
->memoryMap
.region
[ci_offset
+i
].alignment
= 4;
377 if ((ent
->driver_data
) != chip_8001
) {
378 /* MPI Memory region 5 inbound queues */
379 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].num_elements
=
381 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].element_size
383 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].total_len
=
384 PM8001_MPI_QUEUE
* 128;
385 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].alignment
388 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].num_elements
=
390 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].element_size
392 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].total_len
=
393 PM8001_MPI_QUEUE
* 64;
394 pm8001_ha
->memoryMap
.region
[ib_offset
+i
].alignment
= 64;
398 for (i
= 0; i
< count
; i
++) {
399 obq
= &pm8001_ha
->outbnd_q_tbl
[i
];
400 spin_lock_init(&obq
->oq_lock
);
401 /* MPI Memory region 4 for producer Index of outbound queues */
402 pm8001_ha
->memoryMap
.region
[pi_offset
+i
].num_elements
= 1;
403 pm8001_ha
->memoryMap
.region
[pi_offset
+i
].element_size
= 4;
404 pm8001_ha
->memoryMap
.region
[pi_offset
+i
].total_len
= 4;
405 pm8001_ha
->memoryMap
.region
[pi_offset
+i
].alignment
= 4;
407 if (ent
->driver_data
!= chip_8001
) {
408 /* MPI Memory region 6 Outbound queues */
409 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].num_elements
=
411 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].element_size
413 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].total_len
=
414 PM8001_MPI_QUEUE
* 128;
415 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].alignment
418 /* MPI Memory region 6 Outbound queues */
419 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].num_elements
=
421 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].element_size
423 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].total_len
=
424 PM8001_MPI_QUEUE
* 64;
425 pm8001_ha
->memoryMap
.region
[ob_offset
+i
].alignment
= 64;
429 /* Memory region write DMA*/
430 pm8001_ha
->memoryMap
.region
[NVMD
].num_elements
= 1;
431 pm8001_ha
->memoryMap
.region
[NVMD
].element_size
= 4096;
432 pm8001_ha
->memoryMap
.region
[NVMD
].total_len
= 4096;
434 /* Memory region for fw flash */
435 pm8001_ha
->memoryMap
.region
[FW_FLASH
].total_len
= 4096;
437 pm8001_ha
->memoryMap
.region
[FORENSIC_MEM
].num_elements
= 1;
438 pm8001_ha
->memoryMap
.region
[FORENSIC_MEM
].total_len
= 0x10000;
439 pm8001_ha
->memoryMap
.region
[FORENSIC_MEM
].element_size
= 0x10000;
440 pm8001_ha
->memoryMap
.region
[FORENSIC_MEM
].alignment
= 0x10000;
441 for (i
= 0; i
< pm8001_ha
->max_memcnt
; i
++) {
442 struct mpi_mem
*region
= &pm8001_ha
->memoryMap
.region
[i
];
444 if (pm8001_mem_alloc(pm8001_ha
->pdev
,
447 ®ion
->phys_addr_hi
,
448 ®ion
->phys_addr_lo
,
450 region
->alignment
) != 0) {
451 pm8001_dbg(pm8001_ha
, FAIL
, "Mem%d alloc failed\n", i
);
456 /* Memory region for devices*/
457 pm8001_ha
->devices
= kzalloc(PM8001_MAX_DEVICES
458 * sizeof(struct pm8001_device
), GFP_KERNEL
);
459 if (!pm8001_ha
->devices
) {
463 for (i
= 0; i
< PM8001_MAX_DEVICES
; i
++) {
464 pm8001_ha
->devices
[i
].dev_type
= SAS_PHY_UNUSED
;
465 pm8001_ha
->devices
[i
].id
= i
;
466 pm8001_ha
->devices
[i
].device_id
= PM8001_MAX_DEVICES
;
467 atomic_set(&pm8001_ha
->devices
[i
].running_req
, 0);
469 pm8001_ha
->flags
= PM8001F_INIT_TIME
;
473 for (i
= 0; i
< pm8001_ha
->max_memcnt
; i
++) {
474 if (pm8001_ha
->memoryMap
.region
[i
].virt_ptr
!= NULL
) {
475 dma_free_coherent(&pm8001_ha
->pdev
->dev
,
476 (pm8001_ha
->memoryMap
.region
[i
].total_len
+
477 pm8001_ha
->memoryMap
.region
[i
].alignment
),
478 pm8001_ha
->memoryMap
.region
[i
].virt_ptr
,
479 pm8001_ha
->memoryMap
.region
[i
].phys_addr
);
487 * pm8001_ioremap - remap the pci high physical address to kernel virtual
488 * address so that we can access them.
489 * @pm8001_ha: our hba structure.
491 static int pm8001_ioremap(struct pm8001_hba_info
*pm8001_ha
)
495 struct pci_dev
*pdev
;
497 pdev
= pm8001_ha
->pdev
;
498 /* map pci mem (PMC pci base 0-3)*/
499 for (bar
= 0; bar
< PCI_STD_NUM_BARS
; bar
++) {
501 ** logical BARs for SPC:
502 ** bar 0 and 1 - logical BAR0
503 ** bar 2 and 3 - logical BAR1
504 ** bar4 - logical BAR2
505 ** bar5 - logical BAR3
506 ** Skip the appropriate assignments:
508 if ((bar
== 1) || (bar
== 3))
510 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
511 pm8001_ha
->io_mem
[logicalBar
].membase
=
512 pci_resource_start(pdev
, bar
);
513 pm8001_ha
->io_mem
[logicalBar
].memsize
=
514 pci_resource_len(pdev
, bar
);
515 pm8001_ha
->io_mem
[logicalBar
].memvirtaddr
=
516 ioremap(pm8001_ha
->io_mem
[logicalBar
].membase
,
517 pm8001_ha
->io_mem
[logicalBar
].memsize
);
518 if (!pm8001_ha
->io_mem
[logicalBar
].memvirtaddr
) {
519 pm8001_dbg(pm8001_ha
, INIT
,
520 "Failed to ioremap bar %d, logicalBar %d",
524 pm8001_dbg(pm8001_ha
, INIT
,
525 "base addr %llx virt_addr=%llx len=%d\n",
526 (u64
)pm8001_ha
->io_mem
[logicalBar
].membase
,
528 pm8001_ha
->io_mem
[logicalBar
].memvirtaddr
,
529 pm8001_ha
->io_mem
[logicalBar
].memsize
);
531 pm8001_ha
->io_mem
[logicalBar
].membase
= 0;
532 pm8001_ha
->io_mem
[logicalBar
].memsize
= 0;
533 pm8001_ha
->io_mem
[logicalBar
].memvirtaddr
= NULL
;
541 * pm8001_pci_alloc - initialize our ha card structure
544 * @shost: scsi host struct which has been initialized before.
546 static struct pm8001_hba_info
*pm8001_pci_alloc(struct pci_dev
*pdev
,
547 const struct pci_device_id
*ent
,
548 struct Scsi_Host
*shost
)
551 struct pm8001_hba_info
*pm8001_ha
;
552 struct sas_ha_struct
*sha
= SHOST_TO_SAS_HA(shost
);
554 pm8001_ha
= sha
->lldd_ha
;
558 pm8001_ha
->pdev
= pdev
;
559 pm8001_ha
->dev
= &pdev
->dev
;
560 pm8001_ha
->chip_id
= ent
->driver_data
;
561 pm8001_ha
->chip
= &pm8001_chips
[pm8001_ha
->chip_id
];
562 pm8001_ha
->irq
= pdev
->irq
;
563 pm8001_ha
->sas
= sha
;
564 pm8001_ha
->shost
= shost
;
565 pm8001_ha
->id
= pm8001_id
++;
566 pm8001_ha
->logging_level
= logging_level
;
567 pm8001_ha
->non_fatal_count
= 0;
568 if (link_rate
>= 1 && link_rate
<= 15)
569 pm8001_ha
->link_rate
= (link_rate
<< 8);
571 pm8001_ha
->link_rate
= LINKRATE_15
| LINKRATE_30
|
572 LINKRATE_60
| LINKRATE_120
;
573 pm8001_dbg(pm8001_ha
, FAIL
,
574 "Setting link rate to default value\n");
576 sprintf(pm8001_ha
->name
, "%s%d", DRV_NAME
, pm8001_ha
->id
);
577 /* IOMB size is 128 for 8088/89 controllers */
578 if (pm8001_ha
->chip_id
!= chip_8001
)
579 pm8001_ha
->iomb_size
= IOMB_SIZE_SPCV
;
581 pm8001_ha
->iomb_size
= IOMB_SIZE_SPC
;
583 pm8001_init_tasklet(pm8001_ha
);
585 if (pm8001_ioremap(pm8001_ha
))
586 goto failed_pci_alloc
;
587 if (!pm8001_alloc(pm8001_ha
, ent
))
590 pm8001_free(pm8001_ha
);
595 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
598 static int pci_go_44(struct pci_dev
*pdev
)
602 rc
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(44));
604 rc
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
606 dev_printk(KERN_ERR
, &pdev
->dev
,
607 "32-bit DMA enable failed\n");
613 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
614 * @shost: scsi host which has been allocated outside.
615 * @chip_info: our ha struct.
617 static int pm8001_prep_sas_ha_init(struct Scsi_Host
*shost
,
618 const struct pm8001_chip_info
*chip_info
)
621 struct asd_sas_phy
**arr_phy
;
622 struct asd_sas_port
**arr_port
;
623 struct sas_ha_struct
*sha
= SHOST_TO_SAS_HA(shost
);
625 phy_nr
= chip_info
->n_phy
;
627 memset(sha
, 0x00, sizeof(*sha
));
628 arr_phy
= kcalloc(phy_nr
, sizeof(void *), GFP_KERNEL
);
631 arr_port
= kcalloc(port_nr
, sizeof(void *), GFP_KERNEL
);
635 sha
->sas_phy
= arr_phy
;
636 sha
->sas_port
= arr_port
;
637 sha
->lldd_ha
= kzalloc(sizeof(struct pm8001_hba_info
), GFP_KERNEL
);
641 shost
->transportt
= pm8001_stt
;
642 shost
->max_id
= PM8001_MAX_DEVICES
;
643 shost
->unique_id
= pm8001_id
;
644 shost
->max_cmd_len
= 16;
655 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
656 * @shost: scsi host which has been allocated outside
657 * @chip_info: our ha struct.
659 static void pm8001_post_sas_ha_init(struct Scsi_Host
*shost
,
660 const struct pm8001_chip_info
*chip_info
)
663 struct pm8001_hba_info
*pm8001_ha
;
664 struct sas_ha_struct
*sha
= SHOST_TO_SAS_HA(shost
);
666 pm8001_ha
= sha
->lldd_ha
;
667 for (i
= 0; i
< chip_info
->n_phy
; i
++) {
668 sha
->sas_phy
[i
] = &pm8001_ha
->phy
[i
].sas_phy
;
669 sha
->sas_port
[i
] = &pm8001_ha
->port
[i
].sas_port
;
670 sha
->sas_phy
[i
]->sas_addr
=
671 (u8
*)&pm8001_ha
->phy
[i
].dev_sas_addr
;
673 sha
->sas_ha_name
= DRV_NAME
;
674 sha
->dev
= pm8001_ha
->dev
;
675 sha
->strict_wide_ports
= 1;
676 sha
->sas_addr
= &pm8001_ha
->sas_addr
[0];
677 sha
->num_phys
= chip_info
->n_phy
;
682 * pm8001_init_sas_add - initialize sas address
683 * @pm8001_ha: our ha struct.
685 * Currently we just set the fixed SAS address to our HBA, for manufacture,
686 * it should read from the EEPROM
688 static int pm8001_init_sas_add(struct pm8001_hba_info
*pm8001_ha
)
690 DECLARE_COMPLETION_ONSTACK(completion
);
691 struct pm8001_ioctl_payload payload
;
692 unsigned long time_remaining
;
698 if (!pm8001_read_wwn
) {
699 __be64 dev_sas_addr
= cpu_to_be64(0x50010c600047f9d0ULL
);
701 for (i
= 0; i
< pm8001_ha
->chip
->n_phy
; i
++)
702 memcpy(&pm8001_ha
->phy
[i
].dev_sas_addr
, &dev_sas_addr
,
704 memcpy(pm8001_ha
->sas_addr
, &pm8001_ha
->phy
[0].dev_sas_addr
,
710 * For new SPC controllers WWN is stored in flash vpd. For SPC/SPCve
711 * controllers WWN is stored in EEPROM. And for Older SPC WWN is stored
714 if (PM8001_CHIP_DISP
->fatal_errors(pm8001_ha
)) {
715 pm8001_dbg(pm8001_ha
, FAIL
, "controller is in fatal error state\n");
719 pci_read_config_word(pm8001_ha
->pdev
, PCI_DEVICE_ID
, &deviceid
);
720 pm8001_ha
->nvmd_completion
= &completion
;
722 if (pm8001_ha
->chip_id
== chip_8001
) {
723 if (deviceid
== 0x8081 || deviceid
== 0x0042) {
724 payload
.minor_function
= 4;
725 payload
.rd_length
= 4096;
727 payload
.minor_function
= 0;
728 payload
.rd_length
= 128;
730 } else if ((pm8001_ha
->chip_id
== chip_8070
||
731 pm8001_ha
->chip_id
== chip_8072
) &&
732 pm8001_ha
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_ATTO
) {
733 payload
.minor_function
= 4;
734 payload
.rd_length
= 4096;
736 payload
.minor_function
= 1;
737 payload
.rd_length
= 4096;
740 payload
.func_specific
= kzalloc(payload
.rd_length
, GFP_KERNEL
);
741 if (!payload
.func_specific
) {
742 pm8001_dbg(pm8001_ha
, FAIL
, "mem alloc fail\n");
745 rc
= PM8001_CHIP_DISP
->get_nvmd_req(pm8001_ha
, &payload
);
747 kfree(payload
.func_specific
);
748 pm8001_dbg(pm8001_ha
, FAIL
, "nvmd failed\n");
751 time_remaining
= wait_for_completion_timeout(&completion
,
752 msecs_to_jiffies(60*1000)); // 1 min
753 if (!time_remaining
) {
754 kfree(payload
.func_specific
);
755 pm8001_dbg(pm8001_ha
, FAIL
, "get_nvmd_req timeout\n");
760 for (i
= 0, j
= 0; i
<= 7; i
++, j
++) {
761 if (pm8001_ha
->chip_id
== chip_8001
) {
762 if (deviceid
== 0x8081)
763 pm8001_ha
->sas_addr
[j
] =
764 payload
.func_specific
[0x704 + i
];
765 else if (deviceid
== 0x0042)
766 pm8001_ha
->sas_addr
[j
] =
767 payload
.func_specific
[0x010 + i
];
768 } else if ((pm8001_ha
->chip_id
== chip_8070
||
769 pm8001_ha
->chip_id
== chip_8072
) &&
770 pm8001_ha
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_ATTO
) {
771 pm8001_ha
->sas_addr
[j
] =
772 payload
.func_specific
[0x010 + i
];
774 pm8001_ha
->sas_addr
[j
] =
775 payload
.func_specific
[0x804 + i
];
777 memcpy(sas_add
, pm8001_ha
->sas_addr
, SAS_ADDR_SIZE
);
778 for (i
= 0; i
< pm8001_ha
->chip
->n_phy
; i
++) {
779 if (i
&& ((i
% 4) == 0))
780 sas_add
[7] = sas_add
[7] + 4;
781 memcpy(&pm8001_ha
->phy
[i
].dev_sas_addr
,
782 sas_add
, SAS_ADDR_SIZE
);
783 pm8001_dbg(pm8001_ha
, INIT
, "phy %d sas_addr = %016llx\n", i
,
784 pm8001_ha
->phy
[i
].dev_sas_addr
);
786 kfree(payload
.func_specific
);
792 * pm8001_get_phy_settings_info : Read phy setting values.
793 * @pm8001_ha : our hba.
795 static int pm8001_get_phy_settings_info(struct pm8001_hba_info
*pm8001_ha
)
797 DECLARE_COMPLETION_ONSTACK(completion
);
798 struct pm8001_ioctl_payload payload
;
801 if (!pm8001_read_wwn
)
804 pm8001_ha
->nvmd_completion
= &completion
;
805 /* SAS ADDRESS read from flash / EEPROM */
806 payload
.minor_function
= 6;
808 payload
.rd_length
= 4096;
809 payload
.func_specific
= kzalloc(4096, GFP_KERNEL
);
810 if (!payload
.func_specific
)
812 /* Read phy setting values from flash */
813 rc
= PM8001_CHIP_DISP
->get_nvmd_req(pm8001_ha
, &payload
);
815 kfree(payload
.func_specific
);
816 pm8001_dbg(pm8001_ha
, INIT
, "nvmd failed\n");
819 wait_for_completion(&completion
);
820 pm8001_set_phy_profile(pm8001_ha
, sizeof(u8
), payload
.func_specific
);
821 kfree(payload
.func_specific
);
826 struct pm8001_mpi3_phy_pg_trx_config
{
839 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
840 * @pm8001_ha : our adapter
841 * @phycfg : PHY config page to populate
844 void pm8001_get_internal_phy_settings(struct pm8001_hba_info
*pm8001_ha
,
845 struct pm8001_mpi3_phy_pg_trx_config
*phycfg
)
847 phycfg
->LaneLosCfg
= 0x00000132;
848 phycfg
->LanePgaCfg1
= 0x00203949;
849 phycfg
->LanePisoCfg1
= 0x000000FF;
850 phycfg
->LanePisoCfg2
= 0xFF000001;
851 phycfg
->LanePisoCfg3
= 0xE7011300;
852 phycfg
->LanePisoCfg4
= 0x631C40C0;
853 phycfg
->LanePisoCfg5
= 0xF8102036;
854 phycfg
->LanePisoCfg6
= 0xF74A1000;
855 phycfg
->LaneBctCtrl
= 0x00FB33F8;
859 * pm8001_get_external_phy_settings - Retrieves the external PHY settings
860 * @pm8001_ha : our adapter
861 * @phycfg : PHY config page to populate
864 void pm8001_get_external_phy_settings(struct pm8001_hba_info
*pm8001_ha
,
865 struct pm8001_mpi3_phy_pg_trx_config
*phycfg
)
867 phycfg
->LaneLosCfg
= 0x00000132;
868 phycfg
->LanePgaCfg1
= 0x00203949;
869 phycfg
->LanePisoCfg1
= 0x000000FF;
870 phycfg
->LanePisoCfg2
= 0xFF000001;
871 phycfg
->LanePisoCfg3
= 0xE7011300;
872 phycfg
->LanePisoCfg4
= 0x63349140;
873 phycfg
->LanePisoCfg5
= 0xF8102036;
874 phycfg
->LanePisoCfg6
= 0xF80D9300;
875 phycfg
->LaneBctCtrl
= 0x00FB33F8;
879 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
880 * @pm8001_ha : our adapter
881 * @phymask : The PHY mask
884 void pm8001_get_phy_mask(struct pm8001_hba_info
*pm8001_ha
, int *phymask
)
886 switch (pm8001_ha
->pdev
->subsystem_device
) {
887 case 0x0070: /* H1280 - 8 external 0 internal */
888 case 0x0072: /* H12F0 - 16 external 0 internal */
892 case 0x0071: /* H1208 - 0 external 8 internal */
893 case 0x0073: /* H120F - 0 external 16 internal */
897 case 0x0080: /* H1244 - 4 external 4 internal */
901 case 0x0081: /* H1248 - 4 external 8 internal */
905 case 0x0082: /* H1288 - 8 external 8 internal */
910 pm8001_dbg(pm8001_ha
, INIT
,
911 "Unknown subsystem device=0x%.04x\n",
912 pm8001_ha
->pdev
->subsystem_device
);
917 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
918 * @pm8001_ha : our adapter
921 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info
*pm8001_ha
)
923 struct pm8001_mpi3_phy_pg_trx_config phycfg_int
;
924 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext
;
928 memset(&phycfg_int
, 0, sizeof(phycfg_int
));
929 memset(&phycfg_ext
, 0, sizeof(phycfg_ext
));
931 pm8001_get_internal_phy_settings(pm8001_ha
, &phycfg_int
);
932 pm8001_get_external_phy_settings(pm8001_ha
, &phycfg_ext
);
933 pm8001_get_phy_mask(pm8001_ha
, &phymask
);
935 for (i
= 0; i
< pm8001_ha
->chip
->n_phy
; i
++) {
936 if (phymask
& (1 << i
)) {/* Internal PHY */
937 pm8001_set_phy_profile_single(pm8001_ha
, i
,
938 sizeof(phycfg_int
) / sizeof(u32
),
941 } else { /* External PHY */
942 pm8001_set_phy_profile_single(pm8001_ha
, i
,
943 sizeof(phycfg_ext
) / sizeof(u32
),
952 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
953 * @pm8001_ha : our hba.
955 static int pm8001_configure_phy_settings(struct pm8001_hba_info
*pm8001_ha
)
957 switch (pm8001_ha
->pdev
->subsystem_vendor
) {
958 case PCI_VENDOR_ID_ATTO
:
959 if (pm8001_ha
->pdev
->device
== 0x0042) /* 6Gb */
962 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha
);
964 case PCI_VENDOR_ID_ADAPTEC2
:
969 return pm8001_get_phy_settings_info(pm8001_ha
);
974 * pm8001_setup_msix - enable MSI-X interrupt
975 * @pm8001_ha: our ha struct.
977 static u32
pm8001_setup_msix(struct pm8001_hba_info
*pm8001_ha
)
979 unsigned int allocated_irq_vectors
;
982 /* SPCv controllers supports 64 msi-x */
983 if (pm8001_ha
->chip_id
== chip_8001
) {
984 rc
= pci_alloc_irq_vectors(pm8001_ha
->pdev
, 1, 1,
988 * Queue index #0 is used always for housekeeping, so don't
989 * include in the affinity spreading.
991 struct irq_affinity desc
= {
994 rc
= pci_alloc_irq_vectors_affinity(
995 pm8001_ha
->pdev
, 2, PM8001_MAX_MSIX_VEC
,
996 PCI_IRQ_MSIX
| PCI_IRQ_AFFINITY
, &desc
);
999 allocated_irq_vectors
= rc
;
1003 /* Assigns the number of interrupts */
1004 pm8001_ha
->number_of_intr
= allocated_irq_vectors
;
1006 /* Maximum queue number updating in HBA structure */
1007 pm8001_ha
->max_q_num
= allocated_irq_vectors
;
1009 pm8001_dbg(pm8001_ha
, INIT
,
1010 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
1011 rc
, pm8001_ha
->number_of_intr
);
1015 static u32
pm8001_request_msix(struct pm8001_hba_info
*pm8001_ha
)
1018 int flag
= 0, rc
= 0;
1019 int nr_irqs
= pm8001_ha
->number_of_intr
;
1021 if (pm8001_ha
->chip_id
!= chip_8001
)
1022 flag
&= ~IRQF_SHARED
;
1024 pm8001_dbg(pm8001_ha
, INIT
,
1025 "pci_enable_msix request number of intr %d\n",
1026 pm8001_ha
->number_of_intr
);
1028 if (nr_irqs
> ARRAY_SIZE(pm8001_ha
->intr_drvname
))
1029 nr_irqs
= ARRAY_SIZE(pm8001_ha
->intr_drvname
);
1031 for (i
= 0; i
< nr_irqs
; i
++) {
1032 snprintf(pm8001_ha
->intr_drvname
[i
],
1033 sizeof(pm8001_ha
->intr_drvname
[0]),
1034 "%s-%d", pm8001_ha
->name
, i
);
1035 pm8001_ha
->irq_vector
[i
].irq_id
= i
;
1036 pm8001_ha
->irq_vector
[i
].drv_inst
= pm8001_ha
;
1038 rc
= request_irq(pci_irq_vector(pm8001_ha
->pdev
, i
),
1039 pm8001_interrupt_handler_msix
, flag
,
1040 pm8001_ha
->intr_drvname
[i
],
1041 &(pm8001_ha
->irq_vector
[i
]));
1043 for (j
= 0; j
< i
; j
++) {
1044 free_irq(pci_irq_vector(pm8001_ha
->pdev
, i
),
1045 &(pm8001_ha
->irq_vector
[i
]));
1047 pci_free_irq_vectors(pm8001_ha
->pdev
);
1056 * pm8001_request_irq - register interrupt
1057 * @pm8001_ha: our ha struct.
1059 static u32
pm8001_request_irq(struct pm8001_hba_info
*pm8001_ha
)
1061 struct pci_dev
*pdev
= pm8001_ha
->pdev
;
1064 if (pm8001_use_msix
&& pci_find_capability(pdev
, PCI_CAP_ID_MSIX
)) {
1065 rc
= pm8001_setup_msix(pm8001_ha
);
1067 pm8001_dbg(pm8001_ha
, FAIL
,
1068 "pm8001_setup_irq failed [ret: %d]\n", rc
);
1072 if (!pdev
->msix_cap
|| !pci_msi_enabled())
1075 rc
= pm8001_request_msix(pm8001_ha
);
1079 pm8001_ha
->use_msix
= true;
1085 /* Initialize the INT-X interrupt */
1086 pm8001_dbg(pm8001_ha
, INIT
, "MSIX not supported!!!\n");
1087 pm8001_ha
->use_msix
= false;
1088 pm8001_ha
->irq_vector
[0].irq_id
= 0;
1089 pm8001_ha
->irq_vector
[0].drv_inst
= pm8001_ha
;
1091 return request_irq(pdev
->irq
, pm8001_interrupt_handler_intx
,
1092 IRQF_SHARED
, pm8001_ha
->name
,
1093 SHOST_TO_SAS_HA(pm8001_ha
->shost
));
1096 static void pm8001_free_irq(struct pm8001_hba_info
*pm8001_ha
)
1098 struct pci_dev
*pdev
= pm8001_ha
->pdev
;
1101 if (pm8001_ha
->use_msix
) {
1102 for (i
= 0; i
< pm8001_ha
->number_of_intr
; i
++)
1103 synchronize_irq(pci_irq_vector(pdev
, i
));
1105 for (i
= 0; i
< pm8001_ha
->number_of_intr
; i
++)
1106 free_irq(pci_irq_vector(pdev
, i
), &pm8001_ha
->irq_vector
[i
]);
1108 pci_free_irq_vectors(pdev
);
1113 free_irq(pm8001_ha
->irq
, pm8001_ha
->sas
);
1117 * pm8001_pci_probe - probe supported device
1118 * @pdev: pci device which kernel has been prepared for.
1119 * @ent: pci device id
1121 * This function is the main initialization function, when register a new
1122 * pci driver it is invoked, all struct and hardware initialization should be
1123 * done here, also, register interrupt.
1125 static int pm8001_pci_probe(struct pci_dev
*pdev
,
1126 const struct pci_device_id
*ent
)
1131 struct pm8001_hba_info
*pm8001_ha
;
1132 struct Scsi_Host
*shost
= NULL
;
1133 const struct pm8001_chip_info
*chip
;
1134 struct sas_ha_struct
*sha
;
1136 dev_printk(KERN_INFO
, &pdev
->dev
,
1137 "pm80xx: driver version %s\n", DRV_VERSION
);
1138 rc
= pci_enable_device(pdev
);
1140 goto err_out_enable
;
1141 pci_set_master(pdev
);
1143 * Enable pci slot busmaster by setting pci command register.
1144 * This is required by FW for Cyclone card.
1147 pci_read_config_dword(pdev
, PCI_COMMAND
, &pci_reg
);
1149 pci_write_config_dword(pdev
, PCI_COMMAND
, pci_reg
);
1150 rc
= pci_request_regions(pdev
, DRV_NAME
);
1152 goto err_out_disable
;
1153 rc
= pci_go_44(pdev
);
1155 goto err_out_regions
;
1157 shost
= scsi_host_alloc(&pm8001_sht
, sizeof(void *));
1160 goto err_out_regions
;
1162 chip
= &pm8001_chips
[ent
->driver_data
];
1163 sha
= kzalloc(sizeof(struct sas_ha_struct
), GFP_KERNEL
);
1166 goto err_out_free_host
;
1168 SHOST_TO_SAS_HA(shost
) = sha
;
1170 rc
= pm8001_prep_sas_ha_init(shost
, chip
);
1175 pci_set_drvdata(pdev
, SHOST_TO_SAS_HA(shost
));
1176 /* ent->driver variable is used to differentiate between controllers */
1177 pm8001_ha
= pm8001_pci_alloc(pdev
, ent
, shost
);
1183 PM8001_CHIP_DISP
->chip_soft_rst(pm8001_ha
);
1184 rc
= PM8001_CHIP_DISP
->chip_init(pm8001_ha
);
1186 pm8001_dbg(pm8001_ha
, FAIL
,
1187 "chip_init failed [ret: %d]\n", rc
);
1188 goto err_out_ha_free
;
1191 rc
= pm8001_init_ccb_tag(pm8001_ha
);
1193 goto err_out_enable
;
1196 PM8001_CHIP_DISP
->chip_post_init(pm8001_ha
);
1198 if (pm8001_ha
->number_of_intr
> 1) {
1199 shost
->nr_hw_queues
= pm8001_ha
->number_of_intr
- 1;
1201 * For now, ensure we're not sent too many commands by setting
1202 * host_tagset. This is also required if we start using request
1205 shost
->host_tagset
= 1;
1208 rc
= scsi_add_host(shost
, &pdev
->dev
);
1210 goto err_out_ha_free
;
1212 PM8001_CHIP_DISP
->interrupt_enable(pm8001_ha
, 0);
1213 if (pm8001_ha
->chip_id
!= chip_8001
) {
1214 for (i
= 1; i
< pm8001_ha
->number_of_intr
; i
++)
1215 PM8001_CHIP_DISP
->interrupt_enable(pm8001_ha
, i
);
1216 /* setup thermal configuration. */
1217 pm80xx_set_thermal_config(pm8001_ha
);
1220 rc
= pm8001_init_sas_add(pm8001_ha
);
1223 /* phy setting support for motherboard controller */
1224 rc
= pm8001_configure_phy_settings(pm8001_ha
);
1228 pm8001_post_sas_ha_init(shost
, chip
);
1229 rc
= sas_register_ha(SHOST_TO_SAS_HA(shost
));
1231 pm8001_dbg(pm8001_ha
, FAIL
,
1232 "sas_register_ha failed [ret: %d]\n", rc
);
1235 list_add_tail(&pm8001_ha
->list
, &hba_list
);
1236 pm8001_ha
->flags
= PM8001F_RUN_TIME
;
1237 scsi_scan_host(pm8001_ha
->shost
);
1241 scsi_remove_host(pm8001_ha
->shost
);
1243 pm8001_free(pm8001_ha
);
1247 scsi_host_put(shost
);
1249 pci_release_regions(pdev
);
1251 pci_disable_device(pdev
);
1257 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1258 * @pm8001_ha: our hba card information.
1260 static int pm8001_init_ccb_tag(struct pm8001_hba_info
*pm8001_ha
)
1262 struct Scsi_Host
*shost
= pm8001_ha
->shost
;
1263 struct device
*dev
= pm8001_ha
->dev
;
1264 u32 max_out_io
, ccb_count
;
1267 max_out_io
= pm8001_ha
->main_cfg_tbl
.pm80xx_tbl
.max_out_io
;
1268 ccb_count
= min_t(int, PM8001_MAX_CCB
, max_out_io
);
1270 shost
->can_queue
= ccb_count
- PM8001_RESERVE_SLOT
;
1272 pm8001_ha
->rsvd_tags
= bitmap_zalloc(PM8001_RESERVE_SLOT
, GFP_KERNEL
);
1273 if (!pm8001_ha
->rsvd_tags
)
1276 /* Memory region for ccb_info*/
1277 pm8001_ha
->ccb_count
= ccb_count
;
1278 pm8001_ha
->ccb_info
=
1279 kcalloc(ccb_count
, sizeof(struct pm8001_ccb_info
), GFP_KERNEL
);
1280 if (!pm8001_ha
->ccb_info
) {
1281 pm8001_dbg(pm8001_ha
, FAIL
,
1282 "Unable to allocate memory for ccb\n");
1285 for (i
= 0; i
< ccb_count
; i
++) {
1286 pm8001_ha
->ccb_info
[i
].buf_prd
= dma_alloc_coherent(dev
,
1287 sizeof(struct pm8001_prd
) * PM8001_MAX_DMA_SG
,
1288 &pm8001_ha
->ccb_info
[i
].ccb_dma_handle
,
1290 if (!pm8001_ha
->ccb_info
[i
].buf_prd
) {
1291 pm8001_dbg(pm8001_ha
, FAIL
,
1292 "ccb prd memory allocation error\n");
1295 pm8001_ha
->ccb_info
[i
].task
= NULL
;
1296 pm8001_ha
->ccb_info
[i
].ccb_tag
= PM8001_INVALID_TAG
;
1297 pm8001_ha
->ccb_info
[i
].device
= NULL
;
1303 kfree(pm8001_ha
->devices
);
1308 static void pm8001_pci_remove(struct pci_dev
*pdev
)
1310 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
1311 struct pm8001_hba_info
*pm8001_ha
= sha
->lldd_ha
;
1314 sas_unregister_ha(sha
);
1315 sas_remove_host(pm8001_ha
->shost
);
1316 list_del(&pm8001_ha
->list
);
1317 PM8001_CHIP_DISP
->interrupt_disable(pm8001_ha
, 0xFF);
1318 PM8001_CHIP_DISP
->chip_soft_rst(pm8001_ha
);
1320 pm8001_free_irq(pm8001_ha
);
1321 pm8001_kill_tasklet(pm8001_ha
);
1322 scsi_host_put(pm8001_ha
->shost
);
1324 for (i
= 0; i
< pm8001_ha
->ccb_count
; i
++) {
1325 dma_free_coherent(&pm8001_ha
->pdev
->dev
,
1326 sizeof(struct pm8001_prd
) * PM8001_MAX_DMA_SG
,
1327 pm8001_ha
->ccb_info
[i
].buf_prd
,
1328 pm8001_ha
->ccb_info
[i
].ccb_dma_handle
);
1330 kfree(pm8001_ha
->ccb_info
);
1331 kfree(pm8001_ha
->devices
);
1333 pm8001_free(pm8001_ha
);
1334 kfree(sha
->sas_phy
);
1335 kfree(sha
->sas_port
);
1337 pci_release_regions(pdev
);
1338 pci_disable_device(pdev
);
1342 * pm8001_pci_suspend - power management suspend main entry point
1343 * @dev: Device struct
1345 * Return: 0 on success, anything else on error.
1347 static int __maybe_unused
pm8001_pci_suspend(struct device
*dev
)
1349 struct pci_dev
*pdev
= to_pci_dev(dev
);
1350 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
1351 struct pm8001_hba_info
*pm8001_ha
= sha
->lldd_ha
;
1353 sas_suspend_ha(sha
);
1354 flush_workqueue(pm8001_wq
);
1355 scsi_block_requests(pm8001_ha
->shost
);
1356 if (!pdev
->pm_cap
) {
1357 dev_err(dev
, " PCI PM not supported\n");
1360 PM8001_CHIP_DISP
->interrupt_disable(pm8001_ha
, 0xFF);
1361 PM8001_CHIP_DISP
->chip_soft_rst(pm8001_ha
);
1363 pm8001_free_irq(pm8001_ha
);
1364 pm8001_kill_tasklet(pm8001_ha
);
1366 pm8001_info(pm8001_ha
, "pdev=0x%p, slot=%s, entering "
1367 "suspended state\n", pdev
,
1373 * pm8001_pci_resume - power management resume main entry point
1374 * @dev: Device struct
1376 * Return: 0 on success, anything else on error.
1378 static int __maybe_unused
pm8001_pci_resume(struct device
*dev
)
1380 struct pci_dev
*pdev
= to_pci_dev(dev
);
1381 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
1382 struct pm8001_hba_info
*pm8001_ha
;
1385 DECLARE_COMPLETION_ONSTACK(completion
);
1387 pm8001_ha
= sha
->lldd_ha
;
1389 pm8001_info(pm8001_ha
,
1390 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1391 pdev
, pm8001_ha
->name
, pdev
->current_state
);
1393 rc
= pci_go_44(pdev
);
1395 goto err_out_disable
;
1396 sas_prep_resume_ha(sha
);
1397 /* chip soft rst only for spc */
1398 if (pm8001_ha
->chip_id
== chip_8001
) {
1399 PM8001_CHIP_DISP
->chip_soft_rst(pm8001_ha
);
1400 pm8001_dbg(pm8001_ha
, INIT
, "chip soft reset successful\n");
1402 rc
= PM8001_CHIP_DISP
->chip_init(pm8001_ha
);
1404 goto err_out_disable
;
1406 /* disable all the interrupt bits */
1407 PM8001_CHIP_DISP
->interrupt_disable(pm8001_ha
, 0xFF);
1409 rc
= pm8001_request_irq(pm8001_ha
);
1411 goto err_out_disable
;
1413 pm8001_init_tasklet(pm8001_ha
);
1415 PM8001_CHIP_DISP
->interrupt_enable(pm8001_ha
, 0);
1416 if (pm8001_ha
->chip_id
!= chip_8001
) {
1417 for (i
= 1; i
< pm8001_ha
->number_of_intr
; i
++)
1418 PM8001_CHIP_DISP
->interrupt_enable(pm8001_ha
, i
);
1421 /* Chip documentation for the 8070 and 8072 SPCv */
1422 /* states that a 500ms minimum delay is required */
1423 /* before issuing commands. Otherwise, the firmware */
1424 /* will enter an unrecoverable state. */
1426 if (pm8001_ha
->chip_id
== chip_8070
||
1427 pm8001_ha
->chip_id
== chip_8072
) {
1431 /* Spin up the PHYs */
1433 pm8001_ha
->flags
= PM8001F_RUN_TIME
;
1434 for (i
= 0; i
< pm8001_ha
->chip
->n_phy
; i
++) {
1435 pm8001_ha
->phy
[i
].enable_completion
= &completion
;
1436 PM8001_CHIP_DISP
->phy_start_req(pm8001_ha
, i
);
1437 wait_for_completion(&completion
);
1443 scsi_remove_host(pm8001_ha
->shost
);
1448 /* update of pci device, vendor id and driver data with
1449 * unique value for each of the controller
1451 static struct pci_device_id pm8001_pci_table
[] = {
1452 { PCI_VDEVICE(PMC_Sierra
, 0x8001), chip_8001
},
1453 { PCI_VDEVICE(PMC_Sierra
, 0x8006), chip_8006
},
1454 { PCI_VDEVICE(ADAPTEC2
, 0x8006), chip_8006
},
1455 { PCI_VDEVICE(ATTO
, 0x0042), chip_8001
},
1456 /* Support for SPC/SPCv/SPCve controllers */
1457 { PCI_VDEVICE(ADAPTEC2
, 0x8001), chip_8001
},
1458 { PCI_VDEVICE(PMC_Sierra
, 0x8008), chip_8008
},
1459 { PCI_VDEVICE(ADAPTEC2
, 0x8008), chip_8008
},
1460 { PCI_VDEVICE(PMC_Sierra
, 0x8018), chip_8018
},
1461 { PCI_VDEVICE(ADAPTEC2
, 0x8018), chip_8018
},
1462 { PCI_VDEVICE(PMC_Sierra
, 0x8009), chip_8009
},
1463 { PCI_VDEVICE(ADAPTEC2
, 0x8009), chip_8009
},
1464 { PCI_VDEVICE(PMC_Sierra
, 0x8019), chip_8019
},
1465 { PCI_VDEVICE(ADAPTEC2
, 0x8019), chip_8019
},
1466 { PCI_VDEVICE(PMC_Sierra
, 0x8074), chip_8074
},
1467 { PCI_VDEVICE(ADAPTEC2
, 0x8074), chip_8074
},
1468 { PCI_VDEVICE(PMC_Sierra
, 0x8076), chip_8076
},
1469 { PCI_VDEVICE(ADAPTEC2
, 0x8076), chip_8076
},
1470 { PCI_VDEVICE(PMC_Sierra
, 0x8077), chip_8077
},
1471 { PCI_VDEVICE(ADAPTEC2
, 0x8077), chip_8077
},
1472 { PCI_VENDOR_ID_ADAPTEC2
, 0x8081,
1473 PCI_VENDOR_ID_ADAPTEC2
, 0x0400, 0, 0, chip_8001
},
1474 { PCI_VENDOR_ID_ADAPTEC2
, 0x8081,
1475 PCI_VENDOR_ID_ADAPTEC2
, 0x0800, 0, 0, chip_8001
},
1476 { PCI_VENDOR_ID_ADAPTEC2
, 0x8088,
1477 PCI_VENDOR_ID_ADAPTEC2
, 0x0008, 0, 0, chip_8008
},
1478 { PCI_VENDOR_ID_ADAPTEC2
, 0x8088,
1479 PCI_VENDOR_ID_ADAPTEC2
, 0x0800, 0, 0, chip_8008
},
1480 { PCI_VENDOR_ID_ADAPTEC2
, 0x8089,
1481 PCI_VENDOR_ID_ADAPTEC2
, 0x0008, 0, 0, chip_8009
},
1482 { PCI_VENDOR_ID_ADAPTEC2
, 0x8089,
1483 PCI_VENDOR_ID_ADAPTEC2
, 0x0800, 0, 0, chip_8009
},
1484 { PCI_VENDOR_ID_ADAPTEC2
, 0x8088,
1485 PCI_VENDOR_ID_ADAPTEC2
, 0x0016, 0, 0, chip_8018
},
1486 { PCI_VENDOR_ID_ADAPTEC2
, 0x8088,
1487 PCI_VENDOR_ID_ADAPTEC2
, 0x1600, 0, 0, chip_8018
},
1488 { PCI_VENDOR_ID_ADAPTEC2
, 0x8089,
1489 PCI_VENDOR_ID_ADAPTEC2
, 0x0016, 0, 0, chip_8019
},
1490 { PCI_VENDOR_ID_ADAPTEC2
, 0x8089,
1491 PCI_VENDOR_ID_ADAPTEC2
, 0x1600, 0, 0, chip_8019
},
1492 { PCI_VENDOR_ID_ADAPTEC2
, 0x8074,
1493 PCI_VENDOR_ID_ADAPTEC2
, 0x0800, 0, 0, chip_8074
},
1494 { PCI_VENDOR_ID_ADAPTEC2
, 0x8076,
1495 PCI_VENDOR_ID_ADAPTEC2
, 0x1600, 0, 0, chip_8076
},
1496 { PCI_VENDOR_ID_ADAPTEC2
, 0x8077,
1497 PCI_VENDOR_ID_ADAPTEC2
, 0x1600, 0, 0, chip_8077
},
1498 { PCI_VENDOR_ID_ADAPTEC2
, 0x8074,
1499 PCI_VENDOR_ID_ADAPTEC2
, 0x0008, 0, 0, chip_8074
},
1500 { PCI_VENDOR_ID_ADAPTEC2
, 0x8076,
1501 PCI_VENDOR_ID_ADAPTEC2
, 0x0016, 0, 0, chip_8076
},
1502 { PCI_VENDOR_ID_ADAPTEC2
, 0x8077,
1503 PCI_VENDOR_ID_ADAPTEC2
, 0x0016, 0, 0, chip_8077
},
1504 { PCI_VENDOR_ID_ADAPTEC2
, 0x8076,
1505 PCI_VENDOR_ID_ADAPTEC2
, 0x0808, 0, 0, chip_8076
},
1506 { PCI_VENDOR_ID_ADAPTEC2
, 0x8077,
1507 PCI_VENDOR_ID_ADAPTEC2
, 0x0808, 0, 0, chip_8077
},
1508 { PCI_VENDOR_ID_ADAPTEC2
, 0x8074,
1509 PCI_VENDOR_ID_ADAPTEC2
, 0x0404, 0, 0, chip_8074
},
1510 { PCI_VENDOR_ID_ATTO
, 0x8070,
1511 PCI_VENDOR_ID_ATTO
, 0x0070, 0, 0, chip_8070
},
1512 { PCI_VENDOR_ID_ATTO
, 0x8070,
1513 PCI_VENDOR_ID_ATTO
, 0x0071, 0, 0, chip_8070
},
1514 { PCI_VENDOR_ID_ATTO
, 0x8072,
1515 PCI_VENDOR_ID_ATTO
, 0x0072, 0, 0, chip_8072
},
1516 { PCI_VENDOR_ID_ATTO
, 0x8072,
1517 PCI_VENDOR_ID_ATTO
, 0x0073, 0, 0, chip_8072
},
1518 { PCI_VENDOR_ID_ATTO
, 0x8070,
1519 PCI_VENDOR_ID_ATTO
, 0x0080, 0, 0, chip_8070
},
1520 { PCI_VENDOR_ID_ATTO
, 0x8072,
1521 PCI_VENDOR_ID_ATTO
, 0x0081, 0, 0, chip_8072
},
1522 { PCI_VENDOR_ID_ATTO
, 0x8072,
1523 PCI_VENDOR_ID_ATTO
, 0x0082, 0, 0, chip_8072
},
1524 {} /* terminate list */
1527 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops
,
1531 static struct pci_driver pm8001_pci_driver
= {
1533 .id_table
= pm8001_pci_table
,
1534 .probe
= pm8001_pci_probe
,
1535 .remove
= pm8001_pci_remove
,
1536 .driver
.pm
= &pm8001_pci_pm_ops
,
1540 * pm8001_init - initialize scsi transport template
1542 static int __init
pm8001_init(void)
1546 if (pm8001_use_tasklet
&& !pm8001_use_msix
)
1547 pm8001_use_tasklet
= false;
1549 pm8001_wq
= alloc_workqueue("pm80xx", 0, 0);
1554 pm8001_stt
= sas_domain_attach_transport(&pm8001_transport_ops
);
1557 rc
= pci_register_driver(&pm8001_pci_driver
);
1563 sas_release_transport(pm8001_stt
);
1565 destroy_workqueue(pm8001_wq
);
1570 static void __exit
pm8001_exit(void)
1572 pci_unregister_driver(&pm8001_pci_driver
);
1573 sas_release_transport(pm8001_stt
);
1574 destroy_workqueue(pm8001_wq
);
1577 module_init(pm8001_init
);
1578 module_exit(pm8001_exit
);
1580 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1581 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1582 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1583 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1585 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1586 "SAS/SATA controller driver");
1587 MODULE_VERSION(DRV_VERSION
);
1588 MODULE_LICENSE("GPL");
1589 MODULE_DEVICE_TABLE(pci
, pm8001_pci_table
);