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Merge tag 'v4.9.32' into linux-4.9.x-grsecurity-3.1
[people/arne_f/kernel.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
84 MODULE_PARM_DESC(ql2xextended_error_logging,
85 "Option to enable extended error logging,\n"
86 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
87 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
88 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
89 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
90 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
91 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
92 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
93 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
94 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
95 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
96 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
97 "\t\t0x1e400000 - Preferred value for capturing essential "
98 "debug information (equivalent to old "
99 "ql2xextended_error_logging=1).\n"
100 "\t\tDo LOGICAL OR of the value to enable more than one level");
101
102 int ql2xshiftctondsd = 6;
103 module_param(ql2xshiftctondsd, int, S_IRUGO);
104 MODULE_PARM_DESC(ql2xshiftctondsd,
105 "Set to control shifting of command type processing "
106 "based on total number of SG elements.");
107
108 int ql2xfdmienable=1;
109 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
110 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
111 MODULE_PARM_DESC(ql2xfdmienable,
112 "Enables FDMI registrations. "
113 "0 - no FDMI. Default is 1 - perform FDMI.");
114
115 #define MAX_Q_DEPTH 32
116 static int ql2xmaxqdepth = MAX_Q_DEPTH;
117 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
118 MODULE_PARM_DESC(ql2xmaxqdepth,
119 "Maximum queue depth to set for each LUN. "
120 "Default is 32.");
121
122 int ql2xenabledif = 2;
123 module_param(ql2xenabledif, int, S_IRUGO);
124 MODULE_PARM_DESC(ql2xenabledif,
125 " Enable T10-CRC-DIF:\n"
126 " Default is 2.\n"
127 " 0 -- No DIF Support\n"
128 " 1 -- Enable DIF for all types\n"
129 " 2 -- Enable DIF for all types, except Type 0.\n");
130
131 int ql2xenablehba_err_chk = 2;
132 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
133 MODULE_PARM_DESC(ql2xenablehba_err_chk,
134 " Enable T10-CRC-DIF Error isolation by HBA:\n"
135 " Default is 2.\n"
136 " 0 -- Error isolation disabled\n"
137 " 1 -- Error isolation enabled only for DIX Type 0\n"
138 " 2 -- Error isolation enabled for all Types\n");
139
140 int ql2xiidmaenable=1;
141 module_param(ql2xiidmaenable, int, S_IRUGO);
142 MODULE_PARM_DESC(ql2xiidmaenable,
143 "Enables iIDMA settings "
144 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
145
146 int ql2xmaxqueues = 1;
147 module_param(ql2xmaxqueues, int, S_IRUGO);
148 MODULE_PARM_DESC(ql2xmaxqueues,
149 "Enables MQ settings "
150 "Default is 1 for single queue. Set it to number "
151 "of queues in MQ mode.");
152
153 int ql2xmultique_tag;
154 module_param(ql2xmultique_tag, int, S_IRUGO);
155 MODULE_PARM_DESC(ql2xmultique_tag,
156 "Enables CPU affinity settings for the driver "
157 "Default is 0 for no affinity of request and response IO. "
158 "Set it to 1 to turn on the cpu affinity.");
159
160 int ql2xfwloadbin;
161 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
162 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
163 MODULE_PARM_DESC(ql2xfwloadbin,
164 "Option to specify location from which to load ISP firmware:.\n"
165 " 2 -- load firmware via the request_firmware() (hotplug).\n"
166 " interface.\n"
167 " 1 -- load firmware from flash.\n"
168 " 0 -- use default semantics.\n");
169
170 int ql2xetsenable;
171 module_param(ql2xetsenable, int, S_IRUGO);
172 MODULE_PARM_DESC(ql2xetsenable,
173 "Enables firmware ETS burst."
174 "Default is 0 - skip ETS enablement.");
175
176 int ql2xdbwr = 1;
177 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
178 MODULE_PARM_DESC(ql2xdbwr,
179 "Option to specify scheme for request queue posting.\n"
180 " 0 -- Regular doorbell.\n"
181 " 1 -- CAMRAM doorbell (faster).\n");
182
183 int ql2xtargetreset = 1;
184 module_param(ql2xtargetreset, int, S_IRUGO);
185 MODULE_PARM_DESC(ql2xtargetreset,
186 "Enable target reset."
187 "Default is 1 - use hw defaults.");
188
189 int ql2xgffidenable;
190 module_param(ql2xgffidenable, int, S_IRUGO);
191 MODULE_PARM_DESC(ql2xgffidenable,
192 "Enables GFF_ID checks of port type. "
193 "Default is 0 - Do not use GFF_ID information.");
194
195 int ql2xasynctmfenable;
196 module_param(ql2xasynctmfenable, int, S_IRUGO);
197 MODULE_PARM_DESC(ql2xasynctmfenable,
198 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
199 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
200
201 int ql2xdontresethba;
202 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
203 MODULE_PARM_DESC(ql2xdontresethba,
204 "Option to specify reset behaviour.\n"
205 " 0 (Default) -- Reset on failure.\n"
206 " 1 -- Do not reset on failure.\n");
207
208 uint64_t ql2xmaxlun = MAX_LUNS;
209 module_param(ql2xmaxlun, ullong, S_IRUGO);
210 MODULE_PARM_DESC(ql2xmaxlun,
211 "Defines the maximum LU number to register with the SCSI "
212 "midlayer. Default is 65535.");
213
214 int ql2xmdcapmask = 0x1F;
215 module_param(ql2xmdcapmask, int, S_IRUGO);
216 MODULE_PARM_DESC(ql2xmdcapmask,
217 "Set the Minidump driver capture mask level. "
218 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
219
220 int ql2xmdenable = 1;
221 module_param(ql2xmdenable, int, S_IRUGO);
222 MODULE_PARM_DESC(ql2xmdenable,
223 "Enable/disable MiniDump. "
224 "0 - MiniDump disabled. "
225 "1 (Default) - MiniDump enabled.");
226
227 int ql2xexlogins = 0;
228 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
229 MODULE_PARM_DESC(ql2xexlogins,
230 "Number of extended Logins. "
231 "0 (Default)- Disabled.");
232
233 int ql2xexchoffld = 0;
234 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
235 MODULE_PARM_DESC(ql2xexchoffld,
236 "Number of exchanges to offload. "
237 "0 (Default)- Disabled.");
238
239 int ql2xfwholdabts = 0;
240 module_param(ql2xfwholdabts, int, S_IRUGO);
241 MODULE_PARM_DESC(ql2xfwholdabts,
242 "Allow FW to hold status IOCB until ABTS rsp received. "
243 "0 (Default) Do not set fw option. "
244 "1 - Set fw option to hold ABTS.");
245
246 /*
247 * SCSI host template entry points
248 */
249 static int qla2xxx_slave_configure(struct scsi_device * device);
250 static int qla2xxx_slave_alloc(struct scsi_device *);
251 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
252 static void qla2xxx_scan_start(struct Scsi_Host *);
253 static void qla2xxx_slave_destroy(struct scsi_device *);
254 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
255 static int qla2xxx_eh_abort(struct scsi_cmnd *);
256 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
257 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
258 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
259 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
260
261 static void qla2x00_clear_drv_active(struct qla_hw_data *);
262 static void qla2x00_free_device(scsi_qla_host_t *);
263 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
264
265 struct scsi_host_template qla2xxx_driver_template = {
266 .module = THIS_MODULE,
267 .name = QLA2XXX_DRIVER_NAME,
268 .queuecommand = qla2xxx_queuecommand,
269
270 .eh_abort_handler = qla2xxx_eh_abort,
271 .eh_device_reset_handler = qla2xxx_eh_device_reset,
272 .eh_target_reset_handler = qla2xxx_eh_target_reset,
273 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
274 .eh_host_reset_handler = qla2xxx_eh_host_reset,
275
276 .slave_configure = qla2xxx_slave_configure,
277
278 .slave_alloc = qla2xxx_slave_alloc,
279 .slave_destroy = qla2xxx_slave_destroy,
280 .scan_finished = qla2xxx_scan_finished,
281 .scan_start = qla2xxx_scan_start,
282 .change_queue_depth = scsi_change_queue_depth,
283 .this_id = -1,
284 .cmd_per_lun = 3,
285 .use_clustering = ENABLE_CLUSTERING,
286 .sg_tablesize = SG_ALL,
287
288 .max_sectors = 0xFFFF,
289 .shost_attrs = qla2x00_host_attrs,
290
291 .supported_mode = MODE_INITIATOR,
292 .track_queue_depth = 1,
293 };
294
295 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
296 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
297
298 /* TODO Convert to inlines
299 *
300 * Timer routines
301 */
302
303 __inline__ void
304 qla2x00_start_timer(scsi_qla_host_t *vha, void (*func)(unsigned long), unsigned long interval)
305 {
306 init_timer(&vha->timer);
307 vha->timer.expires = jiffies + interval * HZ;
308 vha->timer.data = (unsigned long)vha;
309 vha->timer.function = func;
310 add_timer(&vha->timer);
311 vha->timer_active = 1;
312 }
313
314 static inline void
315 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
316 {
317 /* Currently used for 82XX only. */
318 if (vha->device_flags & DFLG_DEV_FAILED) {
319 ql_dbg(ql_dbg_timer, vha, 0x600d,
320 "Device in a failed state, returning.\n");
321 return;
322 }
323
324 mod_timer(&vha->timer, jiffies + interval * HZ);
325 }
326
327 static __inline__ void
328 qla2x00_stop_timer(scsi_qla_host_t *vha)
329 {
330 del_timer_sync(&vha->timer);
331 vha->timer_active = 0;
332 }
333
334 static int qla2x00_do_dpc(void *data);
335
336 static void qla2x00_rst_aen(scsi_qla_host_t *);
337
338 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
339 struct req_que **, struct rsp_que **);
340 static void qla2x00_free_fw_dump(struct qla_hw_data *);
341 static void qla2x00_mem_free(struct qla_hw_data *);
342
343 /* -------------------------------------------------------------------------- */
344 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
345 struct rsp_que *rsp)
346 {
347 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
348 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
349 GFP_KERNEL);
350 if (!ha->req_q_map) {
351 ql_log(ql_log_fatal, vha, 0x003b,
352 "Unable to allocate memory for request queue ptrs.\n");
353 goto fail_req_map;
354 }
355
356 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
357 GFP_KERNEL);
358 if (!ha->rsp_q_map) {
359 ql_log(ql_log_fatal, vha, 0x003c,
360 "Unable to allocate memory for response queue ptrs.\n");
361 goto fail_rsp_map;
362 }
363 /*
364 * Make sure we record at least the request and response queue zero in
365 * case we need to free them if part of the probe fails.
366 */
367 ha->rsp_q_map[0] = rsp;
368 ha->req_q_map[0] = req;
369 set_bit(0, ha->rsp_qid_map);
370 set_bit(0, ha->req_qid_map);
371 return 1;
372
373 fail_rsp_map:
374 kfree(ha->req_q_map);
375 ha->req_q_map = NULL;
376 fail_req_map:
377 return -ENOMEM;
378 }
379
380 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
381 {
382 if (IS_QLAFX00(ha)) {
383 if (req && req->ring_fx00)
384 dma_free_coherent(&ha->pdev->dev,
385 (req->length_fx00 + 1) * sizeof(request_t),
386 req->ring_fx00, req->dma_fx00);
387 } else if (req && req->ring)
388 dma_free_coherent(&ha->pdev->dev,
389 (req->length + 1) * sizeof(request_t),
390 req->ring, req->dma);
391
392 if (req)
393 kfree(req->outstanding_cmds);
394
395 kfree(req);
396 req = NULL;
397 }
398
399 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
400 {
401 if (IS_QLAFX00(ha)) {
402 if (rsp && rsp->ring)
403 dma_free_coherent(&ha->pdev->dev,
404 (rsp->length_fx00 + 1) * sizeof(request_t),
405 rsp->ring_fx00, rsp->dma_fx00);
406 } else if (rsp && rsp->ring) {
407 dma_free_coherent(&ha->pdev->dev,
408 (rsp->length + 1) * sizeof(response_t),
409 rsp->ring, rsp->dma);
410 }
411 kfree(rsp);
412 rsp = NULL;
413 }
414
415 static void qla2x00_free_queues(struct qla_hw_data *ha)
416 {
417 struct req_que *req;
418 struct rsp_que *rsp;
419 int cnt;
420
421 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
422 if (!test_bit(cnt, ha->req_qid_map))
423 continue;
424
425 req = ha->req_q_map[cnt];
426 qla2x00_free_req_que(ha, req);
427 }
428 kfree(ha->req_q_map);
429 ha->req_q_map = NULL;
430
431 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
432 if (!test_bit(cnt, ha->rsp_qid_map))
433 continue;
434
435 rsp = ha->rsp_q_map[cnt];
436 qla2x00_free_rsp_que(ha, rsp);
437 }
438 kfree(ha->rsp_q_map);
439 ha->rsp_q_map = NULL;
440 }
441
442 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
443 {
444 uint16_t options = 0;
445 int ques, req, ret;
446 struct qla_hw_data *ha = vha->hw;
447
448 if (!(ha->fw_attributes & BIT_6)) {
449 ql_log(ql_log_warn, vha, 0x00d8,
450 "Firmware is not multi-queue capable.\n");
451 goto fail;
452 }
453 if (ql2xmultique_tag) {
454 /* create a request queue for IO */
455 options |= BIT_7;
456 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
457 QLA_DEFAULT_QUE_QOS);
458 if (!req) {
459 ql_log(ql_log_warn, vha, 0x00e0,
460 "Failed to create request queue.\n");
461 goto fail;
462 }
463 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
464 vha->req = ha->req_q_map[req];
465 options |= BIT_1;
466 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
467 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
468 if (!ret) {
469 ql_log(ql_log_warn, vha, 0x00e8,
470 "Failed to create response queue.\n");
471 goto fail2;
472 }
473 }
474 ha->flags.cpu_affinity_enabled = 1;
475 ql_dbg(ql_dbg_multiq, vha, 0xc007,
476 "CPU affinity mode enabled, "
477 "no. of response queues:%d no. of request queues:%d.\n",
478 ha->max_rsp_queues, ha->max_req_queues);
479 ql_dbg(ql_dbg_init, vha, 0x00e9,
480 "CPU affinity mode enabled, "
481 "no. of response queues:%d no. of request queues:%d.\n",
482 ha->max_rsp_queues, ha->max_req_queues);
483 }
484 return 0;
485 fail2:
486 qla25xx_delete_queues(vha);
487 destroy_workqueue(ha->wq);
488 ha->wq = NULL;
489 vha->req = ha->req_q_map[0];
490 fail:
491 ha->mqenable = 0;
492 kfree(ha->req_q_map);
493 kfree(ha->rsp_q_map);
494 ha->max_req_queues = ha->max_rsp_queues = 1;
495 return 1;
496 }
497
498 static char *
499 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
500 {
501 struct qla_hw_data *ha = vha->hw;
502 static char *pci_bus_modes[] = {
503 "33", "66", "100", "133",
504 };
505 uint16_t pci_bus;
506
507 strcpy(str, "PCI");
508 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
509 if (pci_bus) {
510 strcat(str, "-X (");
511 strcat(str, pci_bus_modes[pci_bus]);
512 } else {
513 pci_bus = (ha->pci_attr & BIT_8) >> 8;
514 strcat(str, " (");
515 strcat(str, pci_bus_modes[pci_bus]);
516 }
517 strcat(str, " MHz)");
518
519 return (str);
520 }
521
522 static char *
523 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
524 {
525 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
526 struct qla_hw_data *ha = vha->hw;
527 uint32_t pci_bus;
528
529 if (pci_is_pcie(ha->pdev)) {
530 char lwstr[6];
531 uint32_t lstat, lspeed, lwidth;
532
533 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
534 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
535 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
536
537 strcpy(str, "PCIe (");
538 switch (lspeed) {
539 case 1:
540 strcat(str, "2.5GT/s ");
541 break;
542 case 2:
543 strcat(str, "5.0GT/s ");
544 break;
545 case 3:
546 strcat(str, "8.0GT/s ");
547 break;
548 default:
549 strcat(str, "<unknown> ");
550 break;
551 }
552 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
553 strcat(str, lwstr);
554
555 return str;
556 }
557
558 strcpy(str, "PCI");
559 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
560 if (pci_bus == 0 || pci_bus == 8) {
561 strcat(str, " (");
562 strcat(str, pci_bus_modes[pci_bus >> 3]);
563 } else {
564 strcat(str, "-X ");
565 if (pci_bus & BIT_2)
566 strcat(str, "Mode 2");
567 else
568 strcat(str, "Mode 1");
569 strcat(str, " (");
570 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
571 }
572 strcat(str, " MHz)");
573
574 return str;
575 }
576
577 static char *
578 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
579 {
580 char un_str[10];
581 struct qla_hw_data *ha = vha->hw;
582
583 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
584 ha->fw_minor_version, ha->fw_subminor_version);
585
586 if (ha->fw_attributes & BIT_9) {
587 strcat(str, "FLX");
588 return (str);
589 }
590
591 switch (ha->fw_attributes & 0xFF) {
592 case 0x7:
593 strcat(str, "EF");
594 break;
595 case 0x17:
596 strcat(str, "TP");
597 break;
598 case 0x37:
599 strcat(str, "IP");
600 break;
601 case 0x77:
602 strcat(str, "VI");
603 break;
604 default:
605 sprintf(un_str, "(%x)", ha->fw_attributes);
606 strcat(str, un_str);
607 break;
608 }
609 if (ha->fw_attributes & 0x100)
610 strcat(str, "X");
611
612 return (str);
613 }
614
615 static char *
616 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
617 {
618 struct qla_hw_data *ha = vha->hw;
619
620 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
621 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
622 return str;
623 }
624
625 void
626 qla2x00_sp_free_dma(void *vha, void *ptr)
627 {
628 srb_t *sp = (srb_t *)ptr;
629 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
630 struct qla_hw_data *ha = sp->fcport->vha->hw;
631 void *ctx = GET_CMD_CTX_SP(sp);
632
633 if (sp->flags & SRB_DMA_VALID) {
634 scsi_dma_unmap(cmd);
635 sp->flags &= ~SRB_DMA_VALID;
636 }
637
638 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
639 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
640 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
641 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
642 }
643
644 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
645 /* List assured to be having elements */
646 qla2x00_clean_dsd_pool(ha, sp, NULL);
647 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
648 }
649
650 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
651 dma_pool_free(ha->dl_dma_pool, ctx,
652 ((struct crc_context *)ctx)->crc_ctx_dma);
653 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
654 }
655
656 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
657 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
658
659 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
660 ctx1->fcp_cmnd_dma);
661 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
662 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
663 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
664 mempool_free(ctx1, ha->ctx_mempool);
665 ctx1 = NULL;
666 }
667
668 CMD_SP(cmd) = NULL;
669 qla2x00_rel_sp(sp->fcport->vha, sp);
670 }
671
672 static void
673 qla2x00_sp_compl(void *data, void *ptr, int res)
674 {
675 struct qla_hw_data *ha = (struct qla_hw_data *)data;
676 srb_t *sp = (srb_t *)ptr;
677 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
678
679 cmd->result = res;
680
681 if (atomic_read(&sp->ref_count) == 0) {
682 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
683 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
684 sp, GET_CMD_SP(sp));
685 if (ql2xextended_error_logging & ql_dbg_io)
686 WARN_ON(atomic_read(&sp->ref_count) == 0);
687 return;
688 }
689 if (!atomic_dec_and_test(&sp->ref_count))
690 return;
691
692 qla2x00_sp_free_dma(ha, sp);
693 cmd->scsi_done(cmd);
694 }
695
696 /* If we are SP1 here, we need to still take and release the host_lock as SP1
697 * does not have the changes necessary to avoid taking host->host_lock.
698 */
699 static int
700 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
701 {
702 scsi_qla_host_t *vha = shost_priv(host);
703 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
704 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
705 struct qla_hw_data *ha = vha->hw;
706 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
707 srb_t *sp;
708 int rval;
709
710 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
714
715 if (ha->flags.eeh_busy) {
716 if (ha->flags.pci_channel_io_perm_failure) {
717 ql_dbg(ql_dbg_aer, vha, 0x9010,
718 "PCI Channel IO permanent failure, exiting "
719 "cmd=%p.\n", cmd);
720 cmd->result = DID_NO_CONNECT << 16;
721 } else {
722 ql_dbg(ql_dbg_aer, vha, 0x9011,
723 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
724 cmd->result = DID_REQUEUE << 16;
725 }
726 goto qc24_fail_command;
727 }
728
729 rval = fc_remote_port_chkready(rport);
730 if (rval) {
731 cmd->result = rval;
732 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
733 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
734 cmd, rval);
735 goto qc24_fail_command;
736 }
737
738 if (!vha->flags.difdix_supported &&
739 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
740 ql_dbg(ql_dbg_io, vha, 0x3004,
741 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
742 cmd);
743 cmd->result = DID_NO_CONNECT << 16;
744 goto qc24_fail_command;
745 }
746
747 if (!fcport) {
748 cmd->result = DID_NO_CONNECT << 16;
749 goto qc24_fail_command;
750 }
751
752 if (atomic_read(&fcport->state) != FCS_ONLINE) {
753 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
754 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
755 ql_dbg(ql_dbg_io, vha, 0x3005,
756 "Returning DNC, fcport_state=%d loop_state=%d.\n",
757 atomic_read(&fcport->state),
758 atomic_read(&base_vha->loop_state));
759 cmd->result = DID_NO_CONNECT << 16;
760 goto qc24_fail_command;
761 }
762 goto qc24_target_busy;
763 }
764
765 /*
766 * Return target busy if we've received a non-zero retry_delay_timer
767 * in a FCP_RSP.
768 */
769 if (fcport->retry_delay_timestamp == 0) {
770 /* retry delay not set */
771 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
772 fcport->retry_delay_timestamp = 0;
773 else
774 goto qc24_target_busy;
775
776 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
777 if (!sp)
778 goto qc24_host_busy;
779
780 sp->u.scmd.cmd = cmd;
781 sp->type = SRB_SCSI_CMD;
782 atomic_set(&sp->ref_count, 1);
783 CMD_SP(cmd) = (void *)sp;
784 sp->free = qla2x00_sp_free_dma;
785 sp->done = qla2x00_sp_compl;
786
787 rval = ha->isp_ops->start_scsi(sp);
788 if (rval != QLA_SUCCESS) {
789 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
790 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
791 goto qc24_host_busy_free_sp;
792 }
793
794 return 0;
795
796 qc24_host_busy_free_sp:
797 qla2x00_sp_free_dma(ha, sp);
798
799 qc24_host_busy:
800 return SCSI_MLQUEUE_HOST_BUSY;
801
802 qc24_target_busy:
803 return SCSI_MLQUEUE_TARGET_BUSY;
804
805 qc24_fail_command:
806 cmd->scsi_done(cmd);
807
808 return 0;
809 }
810
811 /*
812 * qla2x00_eh_wait_on_command
813 * Waits for the command to be returned by the Firmware for some
814 * max time.
815 *
816 * Input:
817 * cmd = Scsi Command to wait on.
818 *
819 * Return:
820 * Not Found : 0
821 * Found : 1
822 */
823 static int
824 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
825 {
826 #define ABORT_POLLING_PERIOD 1000
827 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
828 unsigned long wait_iter = ABORT_WAIT_ITER;
829 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
830 struct qla_hw_data *ha = vha->hw;
831 int ret = QLA_SUCCESS;
832
833 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
834 ql_dbg(ql_dbg_taskm, vha, 0x8005,
835 "Return:eh_wait.\n");
836 return ret;
837 }
838
839 while (CMD_SP(cmd) && wait_iter--) {
840 msleep(ABORT_POLLING_PERIOD);
841 }
842 if (CMD_SP(cmd))
843 ret = QLA_FUNCTION_FAILED;
844
845 return ret;
846 }
847
848 /*
849 * qla2x00_wait_for_hba_online
850 * Wait till the HBA is online after going through
851 * <= MAX_RETRIES_OF_ISP_ABORT or
852 * finally HBA is disabled ie marked offline
853 *
854 * Input:
855 * ha - pointer to host adapter structure
856 *
857 * Note:
858 * Does context switching-Release SPIN_LOCK
859 * (if any) before calling this routine.
860 *
861 * Return:
862 * Success (Adapter is online) : 0
863 * Failed (Adapter is offline/disabled) : 1
864 */
865 int
866 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
867 {
868 int return_status;
869 unsigned long wait_online;
870 struct qla_hw_data *ha = vha->hw;
871 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
872
873 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
874 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
875 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
876 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
877 ha->dpc_active) && time_before(jiffies, wait_online)) {
878
879 msleep(1000);
880 }
881 if (base_vha->flags.online)
882 return_status = QLA_SUCCESS;
883 else
884 return_status = QLA_FUNCTION_FAILED;
885
886 return (return_status);
887 }
888
889 /*
890 * qla2x00_wait_for_hba_ready
891 * Wait till the HBA is ready before doing driver unload
892 *
893 * Input:
894 * ha - pointer to host adapter structure
895 *
896 * Note:
897 * Does context switching-Release SPIN_LOCK
898 * (if any) before calling this routine.
899 *
900 */
901 static void
902 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
903 {
904 struct qla_hw_data *ha = vha->hw;
905 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
906
907 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
908 ha->flags.mbox_busy) ||
909 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
910 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
911 if (test_bit(UNLOADING, &base_vha->dpc_flags))
912 break;
913 msleep(1000);
914 }
915 }
916
917 int
918 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
919 {
920 int return_status;
921 unsigned long wait_reset;
922 struct qla_hw_data *ha = vha->hw;
923 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
924
925 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
926 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
927 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
928 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
929 ha->dpc_active) && time_before(jiffies, wait_reset)) {
930
931 msleep(1000);
932
933 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
934 ha->flags.chip_reset_done)
935 break;
936 }
937 if (ha->flags.chip_reset_done)
938 return_status = QLA_SUCCESS;
939 else
940 return_status = QLA_FUNCTION_FAILED;
941
942 return return_status;
943 }
944
945 static void
946 sp_get(struct srb *sp)
947 {
948 atomic_inc(&sp->ref_count);
949 }
950
951 #define ISP_REG_DISCONNECT 0xffffffffU
952 /**************************************************************************
953 * qla2x00_isp_reg_stat
954 *
955 * Description:
956 * Read the host status register of ISP before aborting the command.
957 *
958 * Input:
959 * ha = pointer to host adapter structure.
960 *
961 *
962 * Returns:
963 * Either true or false.
964 *
965 * Note: Return true if there is register disconnect.
966 **************************************************************************/
967 static inline
968 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
969 {
970 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
971 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
972
973 if (IS_P3P_TYPE(ha))
974 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
975 else
976 return ((RD_REG_DWORD(&reg->host_status)) ==
977 ISP_REG_DISCONNECT);
978 }
979
980 /**************************************************************************
981 * qla2xxx_eh_abort
982 *
983 * Description:
984 * The abort function will abort the specified command.
985 *
986 * Input:
987 * cmd = Linux SCSI command packet to be aborted.
988 *
989 * Returns:
990 * Either SUCCESS or FAILED.
991 *
992 * Note:
993 * Only return FAILED if command not returned by firmware.
994 **************************************************************************/
995 static int
996 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
997 {
998 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
999 srb_t *sp;
1000 int ret;
1001 unsigned int id;
1002 uint64_t lun;
1003 unsigned long flags;
1004 int rval, wait = 0;
1005 struct qla_hw_data *ha = vha->hw;
1006
1007 if (qla2x00_isp_reg_stat(ha)) {
1008 ql_log(ql_log_info, vha, 0x8042,
1009 "PCI/Register disconnect, exiting.\n");
1010 return FAILED;
1011 }
1012 if (!CMD_SP(cmd))
1013 return SUCCESS;
1014
1015 ret = fc_block_scsi_eh(cmd);
1016 if (ret != 0)
1017 return ret;
1018 ret = SUCCESS;
1019
1020 id = cmd->device->id;
1021 lun = cmd->device->lun;
1022
1023 spin_lock_irqsave(&ha->hardware_lock, flags);
1024 sp = (srb_t *) CMD_SP(cmd);
1025 if (!sp) {
1026 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1027 return SUCCESS;
1028 }
1029
1030 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1031 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1032 vha->host_no, id, lun, sp, cmd, sp->handle);
1033
1034 /* Get a reference to the sp and drop the lock.*/
1035 sp_get(sp);
1036
1037 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1038 rval = ha->isp_ops->abort_command(sp);
1039 if (rval) {
1040 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
1041 ret = SUCCESS;
1042 else
1043 ret = FAILED;
1044
1045 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1046 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
1047 } else {
1048 ql_dbg(ql_dbg_taskm, vha, 0x8004,
1049 "Abort command mbx success cmd=%p.\n", cmd);
1050 wait = 1;
1051 }
1052
1053 spin_lock_irqsave(&ha->hardware_lock, flags);
1054 sp->done(ha, sp, 0);
1055 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1056
1057 /* Did the command return during mailbox execution? */
1058 if (ret == FAILED && !CMD_SP(cmd))
1059 ret = SUCCESS;
1060
1061 /* Wait for the command to be returned. */
1062 if (wait) {
1063 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1064 ql_log(ql_log_warn, vha, 0x8006,
1065 "Abort handler timed out cmd=%p.\n", cmd);
1066 ret = FAILED;
1067 }
1068 }
1069
1070 ql_log(ql_log_info, vha, 0x801c,
1071 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1072 vha->host_no, id, lun, wait, ret);
1073
1074 return ret;
1075 }
1076
1077 int
1078 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1079 uint64_t l, enum nexus_wait_type type)
1080 {
1081 int cnt, match, status;
1082 unsigned long flags;
1083 struct qla_hw_data *ha = vha->hw;
1084 struct req_que *req;
1085 srb_t *sp;
1086 struct scsi_cmnd *cmd;
1087
1088 status = QLA_SUCCESS;
1089
1090 spin_lock_irqsave(&ha->hardware_lock, flags);
1091 req = vha->req;
1092 for (cnt = 1; status == QLA_SUCCESS &&
1093 cnt < req->num_outstanding_cmds; cnt++) {
1094 sp = req->outstanding_cmds[cnt];
1095 if (!sp)
1096 continue;
1097 if (sp->type != SRB_SCSI_CMD)
1098 continue;
1099 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1100 continue;
1101 match = 0;
1102 cmd = GET_CMD_SP(sp);
1103 switch (type) {
1104 case WAIT_HOST:
1105 match = 1;
1106 break;
1107 case WAIT_TARGET:
1108 match = cmd->device->id == t;
1109 break;
1110 case WAIT_LUN:
1111 match = (cmd->device->id == t &&
1112 cmd->device->lun == l);
1113 break;
1114 }
1115 if (!match)
1116 continue;
1117
1118 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1119 status = qla2x00_eh_wait_on_command(cmd);
1120 spin_lock_irqsave(&ha->hardware_lock, flags);
1121 }
1122 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1123
1124 return status;
1125 }
1126
1127 static char *reset_errors[] = {
1128 "HBA not online",
1129 "HBA not ready",
1130 "Task management failed",
1131 "Waiting for command completions",
1132 };
1133
1134 static int
1135 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1136 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1137 {
1138 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1139 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1140 int err;
1141
1142 if (!fcport) {
1143 return FAILED;
1144 }
1145
1146 err = fc_block_scsi_eh(cmd);
1147 if (err != 0)
1148 return err;
1149
1150 ql_log(ql_log_info, vha, 0x8009,
1151 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1152 cmd->device->id, cmd->device->lun, cmd);
1153
1154 err = 0;
1155 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1156 ql_log(ql_log_warn, vha, 0x800a,
1157 "Wait for hba online failed for cmd=%p.\n", cmd);
1158 goto eh_reset_failed;
1159 }
1160 err = 2;
1161 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1162 != QLA_SUCCESS) {
1163 ql_log(ql_log_warn, vha, 0x800c,
1164 "do_reset failed for cmd=%p.\n", cmd);
1165 goto eh_reset_failed;
1166 }
1167 err = 3;
1168 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1169 cmd->device->lun, type) != QLA_SUCCESS) {
1170 ql_log(ql_log_warn, vha, 0x800d,
1171 "wait for pending cmds failed for cmd=%p.\n", cmd);
1172 goto eh_reset_failed;
1173 }
1174
1175 ql_log(ql_log_info, vha, 0x800e,
1176 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1177 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1178
1179 return SUCCESS;
1180
1181 eh_reset_failed:
1182 ql_log(ql_log_info, vha, 0x800f,
1183 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1184 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1185 cmd);
1186 return FAILED;
1187 }
1188
1189 static int
1190 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1191 {
1192 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1193 struct qla_hw_data *ha = vha->hw;
1194
1195 if (qla2x00_isp_reg_stat(ha)) {
1196 ql_log(ql_log_info, vha, 0x803e,
1197 "PCI/Register disconnect, exiting.\n");
1198 return FAILED;
1199 }
1200
1201 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1202 ha->isp_ops->lun_reset);
1203 }
1204
1205 static int
1206 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1207 {
1208 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1209 struct qla_hw_data *ha = vha->hw;
1210
1211 if (qla2x00_isp_reg_stat(ha)) {
1212 ql_log(ql_log_info, vha, 0x803f,
1213 "PCI/Register disconnect, exiting.\n");
1214 return FAILED;
1215 }
1216
1217 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1218 ha->isp_ops->target_reset);
1219 }
1220
1221 /**************************************************************************
1222 * qla2xxx_eh_bus_reset
1223 *
1224 * Description:
1225 * The bus reset function will reset the bus and abort any executing
1226 * commands.
1227 *
1228 * Input:
1229 * cmd = Linux SCSI command packet of the command that cause the
1230 * bus reset.
1231 *
1232 * Returns:
1233 * SUCCESS/FAILURE (defined as macro in scsi.h).
1234 *
1235 **************************************************************************/
1236 static int
1237 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1238 {
1239 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1240 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1241 int ret = FAILED;
1242 unsigned int id;
1243 uint64_t lun;
1244 struct qla_hw_data *ha = vha->hw;
1245
1246 if (qla2x00_isp_reg_stat(ha)) {
1247 ql_log(ql_log_info, vha, 0x8040,
1248 "PCI/Register disconnect, exiting.\n");
1249 return FAILED;
1250 }
1251
1252 id = cmd->device->id;
1253 lun = cmd->device->lun;
1254
1255 if (!fcport) {
1256 return ret;
1257 }
1258
1259 ret = fc_block_scsi_eh(cmd);
1260 if (ret != 0)
1261 return ret;
1262 ret = FAILED;
1263
1264 ql_log(ql_log_info, vha, 0x8012,
1265 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1266
1267 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1268 ql_log(ql_log_fatal, vha, 0x8013,
1269 "Wait for hba online failed board disabled.\n");
1270 goto eh_bus_reset_done;
1271 }
1272
1273 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1274 ret = SUCCESS;
1275
1276 if (ret == FAILED)
1277 goto eh_bus_reset_done;
1278
1279 /* Flush outstanding commands. */
1280 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1281 QLA_SUCCESS) {
1282 ql_log(ql_log_warn, vha, 0x8014,
1283 "Wait for pending commands failed.\n");
1284 ret = FAILED;
1285 }
1286
1287 eh_bus_reset_done:
1288 ql_log(ql_log_warn, vha, 0x802b,
1289 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1290 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1291
1292 return ret;
1293 }
1294
1295 /**************************************************************************
1296 * qla2xxx_eh_host_reset
1297 *
1298 * Description:
1299 * The reset function will reset the Adapter.
1300 *
1301 * Input:
1302 * cmd = Linux SCSI command packet of the command that cause the
1303 * adapter reset.
1304 *
1305 * Returns:
1306 * Either SUCCESS or FAILED.
1307 *
1308 * Note:
1309 **************************************************************************/
1310 static int
1311 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1312 {
1313 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1314 struct qla_hw_data *ha = vha->hw;
1315 int ret = FAILED;
1316 unsigned int id;
1317 uint64_t lun;
1318 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1319
1320 if (qla2x00_isp_reg_stat(ha)) {
1321 ql_log(ql_log_info, vha, 0x8041,
1322 "PCI/Register disconnect, exiting.\n");
1323 schedule_work(&ha->board_disable);
1324 return SUCCESS;
1325 }
1326
1327 id = cmd->device->id;
1328 lun = cmd->device->lun;
1329
1330 ql_log(ql_log_info, vha, 0x8018,
1331 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1332
1333 /*
1334 * No point in issuing another reset if one is active. Also do not
1335 * attempt a reset if we are updating flash.
1336 */
1337 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1338 goto eh_host_reset_lock;
1339
1340 if (vha != base_vha) {
1341 if (qla2x00_vp_abort_isp(vha))
1342 goto eh_host_reset_lock;
1343 } else {
1344 if (IS_P3P_TYPE(vha->hw)) {
1345 if (!qla82xx_fcoe_ctx_reset(vha)) {
1346 /* Ctx reset success */
1347 ret = SUCCESS;
1348 goto eh_host_reset_lock;
1349 }
1350 /* fall thru if ctx reset failed */
1351 }
1352 if (ha->wq)
1353 flush_workqueue(ha->wq);
1354
1355 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1356 if (ha->isp_ops->abort_isp(base_vha)) {
1357 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1358 /* failed. schedule dpc to try */
1359 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1360
1361 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1362 ql_log(ql_log_warn, vha, 0x802a,
1363 "wait for hba online failed.\n");
1364 goto eh_host_reset_lock;
1365 }
1366 }
1367 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1368 }
1369
1370 /* Waiting for command to be returned to OS.*/
1371 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1372 QLA_SUCCESS)
1373 ret = SUCCESS;
1374
1375 eh_host_reset_lock:
1376 ql_log(ql_log_info, vha, 0x8017,
1377 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1378 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1379
1380 return ret;
1381 }
1382
1383 /*
1384 * qla2x00_loop_reset
1385 * Issue loop reset.
1386 *
1387 * Input:
1388 * ha = adapter block pointer.
1389 *
1390 * Returns:
1391 * 0 = success
1392 */
1393 int
1394 qla2x00_loop_reset(scsi_qla_host_t *vha)
1395 {
1396 int ret;
1397 struct fc_port *fcport;
1398 struct qla_hw_data *ha = vha->hw;
1399
1400 if (IS_QLAFX00(ha)) {
1401 return qlafx00_loop_reset(vha);
1402 }
1403
1404 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1405 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1406 if (fcport->port_type != FCT_TARGET)
1407 continue;
1408
1409 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1410 if (ret != QLA_SUCCESS) {
1411 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1412 "Bus Reset failed: Reset=%d "
1413 "d_id=%x.\n", ret, fcport->d_id.b24);
1414 }
1415 }
1416 }
1417
1418
1419 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1420 atomic_set(&vha->loop_state, LOOP_DOWN);
1421 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1422 qla2x00_mark_all_devices_lost(vha, 0);
1423 ret = qla2x00_full_login_lip(vha);
1424 if (ret != QLA_SUCCESS) {
1425 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1426 "full_login_lip=%d.\n", ret);
1427 }
1428 }
1429
1430 if (ha->flags.enable_lip_reset) {
1431 ret = qla2x00_lip_reset(vha);
1432 if (ret != QLA_SUCCESS)
1433 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1434 "lip_reset failed (%d).\n", ret);
1435 }
1436
1437 /* Issue marker command only when we are going to start the I/O */
1438 vha->marker_needed = 1;
1439
1440 return QLA_SUCCESS;
1441 }
1442
1443 void
1444 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1445 {
1446 int que, cnt;
1447 unsigned long flags;
1448 srb_t *sp;
1449 struct qla_hw_data *ha = vha->hw;
1450 struct req_que *req;
1451
1452 qlt_host_reset_handler(ha);
1453
1454 spin_lock_irqsave(&ha->hardware_lock, flags);
1455 for (que = 0; que < ha->max_req_queues; que++) {
1456 req = ha->req_q_map[que];
1457 if (!req)
1458 continue;
1459 if (!req->outstanding_cmds)
1460 continue;
1461 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1462 sp = req->outstanding_cmds[cnt];
1463 if (sp) {
1464 /* Don't abort commands in adapter during EEH
1465 * recovery as it's not accessible/responding.
1466 */
1467 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1468 (sp->type == SRB_SCSI_CMD)) {
1469 /* Get a reference to the sp and drop the lock.
1470 * The reference ensures this sp->done() call
1471 * - and not the call in qla2xxx_eh_abort() -
1472 * ends the SCSI command (with result 'res').
1473 */
1474 sp_get(sp);
1475 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1476 qla2xxx_eh_abort(GET_CMD_SP(sp));
1477 spin_lock_irqsave(&ha->hardware_lock, flags);
1478 }
1479 req->outstanding_cmds[cnt] = NULL;
1480 sp->done(vha, sp, res);
1481 }
1482 }
1483 }
1484 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1485 }
1486
1487 static int
1488 qla2xxx_slave_alloc(struct scsi_device *sdev)
1489 {
1490 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1491
1492 if (!rport || fc_remote_port_chkready(rport))
1493 return -ENXIO;
1494
1495 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1496
1497 return 0;
1498 }
1499
1500 static int
1501 qla2xxx_slave_configure(struct scsi_device *sdev)
1502 {
1503 scsi_qla_host_t *vha = shost_priv(sdev->host);
1504 struct req_que *req = vha->req;
1505
1506 if (IS_T10_PI_CAPABLE(vha->hw))
1507 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1508
1509 scsi_change_queue_depth(sdev, req->max_q_depth);
1510 return 0;
1511 }
1512
1513 static void
1514 qla2xxx_slave_destroy(struct scsi_device *sdev)
1515 {
1516 sdev->hostdata = NULL;
1517 }
1518
1519 /**
1520 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1521 * @ha: HA context
1522 *
1523 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1524 * supported addressing method.
1525 */
1526 static void
1527 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1528 {
1529 /* Assume a 32bit DMA mask. */
1530 ha->flags.enable_64bit_addressing = 0;
1531
1532 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1533 /* Any upper-dword bits set? */
1534 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1535 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1536 /* Ok, a 64bit DMA mask is applicable. */
1537 ha->flags.enable_64bit_addressing = 1;
1538 pax_open_kernel();
1539 const_cast(ha->isp_ops->calc_req_entries) = qla2x00_calc_iocbs_64;
1540 const_cast(ha->isp_ops->build_iocbs) = qla2x00_build_scsi_iocbs_64;
1541 pax_close_kernel();
1542 return;
1543 }
1544 }
1545
1546 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1547 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1548 }
1549
1550 static void
1551 qla2x00_enable_intrs(struct qla_hw_data *ha)
1552 {
1553 unsigned long flags = 0;
1554 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1555
1556 spin_lock_irqsave(&ha->hardware_lock, flags);
1557 ha->interrupts_on = 1;
1558 /* enable risc and host interrupts */
1559 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1560 RD_REG_WORD(&reg->ictrl);
1561 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1562
1563 }
1564
1565 static void
1566 qla2x00_disable_intrs(struct qla_hw_data *ha)
1567 {
1568 unsigned long flags = 0;
1569 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1570
1571 spin_lock_irqsave(&ha->hardware_lock, flags);
1572 ha->interrupts_on = 0;
1573 /* disable risc and host interrupts */
1574 WRT_REG_WORD(&reg->ictrl, 0);
1575 RD_REG_WORD(&reg->ictrl);
1576 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1577 }
1578
1579 static void
1580 qla24xx_enable_intrs(struct qla_hw_data *ha)
1581 {
1582 unsigned long flags = 0;
1583 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1584
1585 spin_lock_irqsave(&ha->hardware_lock, flags);
1586 ha->interrupts_on = 1;
1587 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1588 RD_REG_DWORD(&reg->ictrl);
1589 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1590 }
1591
1592 static void
1593 qla24xx_disable_intrs(struct qla_hw_data *ha)
1594 {
1595 unsigned long flags = 0;
1596 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1597
1598 if (IS_NOPOLLING_TYPE(ha))
1599 return;
1600 spin_lock_irqsave(&ha->hardware_lock, flags);
1601 ha->interrupts_on = 0;
1602 WRT_REG_DWORD(&reg->ictrl, 0);
1603 RD_REG_DWORD(&reg->ictrl);
1604 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1605 }
1606
1607 static int
1608 qla2x00_iospace_config(struct qla_hw_data *ha)
1609 {
1610 resource_size_t pio;
1611 uint16_t msix;
1612 int cpus;
1613
1614 if (pci_request_selected_regions(ha->pdev, ha->bars,
1615 QLA2XXX_DRIVER_NAME)) {
1616 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1617 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1618 pci_name(ha->pdev));
1619 goto iospace_error_exit;
1620 }
1621 if (!(ha->bars & 1))
1622 goto skip_pio;
1623
1624 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1625 pio = pci_resource_start(ha->pdev, 0);
1626 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1627 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1628 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1629 "Invalid pci I/O region size (%s).\n",
1630 pci_name(ha->pdev));
1631 pio = 0;
1632 }
1633 } else {
1634 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1635 "Region #0 no a PIO resource (%s).\n",
1636 pci_name(ha->pdev));
1637 pio = 0;
1638 }
1639 ha->pio_address = pio;
1640 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1641 "PIO address=%llu.\n",
1642 (unsigned long long)ha->pio_address);
1643
1644 skip_pio:
1645 /* Use MMIO operations for all accesses. */
1646 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1647 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1648 "Region #1 not an MMIO resource (%s), aborting.\n",
1649 pci_name(ha->pdev));
1650 goto iospace_error_exit;
1651 }
1652 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1654 "Invalid PCI mem region size (%s), aborting.\n",
1655 pci_name(ha->pdev));
1656 goto iospace_error_exit;
1657 }
1658
1659 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1660 if (!ha->iobase) {
1661 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1662 "Cannot remap MMIO (%s), aborting.\n",
1663 pci_name(ha->pdev));
1664 goto iospace_error_exit;
1665 }
1666
1667 /* Determine queue resources */
1668 ha->max_req_queues = ha->max_rsp_queues = 1;
1669 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1670 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1671 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1672 goto mqiobase_exit;
1673
1674 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1675 pci_resource_len(ha->pdev, 3));
1676 if (ha->mqiobase) {
1677 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1678 "MQIO Base=%p.\n", ha->mqiobase);
1679 /* Read MSIX vector size of the board */
1680 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1681 ha->msix_count = msix;
1682 /* Max queues are bounded by available msix vectors */
1683 /* queue 0 uses two msix vectors */
1684 if (ql2xmultique_tag) {
1685 cpus = num_online_cpus();
1686 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1687 (cpus + 1) : (ha->msix_count - 1);
1688 ha->max_req_queues = 2;
1689 } else if (ql2xmaxqueues > 1) {
1690 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1691 QLA_MQ_SIZE : ql2xmaxqueues;
1692 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1693 "QoS mode set, max no of request queues:%d.\n",
1694 ha->max_req_queues);
1695 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1696 "QoS mode set, max no of request queues:%d.\n",
1697 ha->max_req_queues);
1698 }
1699 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1700 "MSI-X vector count: %d.\n", msix);
1701 } else
1702 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1703 "BAR 3 not enabled.\n");
1704
1705 mqiobase_exit:
1706 ha->msix_count = ha->max_rsp_queues + 1;
1707 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1708 "MSIX Count:%d.\n", ha->msix_count);
1709 return (0);
1710
1711 iospace_error_exit:
1712 return (-ENOMEM);
1713 }
1714
1715
1716 static int
1717 qla83xx_iospace_config(struct qla_hw_data *ha)
1718 {
1719 uint16_t msix;
1720 int cpus;
1721
1722 if (pci_request_selected_regions(ha->pdev, ha->bars,
1723 QLA2XXX_DRIVER_NAME)) {
1724 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1725 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1726 pci_name(ha->pdev));
1727
1728 goto iospace_error_exit;
1729 }
1730
1731 /* Use MMIO operations for all accesses. */
1732 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1733 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1734 "Invalid pci I/O region size (%s).\n",
1735 pci_name(ha->pdev));
1736 goto iospace_error_exit;
1737 }
1738 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1739 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1740 "Invalid PCI mem region size (%s), aborting\n",
1741 pci_name(ha->pdev));
1742 goto iospace_error_exit;
1743 }
1744
1745 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1746 if (!ha->iobase) {
1747 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1748 "Cannot remap MMIO (%s), aborting.\n",
1749 pci_name(ha->pdev));
1750 goto iospace_error_exit;
1751 }
1752
1753 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1754 /* 83XX 26XX always use MQ type access for queues
1755 * - mbar 2, a.k.a region 4 */
1756 ha->max_req_queues = ha->max_rsp_queues = 1;
1757 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1758 pci_resource_len(ha->pdev, 4));
1759
1760 if (!ha->mqiobase) {
1761 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1762 "BAR2/region4 not enabled\n");
1763 goto mqiobase_exit;
1764 }
1765
1766 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1767 pci_resource_len(ha->pdev, 2));
1768 if (ha->msixbase) {
1769 /* Read MSIX vector size of the board */
1770 pci_read_config_word(ha->pdev,
1771 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1772 ha->msix_count = msix;
1773 /* Max queues are bounded by available msix vectors */
1774 /* queue 0 uses two msix vectors */
1775 if (ql2xmultique_tag) {
1776 cpus = num_online_cpus();
1777 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1778 (cpus + 1) : (ha->msix_count - 1);
1779 ha->max_req_queues = 2;
1780 } else if (ql2xmaxqueues > 1) {
1781 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1782 QLA_MQ_SIZE : ql2xmaxqueues;
1783 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1784 "QoS mode set, max no of request queues:%d.\n",
1785 ha->max_req_queues);
1786 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1787 "QoS mode set, max no of request queues:%d.\n",
1788 ha->max_req_queues);
1789 }
1790 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1791 "MSI-X vector count: %d.\n", msix);
1792 } else
1793 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1794 "BAR 1 not enabled.\n");
1795
1796 mqiobase_exit:
1797 ha->msix_count = ha->max_rsp_queues + 1;
1798
1799 qlt_83xx_iospace_config(ha);
1800
1801 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1802 "MSIX Count:%d.\n", ha->msix_count);
1803 return 0;
1804
1805 iospace_error_exit:
1806 return -ENOMEM;
1807 }
1808
1809 static struct isp_operations qla2100_isp_ops = {
1810 .pci_config = qla2100_pci_config,
1811 .reset_chip = qla2x00_reset_chip,
1812 .chip_diag = qla2x00_chip_diag,
1813 .config_rings = qla2x00_config_rings,
1814 .reset_adapter = qla2x00_reset_adapter,
1815 .nvram_config = qla2x00_nvram_config,
1816 .update_fw_options = qla2x00_update_fw_options,
1817 .load_risc = qla2x00_load_risc,
1818 .pci_info_str = qla2x00_pci_info_str,
1819 .fw_version_str = qla2x00_fw_version_str,
1820 .intr_handler = qla2100_intr_handler,
1821 .enable_intrs = qla2x00_enable_intrs,
1822 .disable_intrs = qla2x00_disable_intrs,
1823 .abort_command = qla2x00_abort_command,
1824 .target_reset = qla2x00_abort_target,
1825 .lun_reset = qla2x00_lun_reset,
1826 .fabric_login = qla2x00_login_fabric,
1827 .fabric_logout = qla2x00_fabric_logout,
1828 .calc_req_entries = qla2x00_calc_iocbs_32,
1829 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1830 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1831 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1832 .read_nvram = qla2x00_read_nvram_data,
1833 .write_nvram = qla2x00_write_nvram_data,
1834 .fw_dump = qla2100_fw_dump,
1835 .beacon_on = NULL,
1836 .beacon_off = NULL,
1837 .beacon_blink = NULL,
1838 .read_optrom = qla2x00_read_optrom_data,
1839 .write_optrom = qla2x00_write_optrom_data,
1840 .get_flash_version = qla2x00_get_flash_version,
1841 .start_scsi = qla2x00_start_scsi,
1842 .abort_isp = qla2x00_abort_isp,
1843 .iospace_config = qla2x00_iospace_config,
1844 .initialize_adapter = qla2x00_initialize_adapter,
1845 };
1846
1847 static struct isp_operations qla2300_isp_ops = {
1848 .pci_config = qla2300_pci_config,
1849 .reset_chip = qla2x00_reset_chip,
1850 .chip_diag = qla2x00_chip_diag,
1851 .config_rings = qla2x00_config_rings,
1852 .reset_adapter = qla2x00_reset_adapter,
1853 .nvram_config = qla2x00_nvram_config,
1854 .update_fw_options = qla2x00_update_fw_options,
1855 .load_risc = qla2x00_load_risc,
1856 .pci_info_str = qla2x00_pci_info_str,
1857 .fw_version_str = qla2x00_fw_version_str,
1858 .intr_handler = qla2300_intr_handler,
1859 .enable_intrs = qla2x00_enable_intrs,
1860 .disable_intrs = qla2x00_disable_intrs,
1861 .abort_command = qla2x00_abort_command,
1862 .target_reset = qla2x00_abort_target,
1863 .lun_reset = qla2x00_lun_reset,
1864 .fabric_login = qla2x00_login_fabric,
1865 .fabric_logout = qla2x00_fabric_logout,
1866 .calc_req_entries = qla2x00_calc_iocbs_32,
1867 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1868 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1869 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1870 .read_nvram = qla2x00_read_nvram_data,
1871 .write_nvram = qla2x00_write_nvram_data,
1872 .fw_dump = qla2300_fw_dump,
1873 .beacon_on = qla2x00_beacon_on,
1874 .beacon_off = qla2x00_beacon_off,
1875 .beacon_blink = qla2x00_beacon_blink,
1876 .read_optrom = qla2x00_read_optrom_data,
1877 .write_optrom = qla2x00_write_optrom_data,
1878 .get_flash_version = qla2x00_get_flash_version,
1879 .start_scsi = qla2x00_start_scsi,
1880 .abort_isp = qla2x00_abort_isp,
1881 .iospace_config = qla2x00_iospace_config,
1882 .initialize_adapter = qla2x00_initialize_adapter,
1883 };
1884
1885 static struct isp_operations qla24xx_isp_ops = {
1886 .pci_config = qla24xx_pci_config,
1887 .reset_chip = qla24xx_reset_chip,
1888 .chip_diag = qla24xx_chip_diag,
1889 .config_rings = qla24xx_config_rings,
1890 .reset_adapter = qla24xx_reset_adapter,
1891 .nvram_config = qla24xx_nvram_config,
1892 .update_fw_options = qla24xx_update_fw_options,
1893 .load_risc = qla24xx_load_risc,
1894 .pci_info_str = qla24xx_pci_info_str,
1895 .fw_version_str = qla24xx_fw_version_str,
1896 .intr_handler = qla24xx_intr_handler,
1897 .enable_intrs = qla24xx_enable_intrs,
1898 .disable_intrs = qla24xx_disable_intrs,
1899 .abort_command = qla24xx_abort_command,
1900 .target_reset = qla24xx_abort_target,
1901 .lun_reset = qla24xx_lun_reset,
1902 .fabric_login = qla24xx_login_fabric,
1903 .fabric_logout = qla24xx_fabric_logout,
1904 .calc_req_entries = NULL,
1905 .build_iocbs = NULL,
1906 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1907 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1908 .read_nvram = qla24xx_read_nvram_data,
1909 .write_nvram = qla24xx_write_nvram_data,
1910 .fw_dump = qla24xx_fw_dump,
1911 .beacon_on = qla24xx_beacon_on,
1912 .beacon_off = qla24xx_beacon_off,
1913 .beacon_blink = qla24xx_beacon_blink,
1914 .read_optrom = qla24xx_read_optrom_data,
1915 .write_optrom = qla24xx_write_optrom_data,
1916 .get_flash_version = qla24xx_get_flash_version,
1917 .start_scsi = qla24xx_start_scsi,
1918 .abort_isp = qla2x00_abort_isp,
1919 .iospace_config = qla2x00_iospace_config,
1920 .initialize_adapter = qla2x00_initialize_adapter,
1921 };
1922
1923 static struct isp_operations qla25xx_isp_ops = {
1924 .pci_config = qla25xx_pci_config,
1925 .reset_chip = qla24xx_reset_chip,
1926 .chip_diag = qla24xx_chip_diag,
1927 .config_rings = qla24xx_config_rings,
1928 .reset_adapter = qla24xx_reset_adapter,
1929 .nvram_config = qla24xx_nvram_config,
1930 .update_fw_options = qla24xx_update_fw_options,
1931 .load_risc = qla24xx_load_risc,
1932 .pci_info_str = qla24xx_pci_info_str,
1933 .fw_version_str = qla24xx_fw_version_str,
1934 .intr_handler = qla24xx_intr_handler,
1935 .enable_intrs = qla24xx_enable_intrs,
1936 .disable_intrs = qla24xx_disable_intrs,
1937 .abort_command = qla24xx_abort_command,
1938 .target_reset = qla24xx_abort_target,
1939 .lun_reset = qla24xx_lun_reset,
1940 .fabric_login = qla24xx_login_fabric,
1941 .fabric_logout = qla24xx_fabric_logout,
1942 .calc_req_entries = NULL,
1943 .build_iocbs = NULL,
1944 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1945 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1946 .read_nvram = qla25xx_read_nvram_data,
1947 .write_nvram = qla25xx_write_nvram_data,
1948 .fw_dump = qla25xx_fw_dump,
1949 .beacon_on = qla24xx_beacon_on,
1950 .beacon_off = qla24xx_beacon_off,
1951 .beacon_blink = qla24xx_beacon_blink,
1952 .read_optrom = qla25xx_read_optrom_data,
1953 .write_optrom = qla24xx_write_optrom_data,
1954 .get_flash_version = qla24xx_get_flash_version,
1955 .start_scsi = qla24xx_dif_start_scsi,
1956 .abort_isp = qla2x00_abort_isp,
1957 .iospace_config = qla2x00_iospace_config,
1958 .initialize_adapter = qla2x00_initialize_adapter,
1959 };
1960
1961 static struct isp_operations qla81xx_isp_ops = {
1962 .pci_config = qla25xx_pci_config,
1963 .reset_chip = qla24xx_reset_chip,
1964 .chip_diag = qla24xx_chip_diag,
1965 .config_rings = qla24xx_config_rings,
1966 .reset_adapter = qla24xx_reset_adapter,
1967 .nvram_config = qla81xx_nvram_config,
1968 .update_fw_options = qla81xx_update_fw_options,
1969 .load_risc = qla81xx_load_risc,
1970 .pci_info_str = qla24xx_pci_info_str,
1971 .fw_version_str = qla24xx_fw_version_str,
1972 .intr_handler = qla24xx_intr_handler,
1973 .enable_intrs = qla24xx_enable_intrs,
1974 .disable_intrs = qla24xx_disable_intrs,
1975 .abort_command = qla24xx_abort_command,
1976 .target_reset = qla24xx_abort_target,
1977 .lun_reset = qla24xx_lun_reset,
1978 .fabric_login = qla24xx_login_fabric,
1979 .fabric_logout = qla24xx_fabric_logout,
1980 .calc_req_entries = NULL,
1981 .build_iocbs = NULL,
1982 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1983 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1984 .read_nvram = NULL,
1985 .write_nvram = NULL,
1986 .fw_dump = qla81xx_fw_dump,
1987 .beacon_on = qla24xx_beacon_on,
1988 .beacon_off = qla24xx_beacon_off,
1989 .beacon_blink = qla83xx_beacon_blink,
1990 .read_optrom = qla25xx_read_optrom_data,
1991 .write_optrom = qla24xx_write_optrom_data,
1992 .get_flash_version = qla24xx_get_flash_version,
1993 .start_scsi = qla24xx_dif_start_scsi,
1994 .abort_isp = qla2x00_abort_isp,
1995 .iospace_config = qla2x00_iospace_config,
1996 .initialize_adapter = qla2x00_initialize_adapter,
1997 };
1998
1999 static struct isp_operations qla82xx_isp_ops = {
2000 .pci_config = qla82xx_pci_config,
2001 .reset_chip = qla82xx_reset_chip,
2002 .chip_diag = qla24xx_chip_diag,
2003 .config_rings = qla82xx_config_rings,
2004 .reset_adapter = qla24xx_reset_adapter,
2005 .nvram_config = qla81xx_nvram_config,
2006 .update_fw_options = qla24xx_update_fw_options,
2007 .load_risc = qla82xx_load_risc,
2008 .pci_info_str = qla24xx_pci_info_str,
2009 .fw_version_str = qla24xx_fw_version_str,
2010 .intr_handler = qla82xx_intr_handler,
2011 .enable_intrs = qla82xx_enable_intrs,
2012 .disable_intrs = qla82xx_disable_intrs,
2013 .abort_command = qla24xx_abort_command,
2014 .target_reset = qla24xx_abort_target,
2015 .lun_reset = qla24xx_lun_reset,
2016 .fabric_login = qla24xx_login_fabric,
2017 .fabric_logout = qla24xx_fabric_logout,
2018 .calc_req_entries = NULL,
2019 .build_iocbs = NULL,
2020 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2021 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2022 .read_nvram = qla24xx_read_nvram_data,
2023 .write_nvram = qla24xx_write_nvram_data,
2024 .fw_dump = qla82xx_fw_dump,
2025 .beacon_on = qla82xx_beacon_on,
2026 .beacon_off = qla82xx_beacon_off,
2027 .beacon_blink = NULL,
2028 .read_optrom = qla82xx_read_optrom_data,
2029 .write_optrom = qla82xx_write_optrom_data,
2030 .get_flash_version = qla82xx_get_flash_version,
2031 .start_scsi = qla82xx_start_scsi,
2032 .abort_isp = qla82xx_abort_isp,
2033 .iospace_config = qla82xx_iospace_config,
2034 .initialize_adapter = qla2x00_initialize_adapter,
2035 };
2036
2037 static struct isp_operations qla8044_isp_ops = {
2038 .pci_config = qla82xx_pci_config,
2039 .reset_chip = qla82xx_reset_chip,
2040 .chip_diag = qla24xx_chip_diag,
2041 .config_rings = qla82xx_config_rings,
2042 .reset_adapter = qla24xx_reset_adapter,
2043 .nvram_config = qla81xx_nvram_config,
2044 .update_fw_options = qla24xx_update_fw_options,
2045 .load_risc = qla82xx_load_risc,
2046 .pci_info_str = qla24xx_pci_info_str,
2047 .fw_version_str = qla24xx_fw_version_str,
2048 .intr_handler = qla8044_intr_handler,
2049 .enable_intrs = qla82xx_enable_intrs,
2050 .disable_intrs = qla82xx_disable_intrs,
2051 .abort_command = qla24xx_abort_command,
2052 .target_reset = qla24xx_abort_target,
2053 .lun_reset = qla24xx_lun_reset,
2054 .fabric_login = qla24xx_login_fabric,
2055 .fabric_logout = qla24xx_fabric_logout,
2056 .calc_req_entries = NULL,
2057 .build_iocbs = NULL,
2058 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2059 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2060 .read_nvram = NULL,
2061 .write_nvram = NULL,
2062 .fw_dump = qla8044_fw_dump,
2063 .beacon_on = qla82xx_beacon_on,
2064 .beacon_off = qla82xx_beacon_off,
2065 .beacon_blink = NULL,
2066 .read_optrom = qla8044_read_optrom_data,
2067 .write_optrom = qla8044_write_optrom_data,
2068 .get_flash_version = qla82xx_get_flash_version,
2069 .start_scsi = qla82xx_start_scsi,
2070 .abort_isp = qla8044_abort_isp,
2071 .iospace_config = qla82xx_iospace_config,
2072 .initialize_adapter = qla2x00_initialize_adapter,
2073 };
2074
2075 static struct isp_operations qla83xx_isp_ops = {
2076 .pci_config = qla25xx_pci_config,
2077 .reset_chip = qla24xx_reset_chip,
2078 .chip_diag = qla24xx_chip_diag,
2079 .config_rings = qla24xx_config_rings,
2080 .reset_adapter = qla24xx_reset_adapter,
2081 .nvram_config = qla81xx_nvram_config,
2082 .update_fw_options = qla81xx_update_fw_options,
2083 .load_risc = qla81xx_load_risc,
2084 .pci_info_str = qla24xx_pci_info_str,
2085 .fw_version_str = qla24xx_fw_version_str,
2086 .intr_handler = qla24xx_intr_handler,
2087 .enable_intrs = qla24xx_enable_intrs,
2088 .disable_intrs = qla24xx_disable_intrs,
2089 .abort_command = qla24xx_abort_command,
2090 .target_reset = qla24xx_abort_target,
2091 .lun_reset = qla24xx_lun_reset,
2092 .fabric_login = qla24xx_login_fabric,
2093 .fabric_logout = qla24xx_fabric_logout,
2094 .calc_req_entries = NULL,
2095 .build_iocbs = NULL,
2096 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2097 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2098 .read_nvram = NULL,
2099 .write_nvram = NULL,
2100 .fw_dump = qla83xx_fw_dump,
2101 .beacon_on = qla24xx_beacon_on,
2102 .beacon_off = qla24xx_beacon_off,
2103 .beacon_blink = qla83xx_beacon_blink,
2104 .read_optrom = qla25xx_read_optrom_data,
2105 .write_optrom = qla24xx_write_optrom_data,
2106 .get_flash_version = qla24xx_get_flash_version,
2107 .start_scsi = qla24xx_dif_start_scsi,
2108 .abort_isp = qla2x00_abort_isp,
2109 .iospace_config = qla83xx_iospace_config,
2110 .initialize_adapter = qla2x00_initialize_adapter,
2111 };
2112
2113 static struct isp_operations qlafx00_isp_ops = {
2114 .pci_config = qlafx00_pci_config,
2115 .reset_chip = qlafx00_soft_reset,
2116 .chip_diag = qlafx00_chip_diag,
2117 .config_rings = qlafx00_config_rings,
2118 .reset_adapter = qlafx00_soft_reset,
2119 .nvram_config = NULL,
2120 .update_fw_options = NULL,
2121 .load_risc = NULL,
2122 .pci_info_str = qlafx00_pci_info_str,
2123 .fw_version_str = qlafx00_fw_version_str,
2124 .intr_handler = qlafx00_intr_handler,
2125 .enable_intrs = qlafx00_enable_intrs,
2126 .disable_intrs = qlafx00_disable_intrs,
2127 .abort_command = qla24xx_async_abort_command,
2128 .target_reset = qlafx00_abort_target,
2129 .lun_reset = qlafx00_lun_reset,
2130 .fabric_login = NULL,
2131 .fabric_logout = NULL,
2132 .calc_req_entries = NULL,
2133 .build_iocbs = NULL,
2134 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2135 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2136 .read_nvram = qla24xx_read_nvram_data,
2137 .write_nvram = qla24xx_write_nvram_data,
2138 .fw_dump = NULL,
2139 .beacon_on = qla24xx_beacon_on,
2140 .beacon_off = qla24xx_beacon_off,
2141 .beacon_blink = NULL,
2142 .read_optrom = qla24xx_read_optrom_data,
2143 .write_optrom = qla24xx_write_optrom_data,
2144 .get_flash_version = qla24xx_get_flash_version,
2145 .start_scsi = qlafx00_start_scsi,
2146 .abort_isp = qlafx00_abort_isp,
2147 .iospace_config = qlafx00_iospace_config,
2148 .initialize_adapter = qlafx00_initialize_adapter,
2149 };
2150
2151 static struct isp_operations qla27xx_isp_ops = {
2152 .pci_config = qla25xx_pci_config,
2153 .reset_chip = qla24xx_reset_chip,
2154 .chip_diag = qla24xx_chip_diag,
2155 .config_rings = qla24xx_config_rings,
2156 .reset_adapter = qla24xx_reset_adapter,
2157 .nvram_config = qla81xx_nvram_config,
2158 .update_fw_options = qla81xx_update_fw_options,
2159 .load_risc = qla81xx_load_risc,
2160 .pci_info_str = qla24xx_pci_info_str,
2161 .fw_version_str = qla24xx_fw_version_str,
2162 .intr_handler = qla24xx_intr_handler,
2163 .enable_intrs = qla24xx_enable_intrs,
2164 .disable_intrs = qla24xx_disable_intrs,
2165 .abort_command = qla24xx_abort_command,
2166 .target_reset = qla24xx_abort_target,
2167 .lun_reset = qla24xx_lun_reset,
2168 .fabric_login = qla24xx_login_fabric,
2169 .fabric_logout = qla24xx_fabric_logout,
2170 .calc_req_entries = NULL,
2171 .build_iocbs = NULL,
2172 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2173 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2174 .read_nvram = NULL,
2175 .write_nvram = NULL,
2176 .fw_dump = qla27xx_fwdump,
2177 .beacon_on = qla24xx_beacon_on,
2178 .beacon_off = qla24xx_beacon_off,
2179 .beacon_blink = qla83xx_beacon_blink,
2180 .read_optrom = qla25xx_read_optrom_data,
2181 .write_optrom = qla24xx_write_optrom_data,
2182 .get_flash_version = qla24xx_get_flash_version,
2183 .start_scsi = qla24xx_dif_start_scsi,
2184 .abort_isp = qla2x00_abort_isp,
2185 .iospace_config = qla83xx_iospace_config,
2186 .initialize_adapter = qla2x00_initialize_adapter,
2187 };
2188
2189 static inline void
2190 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2191 {
2192 ha->device_type = DT_EXTENDED_IDS;
2193 switch (ha->pdev->device) {
2194 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2195 ha->isp_type |= DT_ISP2100;
2196 ha->device_type &= ~DT_EXTENDED_IDS;
2197 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2198 break;
2199 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2200 ha->isp_type |= DT_ISP2200;
2201 ha->device_type &= ~DT_EXTENDED_IDS;
2202 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2203 break;
2204 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2205 ha->isp_type |= DT_ISP2300;
2206 ha->device_type |= DT_ZIO_SUPPORTED;
2207 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2208 break;
2209 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2210 ha->isp_type |= DT_ISP2312;
2211 ha->device_type |= DT_ZIO_SUPPORTED;
2212 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2213 break;
2214 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2215 ha->isp_type |= DT_ISP2322;
2216 ha->device_type |= DT_ZIO_SUPPORTED;
2217 if (ha->pdev->subsystem_vendor == 0x1028 &&
2218 ha->pdev->subsystem_device == 0x0170)
2219 ha->device_type |= DT_OEM_001;
2220 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2221 break;
2222 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2223 ha->isp_type |= DT_ISP6312;
2224 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2225 break;
2226 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2227 ha->isp_type |= DT_ISP6322;
2228 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2229 break;
2230 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2231 ha->isp_type |= DT_ISP2422;
2232 ha->device_type |= DT_ZIO_SUPPORTED;
2233 ha->device_type |= DT_FWI2;
2234 ha->device_type |= DT_IIDMA;
2235 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2236 break;
2237 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2238 ha->isp_type |= DT_ISP2432;
2239 ha->device_type |= DT_ZIO_SUPPORTED;
2240 ha->device_type |= DT_FWI2;
2241 ha->device_type |= DT_IIDMA;
2242 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2243 break;
2244 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2245 ha->isp_type |= DT_ISP8432;
2246 ha->device_type |= DT_ZIO_SUPPORTED;
2247 ha->device_type |= DT_FWI2;
2248 ha->device_type |= DT_IIDMA;
2249 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2250 break;
2251 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2252 ha->isp_type |= DT_ISP5422;
2253 ha->device_type |= DT_FWI2;
2254 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2255 break;
2256 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2257 ha->isp_type |= DT_ISP5432;
2258 ha->device_type |= DT_FWI2;
2259 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2260 break;
2261 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2262 ha->isp_type |= DT_ISP2532;
2263 ha->device_type |= DT_ZIO_SUPPORTED;
2264 ha->device_type |= DT_FWI2;
2265 ha->device_type |= DT_IIDMA;
2266 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2267 break;
2268 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2269 ha->isp_type |= DT_ISP8001;
2270 ha->device_type |= DT_ZIO_SUPPORTED;
2271 ha->device_type |= DT_FWI2;
2272 ha->device_type |= DT_IIDMA;
2273 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2274 break;
2275 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2276 ha->isp_type |= DT_ISP8021;
2277 ha->device_type |= DT_ZIO_SUPPORTED;
2278 ha->device_type |= DT_FWI2;
2279 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2280 /* Initialize 82XX ISP flags */
2281 qla82xx_init_flags(ha);
2282 break;
2283 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2284 ha->isp_type |= DT_ISP8044;
2285 ha->device_type |= DT_ZIO_SUPPORTED;
2286 ha->device_type |= DT_FWI2;
2287 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2288 /* Initialize 82XX ISP flags */
2289 qla82xx_init_flags(ha);
2290 break;
2291 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2292 ha->isp_type |= DT_ISP2031;
2293 ha->device_type |= DT_ZIO_SUPPORTED;
2294 ha->device_type |= DT_FWI2;
2295 ha->device_type |= DT_IIDMA;
2296 ha->device_type |= DT_T10_PI;
2297 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2298 break;
2299 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2300 ha->isp_type |= DT_ISP8031;
2301 ha->device_type |= DT_ZIO_SUPPORTED;
2302 ha->device_type |= DT_FWI2;
2303 ha->device_type |= DT_IIDMA;
2304 ha->device_type |= DT_T10_PI;
2305 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2306 break;
2307 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2308 ha->isp_type |= DT_ISPFX00;
2309 break;
2310 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2311 ha->isp_type |= DT_ISP2071;
2312 ha->device_type |= DT_ZIO_SUPPORTED;
2313 ha->device_type |= DT_FWI2;
2314 ha->device_type |= DT_IIDMA;
2315 ha->device_type |= DT_T10_PI;
2316 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2317 break;
2318 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2319 ha->isp_type |= DT_ISP2271;
2320 ha->device_type |= DT_ZIO_SUPPORTED;
2321 ha->device_type |= DT_FWI2;
2322 ha->device_type |= DT_IIDMA;
2323 ha->device_type |= DT_T10_PI;
2324 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2325 break;
2326 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2327 ha->isp_type |= DT_ISP2261;
2328 ha->device_type |= DT_ZIO_SUPPORTED;
2329 ha->device_type |= DT_FWI2;
2330 ha->device_type |= DT_IIDMA;
2331 ha->device_type |= DT_T10_PI;
2332 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2333 break;
2334 }
2335
2336 if (IS_QLA82XX(ha))
2337 ha->port_no = ha->portnum & 1;
2338 else {
2339 /* Get adapter physical port no from interrupt pin register. */
2340 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2341 if (IS_QLA27XX(ha))
2342 ha->port_no--;
2343 else
2344 ha->port_no = !(ha->port_no & 1);
2345 }
2346
2347 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2348 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2349 ha->device_type, ha->port_no, ha->fw_srisc_address);
2350 }
2351
2352 static void
2353 qla2xxx_scan_start(struct Scsi_Host *shost)
2354 {
2355 scsi_qla_host_t *vha = shost_priv(shost);
2356
2357 if (vha->hw->flags.running_gold_fw)
2358 return;
2359
2360 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2361 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2362 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2363 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2364 }
2365
2366 static int
2367 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2368 {
2369 scsi_qla_host_t *vha = shost_priv(shost);
2370
2371 if (test_bit(UNLOADING, &vha->dpc_flags))
2372 return 1;
2373 if (!vha->host)
2374 return 1;
2375 if (time > vha->hw->loop_reset_delay * HZ)
2376 return 1;
2377
2378 return atomic_read(&vha->loop_state) == LOOP_READY;
2379 }
2380
2381 /*
2382 * PCI driver interface
2383 */
2384 static int
2385 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2386 {
2387 int ret = -ENODEV;
2388 struct Scsi_Host *host;
2389 scsi_qla_host_t *base_vha = NULL;
2390 struct qla_hw_data *ha;
2391 char pci_info[30];
2392 char fw_str[30], wq_name[30];
2393 struct scsi_host_template *sht;
2394 int bars, mem_only = 0;
2395 uint16_t req_length = 0, rsp_length = 0;
2396 struct req_que *req = NULL;
2397 struct rsp_que *rsp = NULL;
2398 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2399 sht = &qla2xxx_driver_template;
2400 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2401 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2402 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2403 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2404 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2405 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2406 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2407 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2408 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2409 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2410 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2411 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2412 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2413 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2414 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2415 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2416 mem_only = 1;
2417 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2418 "Mem only adapter.\n");
2419 }
2420 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2421 "Bars=%d.\n", bars);
2422
2423 if (mem_only) {
2424 if (pci_enable_device_mem(pdev))
2425 return ret;
2426 } else {
2427 if (pci_enable_device(pdev))
2428 return ret;
2429 }
2430
2431 /* This may fail but that's ok */
2432 pci_enable_pcie_error_reporting(pdev);
2433
2434 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2435 if (!ha) {
2436 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2437 "Unable to allocate memory for ha.\n");
2438 goto disable_device;
2439 }
2440 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2441 "Memory allocated for ha=%p.\n", ha);
2442 ha->pdev = pdev;
2443 ha->tgt.enable_class_2 = ql2xenableclass2;
2444 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2445 spin_lock_init(&ha->tgt.q_full_lock);
2446 spin_lock_init(&ha->tgt.sess_lock);
2447 spin_lock_init(&ha->tgt.atio_lock);
2448
2449
2450 /* Clear our data area */
2451 ha->bars = bars;
2452 ha->mem_only = mem_only;
2453 spin_lock_init(&ha->hardware_lock);
2454 spin_lock_init(&ha->vport_slock);
2455 mutex_init(&ha->selflogin_lock);
2456 mutex_init(&ha->optrom_mutex);
2457
2458 /* Set ISP-type information. */
2459 qla2x00_set_isp_flags(ha);
2460
2461 /* Set EEH reset type to fundamental if required by hba */
2462 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2463 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2464 pdev->needs_freset = 1;
2465
2466 ha->prev_topology = 0;
2467 ha->init_cb_size = sizeof(init_cb_t);
2468 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2469 ha->optrom_size = OPTROM_SIZE_2300;
2470
2471 /* Assign ISP specific operations. */
2472 if (IS_QLA2100(ha)) {
2473 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2474 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2475 req_length = REQUEST_ENTRY_CNT_2100;
2476 rsp_length = RESPONSE_ENTRY_CNT_2100;
2477 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2478 ha->gid_list_info_size = 4;
2479 ha->flash_conf_off = ~0;
2480 ha->flash_data_off = ~0;
2481 ha->nvram_conf_off = ~0;
2482 ha->nvram_data_off = ~0;
2483 ha->isp_ops = &qla2100_isp_ops;
2484 } else if (IS_QLA2200(ha)) {
2485 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2486 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2487 req_length = REQUEST_ENTRY_CNT_2200;
2488 rsp_length = RESPONSE_ENTRY_CNT_2100;
2489 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2490 ha->gid_list_info_size = 4;
2491 ha->flash_conf_off = ~0;
2492 ha->flash_data_off = ~0;
2493 ha->nvram_conf_off = ~0;
2494 ha->nvram_data_off = ~0;
2495 ha->isp_ops = &qla2100_isp_ops;
2496 } else if (IS_QLA23XX(ha)) {
2497 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2498 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2499 req_length = REQUEST_ENTRY_CNT_2200;
2500 rsp_length = RESPONSE_ENTRY_CNT_2300;
2501 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2502 ha->gid_list_info_size = 6;
2503 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2504 ha->optrom_size = OPTROM_SIZE_2322;
2505 ha->flash_conf_off = ~0;
2506 ha->flash_data_off = ~0;
2507 ha->nvram_conf_off = ~0;
2508 ha->nvram_data_off = ~0;
2509 ha->isp_ops = &qla2300_isp_ops;
2510 } else if (IS_QLA24XX_TYPE(ha)) {
2511 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2512 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2513 req_length = REQUEST_ENTRY_CNT_24XX;
2514 rsp_length = RESPONSE_ENTRY_CNT_2300;
2515 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2516 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2517 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2518 ha->gid_list_info_size = 8;
2519 ha->optrom_size = OPTROM_SIZE_24XX;
2520 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2521 ha->isp_ops = &qla24xx_isp_ops;
2522 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2523 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2524 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2525 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2526 } else if (IS_QLA25XX(ha)) {
2527 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2528 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2529 req_length = REQUEST_ENTRY_CNT_24XX;
2530 rsp_length = RESPONSE_ENTRY_CNT_2300;
2531 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2532 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2533 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2534 ha->gid_list_info_size = 8;
2535 ha->optrom_size = OPTROM_SIZE_25XX;
2536 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2537 ha->isp_ops = &qla25xx_isp_ops;
2538 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2539 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2540 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2541 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2542 } else if (IS_QLA81XX(ha)) {
2543 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2544 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2545 req_length = REQUEST_ENTRY_CNT_24XX;
2546 rsp_length = RESPONSE_ENTRY_CNT_2300;
2547 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2548 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2549 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2550 ha->gid_list_info_size = 8;
2551 ha->optrom_size = OPTROM_SIZE_81XX;
2552 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2553 ha->isp_ops = &qla81xx_isp_ops;
2554 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2555 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2556 ha->nvram_conf_off = ~0;
2557 ha->nvram_data_off = ~0;
2558 } else if (IS_QLA82XX(ha)) {
2559 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2560 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2561 req_length = REQUEST_ENTRY_CNT_82XX;
2562 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2563 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2564 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2565 ha->gid_list_info_size = 8;
2566 ha->optrom_size = OPTROM_SIZE_82XX;
2567 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2568 ha->isp_ops = &qla82xx_isp_ops;
2569 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2570 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2571 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2572 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2573 } else if (IS_QLA8044(ha)) {
2574 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2575 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2576 req_length = REQUEST_ENTRY_CNT_82XX;
2577 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2578 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2579 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2580 ha->gid_list_info_size = 8;
2581 ha->optrom_size = OPTROM_SIZE_83XX;
2582 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2583 ha->isp_ops = &qla8044_isp_ops;
2584 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2585 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2586 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2587 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2588 } else if (IS_QLA83XX(ha)) {
2589 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2590 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2591 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2592 req_length = REQUEST_ENTRY_CNT_83XX;
2593 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2594 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2595 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2596 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2597 ha->gid_list_info_size = 8;
2598 ha->optrom_size = OPTROM_SIZE_83XX;
2599 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2600 ha->isp_ops = &qla83xx_isp_ops;
2601 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2602 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2603 ha->nvram_conf_off = ~0;
2604 ha->nvram_data_off = ~0;
2605 } else if (IS_QLAFX00(ha)) {
2606 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2607 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2608 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2609 req_length = REQUEST_ENTRY_CNT_FX00;
2610 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2611 ha->isp_ops = &qlafx00_isp_ops;
2612 ha->port_down_retry_count = 30; /* default value */
2613 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2614 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2615 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2616 ha->mr.fw_hbt_en = 1;
2617 ha->mr.host_info_resend = false;
2618 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2619 } else if (IS_QLA27XX(ha)) {
2620 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2621 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2622 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2623 req_length = REQUEST_ENTRY_CNT_83XX;
2624 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2625 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2626 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2627 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2628 ha->gid_list_info_size = 8;
2629 ha->optrom_size = OPTROM_SIZE_83XX;
2630 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2631 ha->isp_ops = &qla27xx_isp_ops;
2632 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2633 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2634 ha->nvram_conf_off = ~0;
2635 ha->nvram_data_off = ~0;
2636 }
2637
2638 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2639 "mbx_count=%d, req_length=%d, "
2640 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2641 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2642 "max_fibre_devices=%d.\n",
2643 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2644 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2645 ha->nvram_npiv_size, ha->max_fibre_devices);
2646 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2647 "isp_ops=%p, flash_conf_off=%d, "
2648 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2649 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2650 ha->nvram_conf_off, ha->nvram_data_off);
2651
2652 /* Configure PCI I/O space */
2653 ret = ha->isp_ops->iospace_config(ha);
2654 if (ret)
2655 goto iospace_config_failed;
2656
2657 ql_log_pci(ql_log_info, pdev, 0x001d,
2658 "Found an ISP%04X irq %d iobase 0x%p.\n",
2659 pdev->device, pdev->irq, ha->iobase);
2660 mutex_init(&ha->vport_lock);
2661 init_completion(&ha->mbx_cmd_comp);
2662 complete(&ha->mbx_cmd_comp);
2663 init_completion(&ha->mbx_intr_comp);
2664 init_completion(&ha->dcbx_comp);
2665 init_completion(&ha->lb_portup_comp);
2666
2667 set_bit(0, (unsigned long *) ha->vp_idx_map);
2668
2669 qla2x00_config_dma_addressing(ha);
2670 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2671 "64 Bit addressing is %s.\n",
2672 ha->flags.enable_64bit_addressing ? "enable" :
2673 "disable");
2674 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2675 if (ret) {
2676 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2677 "Failed to allocate memory for adapter, aborting.\n");
2678
2679 goto probe_hw_failed;
2680 }
2681
2682 req->max_q_depth = MAX_Q_DEPTH;
2683 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2684 req->max_q_depth = ql2xmaxqdepth;
2685
2686
2687 base_vha = qla2x00_create_host(sht, ha);
2688 if (!base_vha) {
2689 ret = -ENOMEM;
2690 qla2x00_mem_free(ha);
2691 qla2x00_free_req_que(ha, req);
2692 qla2x00_free_rsp_que(ha, rsp);
2693 goto probe_hw_failed;
2694 }
2695
2696 pci_set_drvdata(pdev, base_vha);
2697 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2698
2699 host = base_vha->host;
2700 base_vha->req = req;
2701 if (IS_QLA2XXX_MIDTYPE(ha))
2702 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2703 else
2704 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2705 base_vha->vp_idx;
2706
2707 /* Setup fcport template structure. */
2708 ha->mr.fcport.vha = base_vha;
2709 ha->mr.fcport.port_type = FCT_UNKNOWN;
2710 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2711 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2712 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2713 ha->mr.fcport.scan_state = 1;
2714
2715 /* Set the SG table size based on ISP type */
2716 if (!IS_FWI2_CAPABLE(ha)) {
2717 if (IS_QLA2100(ha))
2718 host->sg_tablesize = 32;
2719 } else {
2720 if (!IS_QLA82XX(ha))
2721 host->sg_tablesize = QLA_SG_ALL;
2722 }
2723 host->max_id = ha->max_fibre_devices;
2724 host->cmd_per_lun = 3;
2725 host->unique_id = host->host_no;
2726 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2727 host->max_cmd_len = 32;
2728 else
2729 host->max_cmd_len = MAX_CMDSZ;
2730 host->max_channel = MAX_BUSES - 1;
2731 /* Older HBAs support only 16-bit LUNs */
2732 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2733 ql2xmaxlun > 0xffff)
2734 host->max_lun = 0xffff;
2735 else
2736 host->max_lun = ql2xmaxlun;
2737 host->transportt = qla2xxx_transport_template;
2738 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2739
2740 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2741 "max_id=%d this_id=%d "
2742 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2743 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2744 host->this_id, host->cmd_per_lun, host->unique_id,
2745 host->max_cmd_len, host->max_channel, host->max_lun,
2746 host->transportt, sht->vendor_id);
2747
2748 que_init:
2749 /* Alloc arrays of request and response ring ptrs */
2750 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2751 ql_log(ql_log_fatal, base_vha, 0x003d,
2752 "Failed to allocate memory for queue pointers..."
2753 "aborting.\n");
2754 goto probe_init_failed;
2755 }
2756
2757 qlt_probe_one_stage1(base_vha, ha);
2758
2759 /* Set up the irqs */
2760 ret = qla2x00_request_irqs(ha, rsp);
2761 if (ret)
2762 goto probe_init_failed;
2763
2764 pci_save_state(pdev);
2765
2766 /* Assign back pointers */
2767 rsp->req = req;
2768 req->rsp = rsp;
2769
2770 if (IS_QLAFX00(ha)) {
2771 ha->rsp_q_map[0] = rsp;
2772 ha->req_q_map[0] = req;
2773 set_bit(0, ha->req_qid_map);
2774 set_bit(0, ha->rsp_qid_map);
2775 }
2776
2777 /* FWI2-capable only. */
2778 req->req_q_in = &ha->iobase->isp24.req_q_in;
2779 req->req_q_out = &ha->iobase->isp24.req_q_out;
2780 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2781 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2782 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2783 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2784 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2785 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2786 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2787 }
2788
2789 if (IS_QLAFX00(ha)) {
2790 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2791 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2792 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2793 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2794 }
2795
2796 if (IS_P3P_TYPE(ha)) {
2797 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2798 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2799 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2800 }
2801
2802 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2803 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2804 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2805 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2806 "req->req_q_in=%p req->req_q_out=%p "
2807 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2808 req->req_q_in, req->req_q_out,
2809 rsp->rsp_q_in, rsp->rsp_q_out);
2810 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2811 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2812 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2813 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2814 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2815 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2816
2817 if (ha->isp_ops->initialize_adapter(base_vha)) {
2818 ql_log(ql_log_fatal, base_vha, 0x00d6,
2819 "Failed to initialize adapter - Adapter flags %x.\n",
2820 base_vha->device_flags);
2821
2822 if (IS_QLA82XX(ha)) {
2823 qla82xx_idc_lock(ha);
2824 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2825 QLA8XXX_DEV_FAILED);
2826 qla82xx_idc_unlock(ha);
2827 ql_log(ql_log_fatal, base_vha, 0x00d7,
2828 "HW State: FAILED.\n");
2829 } else if (IS_QLA8044(ha)) {
2830 qla8044_idc_lock(ha);
2831 qla8044_wr_direct(base_vha,
2832 QLA8044_CRB_DEV_STATE_INDEX,
2833 QLA8XXX_DEV_FAILED);
2834 qla8044_idc_unlock(ha);
2835 ql_log(ql_log_fatal, base_vha, 0x0150,
2836 "HW State: FAILED.\n");
2837 }
2838
2839 ret = -ENODEV;
2840 goto probe_failed;
2841 }
2842
2843 if (IS_QLAFX00(ha))
2844 host->can_queue = QLAFX00_MAX_CANQUEUE;
2845 else
2846 host->can_queue = req->num_outstanding_cmds - 10;
2847
2848 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2849 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2850 host->can_queue, base_vha->req,
2851 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2852
2853 if (ha->mqenable) {
2854 if (qla25xx_setup_mode(base_vha)) {
2855 ql_log(ql_log_warn, base_vha, 0x00ec,
2856 "Failed to create queues, falling back to single queue mode.\n");
2857 goto que_init;
2858 }
2859 }
2860
2861 if (ha->flags.running_gold_fw)
2862 goto skip_dpc;
2863
2864 /*
2865 * Startup the kernel thread for this host adapter
2866 */
2867 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2868 "%s_dpc", base_vha->host_str);
2869 if (IS_ERR(ha->dpc_thread)) {
2870 ql_log(ql_log_fatal, base_vha, 0x00ed,
2871 "Failed to start DPC thread.\n");
2872 ret = PTR_ERR(ha->dpc_thread);
2873 goto probe_failed;
2874 }
2875 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2876 "DPC thread started successfully.\n");
2877
2878 /*
2879 * If we're not coming up in initiator mode, we might sit for
2880 * a while without waking up the dpc thread, which leads to a
2881 * stuck process warning. So just kick the dpc once here and
2882 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2883 */
2884 qla2xxx_wake_dpc(base_vha);
2885
2886 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2887
2888 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2889 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2890 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2891 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2892
2893 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2894 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2895 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2896 INIT_WORK(&ha->idc_state_handler,
2897 qla83xx_idc_state_handler_work);
2898 INIT_WORK(&ha->nic_core_unrecoverable,
2899 qla83xx_nic_core_unrecoverable_work);
2900 }
2901
2902 skip_dpc:
2903 list_add_tail(&base_vha->list, &ha->vp_list);
2904 base_vha->host->irq = ha->pdev->irq;
2905
2906 /* Initialized the timer */
2907 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2908 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2909 "Started qla2x00_timer with "
2910 "interval=%d.\n", WATCH_INTERVAL);
2911 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2912 "Detected hba at address=%p.\n",
2913 ha);
2914
2915 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2916 if (ha->fw_attributes & BIT_4) {
2917 int prot = 0, guard;
2918 base_vha->flags.difdix_supported = 1;
2919 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2920 "Registering for DIF/DIX type 1 and 3 protection.\n");
2921 if (ql2xenabledif == 1)
2922 prot = SHOST_DIX_TYPE0_PROTECTION;
2923 scsi_host_set_prot(host,
2924 prot | SHOST_DIF_TYPE1_PROTECTION
2925 | SHOST_DIF_TYPE2_PROTECTION
2926 | SHOST_DIF_TYPE3_PROTECTION
2927 | SHOST_DIX_TYPE1_PROTECTION
2928 | SHOST_DIX_TYPE2_PROTECTION
2929 | SHOST_DIX_TYPE3_PROTECTION);
2930
2931 guard = SHOST_DIX_GUARD_CRC;
2932
2933 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2934 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2935 guard |= SHOST_DIX_GUARD_IP;
2936
2937 scsi_host_set_guard(host, guard);
2938 } else
2939 base_vha->flags.difdix_supported = 0;
2940 }
2941
2942 ha->isp_ops->enable_intrs(ha);
2943
2944 if (IS_QLAFX00(ha)) {
2945 ret = qlafx00_fx_disc(base_vha,
2946 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2947 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2948 QLA_SG_ALL : 128;
2949 }
2950
2951 ret = scsi_add_host(host, &pdev->dev);
2952 if (ret)
2953 goto probe_failed;
2954
2955 base_vha->flags.init_done = 1;
2956 base_vha->flags.online = 1;
2957 ha->prev_minidump_failed = 0;
2958
2959 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2960 "Init done and hba is online.\n");
2961
2962 if (qla_ini_mode_enabled(base_vha))
2963 scsi_scan_host(host);
2964 else
2965 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2966 "skipping scsi_scan_host() for non-initiator port\n");
2967
2968 qla2x00_alloc_sysfs_attr(base_vha);
2969
2970 if (IS_QLAFX00(ha)) {
2971 ret = qlafx00_fx_disc(base_vha,
2972 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2973
2974 /* Register system information */
2975 ret = qlafx00_fx_disc(base_vha,
2976 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2977 }
2978
2979 qla2x00_init_host_attr(base_vha);
2980
2981 qla2x00_dfs_setup(base_vha);
2982
2983 ql_log(ql_log_info, base_vha, 0x00fb,
2984 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2985 ql_log(ql_log_info, base_vha, 0x00fc,
2986 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2987 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2988 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2989 base_vha->host_no,
2990 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2991
2992 qlt_add_target(ha, base_vha);
2993
2994 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2995
2996 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2997 return -ENODEV;
2998
2999 return 0;
3000
3001 probe_init_failed:
3002 qla2x00_free_req_que(ha, req);
3003 ha->req_q_map[0] = NULL;
3004 clear_bit(0, ha->req_qid_map);
3005 qla2x00_free_rsp_que(ha, rsp);
3006 ha->rsp_q_map[0] = NULL;
3007 clear_bit(0, ha->rsp_qid_map);
3008 ha->max_req_queues = ha->max_rsp_queues = 0;
3009
3010 probe_failed:
3011 if (base_vha->timer_active)
3012 qla2x00_stop_timer(base_vha);
3013 base_vha->flags.online = 0;
3014 if (ha->dpc_thread) {
3015 struct task_struct *t = ha->dpc_thread;
3016
3017 ha->dpc_thread = NULL;
3018 kthread_stop(t);
3019 }
3020
3021 qla2x00_free_device(base_vha);
3022
3023 scsi_host_put(base_vha->host);
3024
3025 probe_hw_failed:
3026 qla2x00_clear_drv_active(ha);
3027
3028 iospace_config_failed:
3029 if (IS_P3P_TYPE(ha)) {
3030 if (!ha->nx_pcibase)
3031 iounmap((device_reg_t *)ha->nx_pcibase);
3032 if (!ql2xdbwr)
3033 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3034 } else {
3035 if (ha->iobase)
3036 iounmap(ha->iobase);
3037 if (ha->cregbase)
3038 iounmap(ha->cregbase);
3039 }
3040 pci_release_selected_regions(ha->pdev, ha->bars);
3041 kfree(ha);
3042 ha = NULL;
3043
3044 disable_device:
3045 pci_disable_device(pdev);
3046 return ret;
3047 }
3048
3049 static void
3050 qla2x00_shutdown(struct pci_dev *pdev)
3051 {
3052 scsi_qla_host_t *vha;
3053 struct qla_hw_data *ha;
3054
3055 if (!atomic_read(&pdev->enable_cnt))
3056 return;
3057
3058 vha = pci_get_drvdata(pdev);
3059 ha = vha->hw;
3060
3061 /* Notify ISPFX00 firmware */
3062 if (IS_QLAFX00(ha))
3063 qlafx00_driver_shutdown(vha, 20);
3064
3065 /* Turn-off FCE trace */
3066 if (ha->flags.fce_enabled) {
3067 qla2x00_disable_fce_trace(vha, NULL, NULL);
3068 ha->flags.fce_enabled = 0;
3069 }
3070
3071 /* Turn-off EFT trace */
3072 if (ha->eft)
3073 qla2x00_disable_eft_trace(vha);
3074
3075 /* Stop currently executing firmware. */
3076 qla2x00_try_to_stop_firmware(vha);
3077
3078 /* Turn adapter off line */
3079 vha->flags.online = 0;
3080
3081 /* turn-off interrupts on the card */
3082 if (ha->interrupts_on) {
3083 vha->flags.init_done = 0;
3084 ha->isp_ops->disable_intrs(ha);
3085 }
3086
3087 qla2x00_free_irqs(vha);
3088
3089 qla2x00_free_fw_dump(ha);
3090
3091 pci_disable_pcie_error_reporting(pdev);
3092 pci_disable_device(pdev);
3093 }
3094
3095 /* Deletes all the virtual ports for a given ha */
3096 static void
3097 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3098 {
3099 scsi_qla_host_t *vha;
3100 unsigned long flags;
3101
3102 mutex_lock(&ha->vport_lock);
3103 while (ha->cur_vport_count) {
3104 spin_lock_irqsave(&ha->vport_slock, flags);
3105
3106 BUG_ON(base_vha->list.next == &ha->vp_list);
3107 /* This assumes first entry in ha->vp_list is always base vha */
3108 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3109 scsi_host_get(vha->host);
3110
3111 spin_unlock_irqrestore(&ha->vport_slock, flags);
3112 mutex_unlock(&ha->vport_lock);
3113
3114 fc_vport_terminate(vha->fc_vport);
3115 scsi_host_put(vha->host);
3116
3117 mutex_lock(&ha->vport_lock);
3118 }
3119 mutex_unlock(&ha->vport_lock);
3120 }
3121
3122 /* Stops all deferred work threads */
3123 static void
3124 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3125 {
3126 /* Flush the work queue and remove it */
3127 if (ha->wq) {
3128 flush_workqueue(ha->wq);
3129 destroy_workqueue(ha->wq);
3130 ha->wq = NULL;
3131 }
3132
3133 /* Cancel all work and destroy DPC workqueues */
3134 if (ha->dpc_lp_wq) {
3135 cancel_work_sync(&ha->idc_aen);
3136 destroy_workqueue(ha->dpc_lp_wq);
3137 ha->dpc_lp_wq = NULL;
3138 }
3139
3140 if (ha->dpc_hp_wq) {
3141 cancel_work_sync(&ha->nic_core_reset);
3142 cancel_work_sync(&ha->idc_state_handler);
3143 cancel_work_sync(&ha->nic_core_unrecoverable);
3144 destroy_workqueue(ha->dpc_hp_wq);
3145 ha->dpc_hp_wq = NULL;
3146 }
3147
3148 /* Kill the kernel thread for this host */
3149 if (ha->dpc_thread) {
3150 struct task_struct *t = ha->dpc_thread;
3151
3152 /*
3153 * qla2xxx_wake_dpc checks for ->dpc_thread
3154 * so we need to zero it out.
3155 */
3156 ha->dpc_thread = NULL;
3157 kthread_stop(t);
3158 }
3159 }
3160
3161 static void
3162 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3163 {
3164 if (IS_QLA82XX(ha)) {
3165
3166 iounmap((device_reg_t *)ha->nx_pcibase);
3167 if (!ql2xdbwr)
3168 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3169 } else {
3170 if (ha->iobase)
3171 iounmap(ha->iobase);
3172
3173 if (ha->cregbase)
3174 iounmap(ha->cregbase);
3175
3176 if (ha->mqiobase)
3177 iounmap(ha->mqiobase);
3178
3179 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3180 iounmap(ha->msixbase);
3181 }
3182 }
3183
3184 static void
3185 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3186 {
3187 if (IS_QLA8044(ha)) {
3188 qla8044_idc_lock(ha);
3189 qla8044_clear_drv_active(ha);
3190 qla8044_idc_unlock(ha);
3191 } else if (IS_QLA82XX(ha)) {
3192 qla82xx_idc_lock(ha);
3193 qla82xx_clear_drv_active(ha);
3194 qla82xx_idc_unlock(ha);
3195 }
3196 }
3197
3198 static void
3199 qla2x00_remove_one(struct pci_dev *pdev)
3200 {
3201 scsi_qla_host_t *base_vha;
3202 struct qla_hw_data *ha;
3203
3204 base_vha = pci_get_drvdata(pdev);
3205 ha = base_vha->hw;
3206
3207 /* Indicate device removal to prevent future board_disable and wait
3208 * until any pending board_disable has completed. */
3209 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3210 cancel_work_sync(&ha->board_disable);
3211
3212 /*
3213 * If the PCI device is disabled then there was a PCI-disconnect and
3214 * qla2x00_disable_board_on_pci_error has taken care of most of the
3215 * resources.
3216 */
3217 if (!atomic_read(&pdev->enable_cnt)) {
3218 scsi_host_put(base_vha->host);
3219 kfree(ha);
3220 pci_set_drvdata(pdev, NULL);
3221 return;
3222 }
3223
3224 qla2x00_wait_for_hba_ready(base_vha);
3225
3226 /* if UNLOAD flag is already set, then continue unload,
3227 * where it was set first.
3228 */
3229 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3230 return;
3231
3232 set_bit(UNLOADING, &base_vha->dpc_flags);
3233
3234 if (IS_QLAFX00(ha))
3235 qlafx00_driver_shutdown(base_vha, 20);
3236
3237 qla2x00_delete_all_vps(ha, base_vha);
3238
3239 if (IS_QLA8031(ha)) {
3240 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3241 "Clearing fcoe driver presence.\n");
3242 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3243 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3244 "Error while clearing DRV-Presence.\n");
3245 }
3246
3247 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3248
3249 qla2x00_dfs_remove(base_vha);
3250
3251 qla84xx_put_chip(base_vha);
3252
3253 /* Laser should be disabled only for ISP2031 */
3254 if (IS_QLA2031(ha))
3255 qla83xx_disable_laser(base_vha);
3256
3257 /* Disable timer */
3258 if (base_vha->timer_active)
3259 qla2x00_stop_timer(base_vha);
3260
3261 base_vha->flags.online = 0;
3262
3263 /* free DMA memory */
3264 if (ha->exlogin_buf)
3265 qla2x00_free_exlogin_buffer(ha);
3266
3267 /* free DMA memory */
3268 if (ha->exchoffld_buf)
3269 qla2x00_free_exchoffld_buffer(ha);
3270
3271 qla2x00_destroy_deferred_work(ha);
3272
3273 qlt_remove_target(ha, base_vha);
3274
3275 qla2x00_free_sysfs_attr(base_vha, true);
3276
3277 fc_remove_host(base_vha->host);
3278
3279 scsi_remove_host(base_vha->host);
3280
3281 qla2x00_free_device(base_vha);
3282
3283 qla2x00_clear_drv_active(ha);
3284
3285 scsi_host_put(base_vha->host);
3286
3287 qla2x00_unmap_iobases(ha);
3288
3289 pci_release_selected_regions(ha->pdev, ha->bars);
3290 kfree(ha);
3291 ha = NULL;
3292
3293 pci_disable_pcie_error_reporting(pdev);
3294
3295 pci_disable_device(pdev);
3296 }
3297
3298 static void
3299 qla2x00_free_device(scsi_qla_host_t *vha)
3300 {
3301 struct qla_hw_data *ha = vha->hw;
3302
3303 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3304
3305 /* Disable timer */
3306 if (vha->timer_active)
3307 qla2x00_stop_timer(vha);
3308
3309 qla25xx_delete_queues(vha);
3310
3311 if (ha->flags.fce_enabled)
3312 qla2x00_disable_fce_trace(vha, NULL, NULL);
3313
3314 if (ha->eft)
3315 qla2x00_disable_eft_trace(vha);
3316
3317 /* Stop currently executing firmware. */
3318 qla2x00_try_to_stop_firmware(vha);
3319
3320 vha->flags.online = 0;
3321
3322 /* turn-off interrupts on the card */
3323 if (ha->interrupts_on) {
3324 vha->flags.init_done = 0;
3325 ha->isp_ops->disable_intrs(ha);
3326 }
3327
3328 qla2x00_free_irqs(vha);
3329
3330 qla2x00_free_fcports(vha);
3331
3332 qla2x00_mem_free(ha);
3333
3334 qla82xx_md_free(vha);
3335
3336 qla2x00_free_queues(ha);
3337 }
3338
3339 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3340 {
3341 fc_port_t *fcport, *tfcport;
3342
3343 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3344 list_del(&fcport->list);
3345 qla2x00_clear_loop_id(fcport);
3346 kfree(fcport);
3347 fcport = NULL;
3348 }
3349 }
3350
3351 static inline void
3352 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3353 int defer)
3354 {
3355 struct fc_rport *rport;
3356 scsi_qla_host_t *base_vha;
3357 unsigned long flags;
3358
3359 if (!fcport->rport)
3360 return;
3361
3362 rport = fcport->rport;
3363 if (defer) {
3364 base_vha = pci_get_drvdata(vha->hw->pdev);
3365 spin_lock_irqsave(vha->host->host_lock, flags);
3366 fcport->drport = rport;
3367 spin_unlock_irqrestore(vha->host->host_lock, flags);
3368 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3369 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3370 qla2xxx_wake_dpc(base_vha);
3371 } else {
3372 int now;
3373 if (rport)
3374 fc_remote_port_delete(rport);
3375 qlt_do_generation_tick(vha, &now);
3376 qlt_fc_port_deleted(vha, fcport, now);
3377 }
3378 }
3379
3380 /*
3381 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3382 *
3383 * Input: ha = adapter block pointer. fcport = port structure pointer.
3384 *
3385 * Return: None.
3386 *
3387 * Context:
3388 */
3389 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3390 int do_login, int defer)
3391 {
3392 if (IS_QLAFX00(vha->hw)) {
3393 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3394 qla2x00_schedule_rport_del(vha, fcport, defer);
3395 return;
3396 }
3397
3398 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3399 vha->vp_idx == fcport->vha->vp_idx) {
3400 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3401 qla2x00_schedule_rport_del(vha, fcport, defer);
3402 }
3403 /*
3404 * We may need to retry the login, so don't change the state of the
3405 * port but do the retries.
3406 */
3407 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3408 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3409
3410 if (!do_login)
3411 return;
3412
3413 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3414
3415 if (fcport->login_retry == 0) {
3416 fcport->login_retry = vha->hw->login_retry_count;
3417
3418 ql_dbg(ql_dbg_disc, vha, 0x2067,
3419 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3420 fcport->port_name, fcport->loop_id, fcport->login_retry);
3421 }
3422 }
3423
3424 /*
3425 * qla2x00_mark_all_devices_lost
3426 * Updates fcport state when device goes offline.
3427 *
3428 * Input:
3429 * ha = adapter block pointer.
3430 * fcport = port structure pointer.
3431 *
3432 * Return:
3433 * None.
3434 *
3435 * Context:
3436 */
3437 void
3438 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3439 {
3440 fc_port_t *fcport;
3441
3442 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3443 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3444 continue;
3445
3446 /*
3447 * No point in marking the device as lost, if the device is
3448 * already DEAD.
3449 */
3450 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3451 continue;
3452 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3453 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3454 if (defer)
3455 qla2x00_schedule_rport_del(vha, fcport, defer);
3456 else if (vha->vp_idx == fcport->vha->vp_idx)
3457 qla2x00_schedule_rport_del(vha, fcport, defer);
3458 }
3459 }
3460 }
3461
3462 /*
3463 * qla2x00_mem_alloc
3464 * Allocates adapter memory.
3465 *
3466 * Returns:
3467 * 0 = success.
3468 * !0 = failure.
3469 */
3470 static int
3471 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3472 struct req_que **req, struct rsp_que **rsp)
3473 {
3474 char name[16];
3475
3476 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3477 &ha->init_cb_dma, GFP_KERNEL);
3478 if (!ha->init_cb)
3479 goto fail;
3480
3481 if (qlt_mem_alloc(ha) < 0)
3482 goto fail_free_init_cb;
3483
3484 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3485 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3486 if (!ha->gid_list)
3487 goto fail_free_tgt_mem;
3488
3489 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3490 if (!ha->srb_mempool)
3491 goto fail_free_gid_list;
3492
3493 if (IS_P3P_TYPE(ha)) {
3494 /* Allocate cache for CT6 Ctx. */
3495 if (!ctx_cachep) {
3496 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3497 sizeof(struct ct6_dsd), 0,
3498 SLAB_HWCACHE_ALIGN, NULL);
3499 if (!ctx_cachep)
3500 goto fail_free_srb_mempool;
3501 }
3502 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3503 ctx_cachep);
3504 if (!ha->ctx_mempool)
3505 goto fail_free_srb_mempool;
3506 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3507 "ctx_cachep=%p ctx_mempool=%p.\n",
3508 ctx_cachep, ha->ctx_mempool);
3509 }
3510
3511 /* Get memory for cached NVRAM */
3512 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3513 if (!ha->nvram)
3514 goto fail_free_ctx_mempool;
3515
3516 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3517 ha->pdev->device);
3518 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3519 DMA_POOL_SIZE, 8, 0);
3520 if (!ha->s_dma_pool)
3521 goto fail_free_nvram;
3522
3523 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3524 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3525 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3526
3527 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3528 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3529 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3530 if (!ha->dl_dma_pool) {
3531 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3532 "Failed to allocate memory for dl_dma_pool.\n");
3533 goto fail_s_dma_pool;
3534 }
3535
3536 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3537 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3538 if (!ha->fcp_cmnd_dma_pool) {
3539 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3540 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3541 goto fail_dl_dma_pool;
3542 }
3543 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3544 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3545 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3546 }
3547
3548 /* Allocate memory for SNS commands */
3549 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3550 /* Get consistent memory allocated for SNS commands */
3551 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3552 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3553 if (!ha->sns_cmd)
3554 goto fail_dma_pool;
3555 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3556 "sns_cmd: %p.\n", ha->sns_cmd);
3557 } else {
3558 /* Get consistent memory allocated for MS IOCB */
3559 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3560 &ha->ms_iocb_dma);
3561 if (!ha->ms_iocb)
3562 goto fail_dma_pool;
3563 /* Get consistent memory allocated for CT SNS commands */
3564 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3565 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3566 if (!ha->ct_sns)
3567 goto fail_free_ms_iocb;
3568 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3569 "ms_iocb=%p ct_sns=%p.\n",
3570 ha->ms_iocb, ha->ct_sns);
3571 }
3572
3573 /* Allocate memory for request ring */
3574 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3575 if (!*req) {
3576 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3577 "Failed to allocate memory for req.\n");
3578 goto fail_req;
3579 }
3580 (*req)->length = req_len;
3581 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3582 ((*req)->length + 1) * sizeof(request_t),
3583 &(*req)->dma, GFP_KERNEL);
3584 if (!(*req)->ring) {
3585 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3586 "Failed to allocate memory for req_ring.\n");
3587 goto fail_req_ring;
3588 }
3589 /* Allocate memory for response ring */
3590 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3591 if (!*rsp) {
3592 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3593 "Failed to allocate memory for rsp.\n");
3594 goto fail_rsp;
3595 }
3596 (*rsp)->hw = ha;
3597 (*rsp)->length = rsp_len;
3598 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3599 ((*rsp)->length + 1) * sizeof(response_t),
3600 &(*rsp)->dma, GFP_KERNEL);
3601 if (!(*rsp)->ring) {
3602 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3603 "Failed to allocate memory for rsp_ring.\n");
3604 goto fail_rsp_ring;
3605 }
3606 (*req)->rsp = *rsp;
3607 (*rsp)->req = *req;
3608 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3609 "req=%p req->length=%d req->ring=%p rsp=%p "
3610 "rsp->length=%d rsp->ring=%p.\n",
3611 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3612 (*rsp)->ring);
3613 /* Allocate memory for NVRAM data for vports */
3614 if (ha->nvram_npiv_size) {
3615 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3616 ha->nvram_npiv_size, GFP_KERNEL);
3617 if (!ha->npiv_info) {
3618 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3619 "Failed to allocate memory for npiv_info.\n");
3620 goto fail_npiv_info;
3621 }
3622 } else
3623 ha->npiv_info = NULL;
3624
3625 /* Get consistent memory allocated for EX-INIT-CB. */
3626 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3627 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3628 &ha->ex_init_cb_dma);
3629 if (!ha->ex_init_cb)
3630 goto fail_ex_init_cb;
3631 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3632 "ex_init_cb=%p.\n", ha->ex_init_cb);
3633 }
3634
3635 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3636
3637 /* Get consistent memory allocated for Async Port-Database. */
3638 if (!IS_FWI2_CAPABLE(ha)) {
3639 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3640 &ha->async_pd_dma);
3641 if (!ha->async_pd)
3642 goto fail_async_pd;
3643 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3644 "async_pd=%p.\n", ha->async_pd);
3645 }
3646
3647 INIT_LIST_HEAD(&ha->vp_list);
3648
3649 /* Allocate memory for our loop_id bitmap */
3650 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3651 GFP_KERNEL);
3652 if (!ha->loop_id_map)
3653 goto fail_loop_id_map;
3654 else {
3655 qla2x00_set_reserved_loop_ids(ha);
3656 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3657 "loop_id_map=%p.\n", ha->loop_id_map);
3658 }
3659
3660 return 0;
3661
3662 fail_loop_id_map:
3663 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3664 fail_async_pd:
3665 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3666 fail_ex_init_cb:
3667 kfree(ha->npiv_info);
3668 fail_npiv_info:
3669 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3670 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3671 (*rsp)->ring = NULL;
3672 (*rsp)->dma = 0;
3673 fail_rsp_ring:
3674 kfree(*rsp);
3675 fail_rsp:
3676 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3677 sizeof(request_t), (*req)->ring, (*req)->dma);
3678 (*req)->ring = NULL;
3679 (*req)->dma = 0;
3680 fail_req_ring:
3681 kfree(*req);
3682 fail_req:
3683 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3684 ha->ct_sns, ha->ct_sns_dma);
3685 ha->ct_sns = NULL;
3686 ha->ct_sns_dma = 0;
3687 fail_free_ms_iocb:
3688 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3689 ha->ms_iocb = NULL;
3690 ha->ms_iocb_dma = 0;
3691
3692 if (ha->sns_cmd)
3693 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3694 ha->sns_cmd, ha->sns_cmd_dma);
3695 fail_dma_pool:
3696 if (IS_QLA82XX(ha) || ql2xenabledif) {
3697 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3698 ha->fcp_cmnd_dma_pool = NULL;
3699 }
3700 fail_dl_dma_pool:
3701 if (IS_QLA82XX(ha) || ql2xenabledif) {
3702 dma_pool_destroy(ha->dl_dma_pool);
3703 ha->dl_dma_pool = NULL;
3704 }
3705 fail_s_dma_pool:
3706 dma_pool_destroy(ha->s_dma_pool);
3707 ha->s_dma_pool = NULL;
3708 fail_free_nvram:
3709 kfree(ha->nvram);
3710 ha->nvram = NULL;
3711 fail_free_ctx_mempool:
3712 if (ha->ctx_mempool)
3713 mempool_destroy(ha->ctx_mempool);
3714 ha->ctx_mempool = NULL;
3715 fail_free_srb_mempool:
3716 if (ha->srb_mempool)
3717 mempool_destroy(ha->srb_mempool);
3718 ha->srb_mempool = NULL;
3719 fail_free_gid_list:
3720 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3721 ha->gid_list,
3722 ha->gid_list_dma);
3723 ha->gid_list = NULL;
3724 ha->gid_list_dma = 0;
3725 fail_free_tgt_mem:
3726 qlt_mem_free(ha);
3727 fail_free_init_cb:
3728 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3729 ha->init_cb_dma);
3730 ha->init_cb = NULL;
3731 ha->init_cb_dma = 0;
3732 fail:
3733 ql_log(ql_log_fatal, NULL, 0x0030,
3734 "Memory allocation failure.\n");
3735 return -ENOMEM;
3736 }
3737
3738 int
3739 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3740 {
3741 int rval;
3742 uint16_t size, max_cnt, temp;
3743 struct qla_hw_data *ha = vha->hw;
3744
3745 /* Return if we don't need to alloacate any extended logins */
3746 if (!ql2xexlogins)
3747 return QLA_SUCCESS;
3748
3749 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3750 max_cnt = 0;
3751 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3752 if (rval != QLA_SUCCESS) {
3753 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3754 "Failed to get exlogin status.\n");
3755 return rval;
3756 }
3757
3758 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3759 ha->exlogin_size = (size * temp);
3760 ql_log(ql_log_info, vha, 0xd024,
3761 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3762 max_cnt, size, temp);
3763
3764 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3765 ha->exlogin_size);
3766
3767 /* Get consistent memory for extended logins */
3768 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3769 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3770 if (!ha->exlogin_buf) {
3771 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3772 "Failed to allocate memory for exlogin_buf_dma.\n");
3773 return -ENOMEM;
3774 }
3775
3776 /* Now configure the dma buffer */
3777 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3778 if (rval) {
3779 ql_log(ql_log_fatal, vha, 0x00cf,
3780 "Setup extended login buffer ****FAILED****.\n");
3781 qla2x00_free_exlogin_buffer(ha);
3782 }
3783
3784 return rval;
3785 }
3786
3787 /*
3788 * qla2x00_free_exlogin_buffer
3789 *
3790 * Input:
3791 * ha = adapter block pointer
3792 */
3793 void
3794 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3795 {
3796 if (ha->exlogin_buf) {
3797 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3798 ha->exlogin_buf, ha->exlogin_buf_dma);
3799 ha->exlogin_buf = NULL;
3800 ha->exlogin_size = 0;
3801 }
3802 }
3803
3804 int
3805 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3806 {
3807 int rval;
3808 uint16_t size, max_cnt, temp;
3809 struct qla_hw_data *ha = vha->hw;
3810
3811 /* Return if we don't need to alloacate any extended logins */
3812 if (!ql2xexchoffld)
3813 return QLA_SUCCESS;
3814
3815 ql_log(ql_log_info, vha, 0xd014,
3816 "Exchange offload count: %d.\n", ql2xexlogins);
3817
3818 max_cnt = 0;
3819 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3820 if (rval != QLA_SUCCESS) {
3821 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3822 "Failed to get exlogin status.\n");
3823 return rval;
3824 }
3825
3826 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3827 ha->exchoffld_size = (size * temp);
3828 ql_log(ql_log_info, vha, 0xd016,
3829 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3830 max_cnt, size, temp);
3831
3832 ql_log(ql_log_info, vha, 0xd017,
3833 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3834
3835 /* Get consistent memory for extended logins */
3836 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3837 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3838 if (!ha->exchoffld_buf) {
3839 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3840 "Failed to allocate memory for exchoffld_buf_dma.\n");
3841 return -ENOMEM;
3842 }
3843
3844 /* Now configure the dma buffer */
3845 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3846 if (rval) {
3847 ql_log(ql_log_fatal, vha, 0xd02e,
3848 "Setup exchange offload buffer ****FAILED****.\n");
3849 qla2x00_free_exchoffld_buffer(ha);
3850 }
3851
3852 return rval;
3853 }
3854
3855 /*
3856 * qla2x00_free_exchoffld_buffer
3857 *
3858 * Input:
3859 * ha = adapter block pointer
3860 */
3861 void
3862 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3863 {
3864 if (ha->exchoffld_buf) {
3865 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3866 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3867 ha->exchoffld_buf = NULL;
3868 ha->exchoffld_size = 0;
3869 }
3870 }
3871
3872 /*
3873 * qla2x00_free_fw_dump
3874 * Frees fw dump stuff.
3875 *
3876 * Input:
3877 * ha = adapter block pointer
3878 */
3879 static void
3880 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3881 {
3882 if (ha->fce)
3883 dma_free_coherent(&ha->pdev->dev,
3884 FCE_SIZE, ha->fce, ha->fce_dma);
3885
3886 if (ha->eft)
3887 dma_free_coherent(&ha->pdev->dev,
3888 EFT_SIZE, ha->eft, ha->eft_dma);
3889
3890 if (ha->fw_dump)
3891 vfree(ha->fw_dump);
3892 if (ha->fw_dump_template)
3893 vfree(ha->fw_dump_template);
3894
3895 ha->fce = NULL;
3896 ha->fce_dma = 0;
3897 ha->eft = NULL;
3898 ha->eft_dma = 0;
3899 ha->fw_dumped = 0;
3900 ha->fw_dump_cap_flags = 0;
3901 ha->fw_dump_reading = 0;
3902 ha->fw_dump = NULL;
3903 ha->fw_dump_len = 0;
3904 ha->fw_dump_template = NULL;
3905 ha->fw_dump_template_len = 0;
3906 }
3907
3908 /*
3909 * qla2x00_mem_free
3910 * Frees all adapter allocated memory.
3911 *
3912 * Input:
3913 * ha = adapter block pointer.
3914 */
3915 static void
3916 qla2x00_mem_free(struct qla_hw_data *ha)
3917 {
3918 qla2x00_free_fw_dump(ha);
3919
3920 if (ha->mctp_dump)
3921 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3922 ha->mctp_dump_dma);
3923
3924 if (ha->srb_mempool)
3925 mempool_destroy(ha->srb_mempool);
3926
3927 if (ha->dcbx_tlv)
3928 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3929 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3930
3931 if (ha->xgmac_data)
3932 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3933 ha->xgmac_data, ha->xgmac_data_dma);
3934
3935 if (ha->sns_cmd)
3936 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3937 ha->sns_cmd, ha->sns_cmd_dma);
3938
3939 if (ha->ct_sns)
3940 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3941 ha->ct_sns, ha->ct_sns_dma);
3942
3943 if (ha->sfp_data)
3944 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3945
3946 if (ha->ms_iocb)
3947 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3948
3949 if (ha->ex_init_cb)
3950 dma_pool_free(ha->s_dma_pool,
3951 ha->ex_init_cb, ha->ex_init_cb_dma);
3952
3953 if (ha->async_pd)
3954 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3955
3956 if (ha->s_dma_pool)
3957 dma_pool_destroy(ha->s_dma_pool);
3958
3959 if (ha->gid_list)
3960 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3961 ha->gid_list, ha->gid_list_dma);
3962
3963 if (IS_QLA82XX(ha)) {
3964 if (!list_empty(&ha->gbl_dsd_list)) {
3965 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3966
3967 /* clean up allocated prev pool */
3968 list_for_each_entry_safe(dsd_ptr,
3969 tdsd_ptr, &ha->gbl_dsd_list, list) {
3970 dma_pool_free(ha->dl_dma_pool,
3971 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3972 list_del(&dsd_ptr->list);
3973 kfree(dsd_ptr);
3974 }
3975 }
3976 }
3977
3978 if (ha->dl_dma_pool)
3979 dma_pool_destroy(ha->dl_dma_pool);
3980
3981 if (ha->fcp_cmnd_dma_pool)
3982 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3983
3984 if (ha->ctx_mempool)
3985 mempool_destroy(ha->ctx_mempool);
3986
3987 qlt_mem_free(ha);
3988
3989 if (ha->init_cb)
3990 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3991 ha->init_cb, ha->init_cb_dma);
3992 vfree(ha->optrom_buffer);
3993 kfree(ha->nvram);
3994 kfree(ha->npiv_info);
3995 kfree(ha->swl);
3996 kfree(ha->loop_id_map);
3997
3998 ha->srb_mempool = NULL;
3999 ha->ctx_mempool = NULL;
4000 ha->sns_cmd = NULL;
4001 ha->sns_cmd_dma = 0;
4002 ha->ct_sns = NULL;
4003 ha->ct_sns_dma = 0;
4004 ha->ms_iocb = NULL;
4005 ha->ms_iocb_dma = 0;
4006 ha->init_cb = NULL;
4007 ha->init_cb_dma = 0;
4008 ha->ex_init_cb = NULL;
4009 ha->ex_init_cb_dma = 0;
4010 ha->async_pd = NULL;
4011 ha->async_pd_dma = 0;
4012
4013 ha->s_dma_pool = NULL;
4014 ha->dl_dma_pool = NULL;
4015 ha->fcp_cmnd_dma_pool = NULL;
4016
4017 ha->gid_list = NULL;
4018 ha->gid_list_dma = 0;
4019
4020 ha->tgt.atio_ring = NULL;
4021 ha->tgt.atio_dma = 0;
4022 ha->tgt.tgt_vp_map = NULL;
4023 }
4024
4025 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4026 struct qla_hw_data *ha)
4027 {
4028 struct Scsi_Host *host;
4029 struct scsi_qla_host *vha = NULL;
4030
4031 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4032 if (host == NULL) {
4033 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4034 "Failed to allocate host from the scsi layer, aborting.\n");
4035 goto fail;
4036 }
4037
4038 /* Clear our data area */
4039 vha = shost_priv(host);
4040 memset(vha, 0, sizeof(scsi_qla_host_t));
4041
4042 vha->host = host;
4043 vha->host_no = host->host_no;
4044 vha->hw = ha;
4045
4046 INIT_LIST_HEAD(&vha->vp_fcports);
4047 INIT_LIST_HEAD(&vha->work_list);
4048 INIT_LIST_HEAD(&vha->list);
4049 INIT_LIST_HEAD(&vha->qla_cmd_list);
4050 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4051 INIT_LIST_HEAD(&vha->logo_list);
4052 INIT_LIST_HEAD(&vha->plogi_ack_list);
4053
4054 spin_lock_init(&vha->work_lock);
4055 spin_lock_init(&vha->cmd_list_lock);
4056 init_waitqueue_head(&vha->vref_waitq);
4057
4058 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
4059 ql_dbg(ql_dbg_init, vha, 0x0041,
4060 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4061 vha->host, vha->hw, vha,
4062 dev_name(&(ha->pdev->dev)));
4063
4064 return vha;
4065
4066 fail:
4067 return vha;
4068 }
4069
4070 static struct qla_work_evt *
4071 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4072 {
4073 struct qla_work_evt *e;
4074 uint8_t bail;
4075
4076 QLA_VHA_MARK_BUSY(vha, bail);
4077 if (bail)
4078 return NULL;
4079
4080 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4081 if (!e) {
4082 QLA_VHA_MARK_NOT_BUSY(vha);
4083 return NULL;
4084 }
4085
4086 INIT_LIST_HEAD(&e->list);
4087 e->type = type;
4088 e->flags = QLA_EVT_FLAG_FREE;
4089 return e;
4090 }
4091
4092 static int
4093 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4094 {
4095 unsigned long flags;
4096
4097 spin_lock_irqsave(&vha->work_lock, flags);
4098 list_add_tail(&e->list, &vha->work_list);
4099 spin_unlock_irqrestore(&vha->work_lock, flags);
4100 qla2xxx_wake_dpc(vha);
4101
4102 return QLA_SUCCESS;
4103 }
4104
4105 int
4106 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4107 u32 data)
4108 {
4109 struct qla_work_evt *e;
4110
4111 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4112 if (!e)
4113 return QLA_FUNCTION_FAILED;
4114
4115 e->u.aen.code = code;
4116 e->u.aen.data = data;
4117 return qla2x00_post_work(vha, e);
4118 }
4119
4120 int
4121 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4122 {
4123 struct qla_work_evt *e;
4124
4125 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4126 if (!e)
4127 return QLA_FUNCTION_FAILED;
4128
4129 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4130 return qla2x00_post_work(vha, e);
4131 }
4132
4133 #define qla2x00_post_async_work(name, type) \
4134 int qla2x00_post_async_##name##_work( \
4135 struct scsi_qla_host *vha, \
4136 fc_port_t *fcport, uint16_t *data) \
4137 { \
4138 struct qla_work_evt *e; \
4139 \
4140 e = qla2x00_alloc_work(vha, type); \
4141 if (!e) \
4142 return QLA_FUNCTION_FAILED; \
4143 \
4144 e->u.logio.fcport = fcport; \
4145 if (data) { \
4146 e->u.logio.data[0] = data[0]; \
4147 e->u.logio.data[1] = data[1]; \
4148 } \
4149 return qla2x00_post_work(vha, e); \
4150 }
4151
4152 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4153 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4154 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4155 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
4156 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4157 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
4158
4159 int
4160 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4161 {
4162 struct qla_work_evt *e;
4163
4164 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4165 if (!e)
4166 return QLA_FUNCTION_FAILED;
4167
4168 e->u.uevent.code = code;
4169 return qla2x00_post_work(vha, e);
4170 }
4171
4172 static void
4173 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4174 {
4175 char event_string[40];
4176 char *envp[] = { event_string, NULL };
4177
4178 switch (code) {
4179 case QLA_UEVENT_CODE_FW_DUMP:
4180 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4181 vha->host_no);
4182 break;
4183 default:
4184 /* do nothing */
4185 break;
4186 }
4187 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4188 }
4189
4190 int
4191 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4192 uint32_t *data, int cnt)
4193 {
4194 struct qla_work_evt *e;
4195
4196 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4197 if (!e)
4198 return QLA_FUNCTION_FAILED;
4199
4200 e->u.aenfx.evtcode = evtcode;
4201 e->u.aenfx.count = cnt;
4202 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4203 return qla2x00_post_work(vha, e);
4204 }
4205
4206 void
4207 qla2x00_do_work(struct scsi_qla_host *vha)
4208 {
4209 struct qla_work_evt *e, *tmp;
4210 unsigned long flags;
4211 LIST_HEAD(work);
4212
4213 spin_lock_irqsave(&vha->work_lock, flags);
4214 list_splice_init(&vha->work_list, &work);
4215 spin_unlock_irqrestore(&vha->work_lock, flags);
4216
4217 list_for_each_entry_safe(e, tmp, &work, list) {
4218 list_del_init(&e->list);
4219
4220 switch (e->type) {
4221 case QLA_EVT_AEN:
4222 fc_host_post_event(vha->host, fc_get_event_number(),
4223 e->u.aen.code, e->u.aen.data);
4224 break;
4225 case QLA_EVT_IDC_ACK:
4226 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4227 break;
4228 case QLA_EVT_ASYNC_LOGIN:
4229 qla2x00_async_login(vha, e->u.logio.fcport,
4230 e->u.logio.data);
4231 break;
4232 case QLA_EVT_ASYNC_LOGIN_DONE:
4233 qla2x00_async_login_done(vha, e->u.logio.fcport,
4234 e->u.logio.data);
4235 break;
4236 case QLA_EVT_ASYNC_LOGOUT:
4237 qla2x00_async_logout(vha, e->u.logio.fcport);
4238 break;
4239 case QLA_EVT_ASYNC_LOGOUT_DONE:
4240 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4241 e->u.logio.data);
4242 break;
4243 case QLA_EVT_ASYNC_ADISC:
4244 qla2x00_async_adisc(vha, e->u.logio.fcport,
4245 e->u.logio.data);
4246 break;
4247 case QLA_EVT_ASYNC_ADISC_DONE:
4248 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4249 e->u.logio.data);
4250 break;
4251 case QLA_EVT_UEVENT:
4252 qla2x00_uevent_emit(vha, e->u.uevent.code);
4253 break;
4254 case QLA_EVT_AENFX:
4255 qlafx00_process_aen(vha, e);
4256 break;
4257 }
4258 if (e->flags & QLA_EVT_FLAG_FREE)
4259 kfree(e);
4260
4261 /* For each work completed decrement vha ref count */
4262 QLA_VHA_MARK_NOT_BUSY(vha);
4263 }
4264 }
4265
4266 /* Relogins all the fcports of a vport
4267 * Context: dpc thread
4268 */
4269 void qla2x00_relogin(struct scsi_qla_host *vha)
4270 {
4271 fc_port_t *fcport;
4272 int status;
4273 uint16_t next_loopid = 0;
4274 struct qla_hw_data *ha = vha->hw;
4275 uint16_t data[2];
4276
4277 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4278 /*
4279 * If the port is not ONLINE then try to login
4280 * to it if we haven't run out of retries.
4281 */
4282 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4283 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4284 fcport->login_retry--;
4285 if (fcport->flags & FCF_FABRIC_DEVICE) {
4286 if (fcport->flags & FCF_FCP2_DEVICE)
4287 ha->isp_ops->fabric_logout(vha,
4288 fcport->loop_id,
4289 fcport->d_id.b.domain,
4290 fcport->d_id.b.area,
4291 fcport->d_id.b.al_pa);
4292
4293 if (fcport->loop_id == FC_NO_LOOP_ID) {
4294 fcport->loop_id = next_loopid =
4295 ha->min_external_loopid;
4296 status = qla2x00_find_new_loop_id(
4297 vha, fcport);
4298 if (status != QLA_SUCCESS) {
4299 /* Ran out of IDs to use */
4300 break;
4301 }
4302 }
4303
4304 if (IS_ALOGIO_CAPABLE(ha)) {
4305 fcport->flags |= FCF_ASYNC_SENT;
4306 data[0] = 0;
4307 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4308 status = qla2x00_post_async_login_work(
4309 vha, fcport, data);
4310 if (status == QLA_SUCCESS)
4311 continue;
4312 /* Attempt a retry. */
4313 status = 1;
4314 } else {
4315 status = qla2x00_fabric_login(vha,
4316 fcport, &next_loopid);
4317 if (status == QLA_SUCCESS) {
4318 int status2;
4319 uint8_t opts;
4320
4321 opts = 0;
4322 if (fcport->flags &
4323 FCF_FCP2_DEVICE)
4324 opts |= BIT_1;
4325 status2 =
4326 qla2x00_get_port_database(
4327 vha, fcport, opts);
4328 if (status2 != QLA_SUCCESS)
4329 status = 1;
4330 }
4331 }
4332 } else
4333 status = qla2x00_local_device_login(vha,
4334 fcport);
4335
4336 if (status == QLA_SUCCESS) {
4337 fcport->old_loop_id = fcport->loop_id;
4338
4339 ql_dbg(ql_dbg_disc, vha, 0x2003,
4340 "Port login OK: logged in ID 0x%x.\n",
4341 fcport->loop_id);
4342
4343 qla2x00_update_fcport(vha, fcport);
4344
4345 } else if (status == 1) {
4346 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4347 /* retry the login again */
4348 ql_dbg(ql_dbg_disc, vha, 0x2007,
4349 "Retrying %d login again loop_id 0x%x.\n",
4350 fcport->login_retry, fcport->loop_id);
4351 } else {
4352 fcport->login_retry = 0;
4353 }
4354
4355 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4356 qla2x00_clear_loop_id(fcport);
4357 }
4358 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4359 break;
4360 }
4361 }
4362
4363 /* Schedule work on any of the dpc-workqueues */
4364 void
4365 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4366 {
4367 struct qla_hw_data *ha = base_vha->hw;
4368
4369 switch (work_code) {
4370 case MBA_IDC_AEN: /* 0x8200 */
4371 if (ha->dpc_lp_wq)
4372 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4373 break;
4374
4375 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4376 if (!ha->flags.nic_core_reset_hdlr_active) {
4377 if (ha->dpc_hp_wq)
4378 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4379 } else
4380 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4381 "NIC Core reset is already active. Skip "
4382 "scheduling it again.\n");
4383 break;
4384 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4385 if (ha->dpc_hp_wq)
4386 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4387 break;
4388 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4389 if (ha->dpc_hp_wq)
4390 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4391 break;
4392 default:
4393 ql_log(ql_log_warn, base_vha, 0xb05f,
4394 "Unknown work-code=0x%x.\n", work_code);
4395 }
4396
4397 return;
4398 }
4399
4400 /* Work: Perform NIC Core Unrecoverable state handling */
4401 void
4402 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4403 {
4404 struct qla_hw_data *ha =
4405 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4406 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4407 uint32_t dev_state = 0;
4408
4409 qla83xx_idc_lock(base_vha, 0);
4410 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4411 qla83xx_reset_ownership(base_vha);
4412 if (ha->flags.nic_core_reset_owner) {
4413 ha->flags.nic_core_reset_owner = 0;
4414 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4415 QLA8XXX_DEV_FAILED);
4416 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4417 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4418 }
4419 qla83xx_idc_unlock(base_vha, 0);
4420 }
4421
4422 /* Work: Execute IDC state handler */
4423 void
4424 qla83xx_idc_state_handler_work(struct work_struct *work)
4425 {
4426 struct qla_hw_data *ha =
4427 container_of(work, struct qla_hw_data, idc_state_handler);
4428 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4429 uint32_t dev_state = 0;
4430
4431 qla83xx_idc_lock(base_vha, 0);
4432 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4433 if (dev_state == QLA8XXX_DEV_FAILED ||
4434 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4435 qla83xx_idc_state_handler(base_vha);
4436 qla83xx_idc_unlock(base_vha, 0);
4437 }
4438
4439 static int
4440 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4441 {
4442 int rval = QLA_SUCCESS;
4443 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4444 uint32_t heart_beat_counter1, heart_beat_counter2;
4445
4446 do {
4447 if (time_after(jiffies, heart_beat_wait)) {
4448 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4449 "Nic Core f/w is not alive.\n");
4450 rval = QLA_FUNCTION_FAILED;
4451 break;
4452 }
4453
4454 qla83xx_idc_lock(base_vha, 0);
4455 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4456 &heart_beat_counter1);
4457 qla83xx_idc_unlock(base_vha, 0);
4458 msleep(100);
4459 qla83xx_idc_lock(base_vha, 0);
4460 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4461 &heart_beat_counter2);
4462 qla83xx_idc_unlock(base_vha, 0);
4463 } while (heart_beat_counter1 == heart_beat_counter2);
4464
4465 return rval;
4466 }
4467
4468 /* Work: Perform NIC Core Reset handling */
4469 void
4470 qla83xx_nic_core_reset_work(struct work_struct *work)
4471 {
4472 struct qla_hw_data *ha =
4473 container_of(work, struct qla_hw_data, nic_core_reset);
4474 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4475 uint32_t dev_state = 0;
4476
4477 if (IS_QLA2031(ha)) {
4478 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4479 ql_log(ql_log_warn, base_vha, 0xb081,
4480 "Failed to dump mctp\n");
4481 return;
4482 }
4483
4484 if (!ha->flags.nic_core_reset_hdlr_active) {
4485 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4486 qla83xx_idc_lock(base_vha, 0);
4487 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4488 &dev_state);
4489 qla83xx_idc_unlock(base_vha, 0);
4490 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4491 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4492 "Nic Core f/w is alive.\n");
4493 return;
4494 }
4495 }
4496
4497 ha->flags.nic_core_reset_hdlr_active = 1;
4498 if (qla83xx_nic_core_reset(base_vha)) {
4499 /* NIC Core reset failed. */
4500 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4501 "NIC Core reset failed.\n");
4502 }
4503 ha->flags.nic_core_reset_hdlr_active = 0;
4504 }
4505 }
4506
4507 /* Work: Handle 8200 IDC aens */
4508 void
4509 qla83xx_service_idc_aen(struct work_struct *work)
4510 {
4511 struct qla_hw_data *ha =
4512 container_of(work, struct qla_hw_data, idc_aen);
4513 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4514 uint32_t dev_state, idc_control;
4515
4516 qla83xx_idc_lock(base_vha, 0);
4517 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4518 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4519 qla83xx_idc_unlock(base_vha, 0);
4520 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4521 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4522 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4523 "Application requested NIC Core Reset.\n");
4524 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4525 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4526 QLA_SUCCESS) {
4527 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4528 "Other protocol driver requested NIC Core Reset.\n");
4529 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4530 }
4531 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4532 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4533 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4534 }
4535 }
4536
4537 static void
4538 qla83xx_wait_logic(void)
4539 {
4540 int i;
4541
4542 /* Yield CPU */
4543 if (!in_interrupt()) {
4544 /*
4545 * Wait about 200ms before retrying again.
4546 * This controls the number of retries for single
4547 * lock operation.
4548 */
4549 msleep(100);
4550 schedule();
4551 } else {
4552 for (i = 0; i < 20; i++)
4553 cpu_relax(); /* This a nop instr on i386 */
4554 }
4555 }
4556
4557 static int
4558 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4559 {
4560 int rval;
4561 uint32_t data;
4562 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4563 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4564 struct qla_hw_data *ha = base_vha->hw;
4565 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4566 "Trying force recovery of the IDC lock.\n");
4567
4568 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4569 if (rval)
4570 return rval;
4571
4572 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4573 return QLA_SUCCESS;
4574 } else {
4575 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4576 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4577 data);
4578 if (rval)
4579 return rval;
4580
4581 msleep(200);
4582
4583 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4584 &data);
4585 if (rval)
4586 return rval;
4587
4588 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4589 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4590 ~(idc_lck_rcvry_stage_mask));
4591 rval = qla83xx_wr_reg(base_vha,
4592 QLA83XX_IDC_LOCK_RECOVERY, data);
4593 if (rval)
4594 return rval;
4595
4596 /* Forcefully perform IDC UnLock */
4597 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4598 &data);
4599 if (rval)
4600 return rval;
4601 /* Clear lock-id by setting 0xff */
4602 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4603 0xff);
4604 if (rval)
4605 return rval;
4606 /* Clear lock-recovery by setting 0x0 */
4607 rval = qla83xx_wr_reg(base_vha,
4608 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4609 if (rval)
4610 return rval;
4611 } else
4612 return QLA_SUCCESS;
4613 }
4614
4615 return rval;
4616 }
4617
4618 static int
4619 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4620 {
4621 int rval = QLA_SUCCESS;
4622 uint32_t o_drv_lockid, n_drv_lockid;
4623 unsigned long lock_recovery_timeout;
4624
4625 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4626 retry_lockid:
4627 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4628 if (rval)
4629 goto exit;
4630
4631 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4632 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4633 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4634 return QLA_SUCCESS;
4635 else
4636 return QLA_FUNCTION_FAILED;
4637 }
4638
4639 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4640 if (rval)
4641 goto exit;
4642
4643 if (o_drv_lockid == n_drv_lockid) {
4644 qla83xx_wait_logic();
4645 goto retry_lockid;
4646 } else
4647 return QLA_SUCCESS;
4648
4649 exit:
4650 return rval;
4651 }
4652
4653 void
4654 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4655 {
4656 uint16_t options = (requester_id << 15) | BIT_6;
4657 uint32_t data;
4658 uint32_t lock_owner;
4659 struct qla_hw_data *ha = base_vha->hw;
4660
4661 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4662 retry_lock:
4663 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4664 == QLA_SUCCESS) {
4665 if (data) {
4666 /* Setting lock-id to our function-number */
4667 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4668 ha->portnum);
4669 } else {
4670 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4671 &lock_owner);
4672 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4673 "Failed to acquire IDC lock, acquired by %d, "
4674 "retrying...\n", lock_owner);
4675
4676 /* Retry/Perform IDC-Lock recovery */
4677 if (qla83xx_idc_lock_recovery(base_vha)
4678 == QLA_SUCCESS) {
4679 qla83xx_wait_logic();
4680 goto retry_lock;
4681 } else
4682 ql_log(ql_log_warn, base_vha, 0xb075,
4683 "IDC Lock recovery FAILED.\n");
4684 }
4685
4686 }
4687
4688 return;
4689
4690 /* XXX: IDC-lock implementation using access-control mbx */
4691 retry_lock2:
4692 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4693 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4694 "Failed to acquire IDC lock. retrying...\n");
4695 /* Retry/Perform IDC-Lock recovery */
4696 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4697 qla83xx_wait_logic();
4698 goto retry_lock2;
4699 } else
4700 ql_log(ql_log_warn, base_vha, 0xb076,
4701 "IDC Lock recovery FAILED.\n");
4702 }
4703
4704 return;
4705 }
4706
4707 void
4708 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4709 {
4710 #if 0
4711 uint16_t options = (requester_id << 15) | BIT_7;
4712 #endif
4713 uint16_t retry;
4714 uint32_t data;
4715 struct qla_hw_data *ha = base_vha->hw;
4716
4717 /* IDC-unlock implementation using driver-unlock/lock-id
4718 * remote registers
4719 */
4720 retry = 0;
4721 retry_unlock:
4722 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4723 == QLA_SUCCESS) {
4724 if (data == ha->portnum) {
4725 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4726 /* Clearing lock-id by setting 0xff */
4727 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4728 } else if (retry < 10) {
4729 /* SV: XXX: IDC unlock retrying needed here? */
4730
4731 /* Retry for IDC-unlock */
4732 qla83xx_wait_logic();
4733 retry++;
4734 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4735 "Failed to release IDC lock, retrying=%d\n", retry);
4736 goto retry_unlock;
4737 }
4738 } else if (retry < 10) {
4739 /* Retry for IDC-unlock */
4740 qla83xx_wait_logic();
4741 retry++;
4742 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4743 "Failed to read drv-lockid, retrying=%d\n", retry);
4744 goto retry_unlock;
4745 }
4746
4747 return;
4748
4749 #if 0
4750 /* XXX: IDC-unlock implementation using access-control mbx */
4751 retry = 0;
4752 retry_unlock2:
4753 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4754 if (retry < 10) {
4755 /* Retry for IDC-unlock */
4756 qla83xx_wait_logic();
4757 retry++;
4758 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4759 "Failed to release IDC lock, retrying=%d\n", retry);
4760 goto retry_unlock2;
4761 }
4762 }
4763
4764 return;
4765 #endif
4766 }
4767
4768 int
4769 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4770 {
4771 int rval = QLA_SUCCESS;
4772 struct qla_hw_data *ha = vha->hw;
4773 uint32_t drv_presence;
4774
4775 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4776 if (rval == QLA_SUCCESS) {
4777 drv_presence |= (1 << ha->portnum);
4778 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4779 drv_presence);
4780 }
4781
4782 return rval;
4783 }
4784
4785 int
4786 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4787 {
4788 int rval = QLA_SUCCESS;
4789
4790 qla83xx_idc_lock(vha, 0);
4791 rval = __qla83xx_set_drv_presence(vha);
4792 qla83xx_idc_unlock(vha, 0);
4793
4794 return rval;
4795 }
4796
4797 int
4798 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4799 {
4800 int rval = QLA_SUCCESS;
4801 struct qla_hw_data *ha = vha->hw;
4802 uint32_t drv_presence;
4803
4804 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4805 if (rval == QLA_SUCCESS) {
4806 drv_presence &= ~(1 << ha->portnum);
4807 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4808 drv_presence);
4809 }
4810
4811 return rval;
4812 }
4813
4814 int
4815 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4816 {
4817 int rval = QLA_SUCCESS;
4818
4819 qla83xx_idc_lock(vha, 0);
4820 rval = __qla83xx_clear_drv_presence(vha);
4821 qla83xx_idc_unlock(vha, 0);
4822
4823 return rval;
4824 }
4825
4826 static void
4827 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4828 {
4829 struct qla_hw_data *ha = vha->hw;
4830 uint32_t drv_ack, drv_presence;
4831 unsigned long ack_timeout;
4832
4833 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4834 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4835 while (1) {
4836 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4837 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4838 if ((drv_ack & drv_presence) == drv_presence)
4839 break;
4840
4841 if (time_after_eq(jiffies, ack_timeout)) {
4842 ql_log(ql_log_warn, vha, 0xb067,
4843 "RESET ACK TIMEOUT! drv_presence=0x%x "
4844 "drv_ack=0x%x\n", drv_presence, drv_ack);
4845 /*
4846 * The function(s) which did not ack in time are forced
4847 * to withdraw any further participation in the IDC
4848 * reset.
4849 */
4850 if (drv_ack != drv_presence)
4851 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4852 drv_ack);
4853 break;
4854 }
4855
4856 qla83xx_idc_unlock(vha, 0);
4857 msleep(1000);
4858 qla83xx_idc_lock(vha, 0);
4859 }
4860
4861 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4862 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4863 }
4864
4865 static int
4866 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4867 {
4868 int rval = QLA_SUCCESS;
4869 uint32_t idc_control;
4870
4871 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4872 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4873
4874 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4875 __qla83xx_get_idc_control(vha, &idc_control);
4876 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4877 __qla83xx_set_idc_control(vha, 0);
4878
4879 qla83xx_idc_unlock(vha, 0);
4880 rval = qla83xx_restart_nic_firmware(vha);
4881 qla83xx_idc_lock(vha, 0);
4882
4883 if (rval != QLA_SUCCESS) {
4884 ql_log(ql_log_fatal, vha, 0xb06a,
4885 "Failed to restart NIC f/w.\n");
4886 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4887 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4888 } else {
4889 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4890 "Success in restarting nic f/w.\n");
4891 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4892 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4893 }
4894
4895 return rval;
4896 }
4897
4898 /* Assumes idc_lock always held on entry */
4899 int
4900 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4901 {
4902 struct qla_hw_data *ha = base_vha->hw;
4903 int rval = QLA_SUCCESS;
4904 unsigned long dev_init_timeout;
4905 uint32_t dev_state;
4906
4907 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4908 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4909
4910 while (1) {
4911
4912 if (time_after_eq(jiffies, dev_init_timeout)) {
4913 ql_log(ql_log_warn, base_vha, 0xb06e,
4914 "Initialization TIMEOUT!\n");
4915 /* Init timeout. Disable further NIC Core
4916 * communication.
4917 */
4918 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4919 QLA8XXX_DEV_FAILED);
4920 ql_log(ql_log_info, base_vha, 0xb06f,
4921 "HW State: FAILED.\n");
4922 }
4923
4924 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4925 switch (dev_state) {
4926 case QLA8XXX_DEV_READY:
4927 if (ha->flags.nic_core_reset_owner)
4928 qla83xx_idc_audit(base_vha,
4929 IDC_AUDIT_COMPLETION);
4930 ha->flags.nic_core_reset_owner = 0;
4931 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4932 "Reset_owner reset by 0x%x.\n",
4933 ha->portnum);
4934 goto exit;
4935 case QLA8XXX_DEV_COLD:
4936 if (ha->flags.nic_core_reset_owner)
4937 rval = qla83xx_device_bootstrap(base_vha);
4938 else {
4939 /* Wait for AEN to change device-state */
4940 qla83xx_idc_unlock(base_vha, 0);
4941 msleep(1000);
4942 qla83xx_idc_lock(base_vha, 0);
4943 }
4944 break;
4945 case QLA8XXX_DEV_INITIALIZING:
4946 /* Wait for AEN to change device-state */
4947 qla83xx_idc_unlock(base_vha, 0);
4948 msleep(1000);
4949 qla83xx_idc_lock(base_vha, 0);
4950 break;
4951 case QLA8XXX_DEV_NEED_RESET:
4952 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4953 qla83xx_need_reset_handler(base_vha);
4954 else {
4955 /* Wait for AEN to change device-state */
4956 qla83xx_idc_unlock(base_vha, 0);
4957 msleep(1000);
4958 qla83xx_idc_lock(base_vha, 0);
4959 }
4960 /* reset timeout value after need reset handler */
4961 dev_init_timeout = jiffies +
4962 (ha->fcoe_dev_init_timeout * HZ);
4963 break;
4964 case QLA8XXX_DEV_NEED_QUIESCENT:
4965 /* XXX: DEBUG for now */
4966 qla83xx_idc_unlock(base_vha, 0);
4967 msleep(1000);
4968 qla83xx_idc_lock(base_vha, 0);
4969 break;
4970 case QLA8XXX_DEV_QUIESCENT:
4971 /* XXX: DEBUG for now */
4972 if (ha->flags.quiesce_owner)
4973 goto exit;
4974
4975 qla83xx_idc_unlock(base_vha, 0);
4976 msleep(1000);
4977 qla83xx_idc_lock(base_vha, 0);
4978 dev_init_timeout = jiffies +
4979 (ha->fcoe_dev_init_timeout * HZ);
4980 break;
4981 case QLA8XXX_DEV_FAILED:
4982 if (ha->flags.nic_core_reset_owner)
4983 qla83xx_idc_audit(base_vha,
4984 IDC_AUDIT_COMPLETION);
4985 ha->flags.nic_core_reset_owner = 0;
4986 __qla83xx_clear_drv_presence(base_vha);
4987 qla83xx_idc_unlock(base_vha, 0);
4988 qla8xxx_dev_failed_handler(base_vha);
4989 rval = QLA_FUNCTION_FAILED;
4990 qla83xx_idc_lock(base_vha, 0);
4991 goto exit;
4992 case QLA8XXX_BAD_VALUE:
4993 qla83xx_idc_unlock(base_vha, 0);
4994 msleep(1000);
4995 qla83xx_idc_lock(base_vha, 0);
4996 break;
4997 default:
4998 ql_log(ql_log_warn, base_vha, 0xb071,
4999 "Unknown Device State: %x.\n", dev_state);
5000 qla83xx_idc_unlock(base_vha, 0);
5001 qla8xxx_dev_failed_handler(base_vha);
5002 rval = QLA_FUNCTION_FAILED;
5003 qla83xx_idc_lock(base_vha, 0);
5004 goto exit;
5005 }
5006 }
5007
5008 exit:
5009 return rval;
5010 }
5011
5012 void
5013 qla2x00_disable_board_on_pci_error(struct work_struct *work)
5014 {
5015 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5016 board_disable);
5017 struct pci_dev *pdev = ha->pdev;
5018 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5019
5020 /* if UNLOAD flag is already set, then continue unload,
5021 * where it was set first.
5022 */
5023 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5024 return;
5025
5026 ql_log(ql_log_warn, base_vha, 0x015b,
5027 "Disabling adapter.\n");
5028
5029 set_bit(UNLOADING, &base_vha->dpc_flags);
5030
5031 qla2x00_delete_all_vps(ha, base_vha);
5032
5033 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5034
5035 qla2x00_dfs_remove(base_vha);
5036
5037 qla84xx_put_chip(base_vha);
5038
5039 if (base_vha->timer_active)
5040 qla2x00_stop_timer(base_vha);
5041
5042 base_vha->flags.online = 0;
5043
5044 qla2x00_destroy_deferred_work(ha);
5045
5046 /*
5047 * Do not try to stop beacon blink as it will issue a mailbox
5048 * command.
5049 */
5050 qla2x00_free_sysfs_attr(base_vha, false);
5051
5052 fc_remove_host(base_vha->host);
5053
5054 scsi_remove_host(base_vha->host);
5055
5056 base_vha->flags.init_done = 0;
5057 qla25xx_delete_queues(base_vha);
5058 qla2x00_free_irqs(base_vha);
5059 qla2x00_free_fcports(base_vha);
5060 qla2x00_mem_free(ha);
5061 qla82xx_md_free(base_vha);
5062 qla2x00_free_queues(ha);
5063
5064 qla2x00_unmap_iobases(ha);
5065
5066 pci_release_selected_regions(ha->pdev, ha->bars);
5067 pci_disable_pcie_error_reporting(pdev);
5068 pci_disable_device(pdev);
5069
5070 /*
5071 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5072 */
5073 }
5074
5075 /**************************************************************************
5076 * qla2x00_do_dpc
5077 * This kernel thread is a task that is schedule by the interrupt handler
5078 * to perform the background processing for interrupts.
5079 *
5080 * Notes:
5081 * This task always run in the context of a kernel thread. It
5082 * is kick-off by the driver's detect code and starts up
5083 * up one per adapter. It immediately goes to sleep and waits for
5084 * some fibre event. When either the interrupt handler or
5085 * the timer routine detects a event it will one of the task
5086 * bits then wake us up.
5087 **************************************************************************/
5088 static int
5089 qla2x00_do_dpc(void *data)
5090 {
5091 scsi_qla_host_t *base_vha;
5092 struct qla_hw_data *ha;
5093
5094 ha = (struct qla_hw_data *)data;
5095 base_vha = pci_get_drvdata(ha->pdev);
5096
5097 set_user_nice(current, MIN_NICE);
5098
5099 set_current_state(TASK_INTERRUPTIBLE);
5100 while (!kthread_should_stop()) {
5101 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5102 "DPC handler sleeping.\n");
5103
5104 schedule();
5105
5106 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5107 goto end_loop;
5108
5109 if (ha->flags.eeh_busy) {
5110 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5111 "eeh_busy=%d.\n", ha->flags.eeh_busy);
5112 goto end_loop;
5113 }
5114
5115 ha->dpc_active = 1;
5116
5117 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5118 "DPC handler waking up, dpc_flags=0x%lx.\n",
5119 base_vha->dpc_flags);
5120
5121 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5122 break;
5123
5124 qla2x00_do_work(base_vha);
5125
5126 if (IS_P3P_TYPE(ha)) {
5127 if (IS_QLA8044(ha)) {
5128 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5129 &base_vha->dpc_flags)) {
5130 qla8044_idc_lock(ha);
5131 qla8044_wr_direct(base_vha,
5132 QLA8044_CRB_DEV_STATE_INDEX,
5133 QLA8XXX_DEV_FAILED);
5134 qla8044_idc_unlock(ha);
5135 ql_log(ql_log_info, base_vha, 0x4004,
5136 "HW State: FAILED.\n");
5137 qla8044_device_state_handler(base_vha);
5138 continue;
5139 }
5140
5141 } else {
5142 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5143 &base_vha->dpc_flags)) {
5144 qla82xx_idc_lock(ha);
5145 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5146 QLA8XXX_DEV_FAILED);
5147 qla82xx_idc_unlock(ha);
5148 ql_log(ql_log_info, base_vha, 0x0151,
5149 "HW State: FAILED.\n");
5150 qla82xx_device_state_handler(base_vha);
5151 continue;
5152 }
5153 }
5154
5155 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5156 &base_vha->dpc_flags)) {
5157
5158 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5159 "FCoE context reset scheduled.\n");
5160 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5161 &base_vha->dpc_flags))) {
5162 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5163 /* FCoE-ctx reset failed.
5164 * Escalate to chip-reset
5165 */
5166 set_bit(ISP_ABORT_NEEDED,
5167 &base_vha->dpc_flags);
5168 }
5169 clear_bit(ABORT_ISP_ACTIVE,
5170 &base_vha->dpc_flags);
5171 }
5172
5173 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5174 "FCoE context reset end.\n");
5175 }
5176 } else if (IS_QLAFX00(ha)) {
5177 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5178 &base_vha->dpc_flags)) {
5179 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5180 "Firmware Reset Recovery\n");
5181 if (qlafx00_reset_initialize(base_vha)) {
5182 /* Failed. Abort isp later. */
5183 if (!test_bit(UNLOADING,
5184 &base_vha->dpc_flags)) {
5185 set_bit(ISP_UNRECOVERABLE,
5186 &base_vha->dpc_flags);
5187 ql_dbg(ql_dbg_dpc, base_vha,
5188 0x4021,
5189 "Reset Recovery Failed\n");
5190 }
5191 }
5192 }
5193
5194 if (test_and_clear_bit(FX00_TARGET_SCAN,
5195 &base_vha->dpc_flags)) {
5196 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5197 "ISPFx00 Target Scan scheduled\n");
5198 if (qlafx00_rescan_isp(base_vha)) {
5199 if (!test_bit(UNLOADING,
5200 &base_vha->dpc_flags))
5201 set_bit(ISP_UNRECOVERABLE,
5202 &base_vha->dpc_flags);
5203 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5204 "ISPFx00 Target Scan Failed\n");
5205 }
5206 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5207 "ISPFx00 Target Scan End\n");
5208 }
5209 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5210 &base_vha->dpc_flags)) {
5211 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5212 "ISPFx00 Host Info resend scheduled\n");
5213 qlafx00_fx_disc(base_vha,
5214 &base_vha->hw->mr.fcport,
5215 FXDISC_REG_HOST_INFO);
5216 }
5217 }
5218
5219 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5220 &base_vha->dpc_flags)) {
5221
5222 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5223 "ISP abort scheduled.\n");
5224 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5225 &base_vha->dpc_flags))) {
5226
5227 if (ha->isp_ops->abort_isp(base_vha)) {
5228 /* failed. retry later */
5229 set_bit(ISP_ABORT_NEEDED,
5230 &base_vha->dpc_flags);
5231 }
5232 clear_bit(ABORT_ISP_ACTIVE,
5233 &base_vha->dpc_flags);
5234 }
5235
5236 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5237 "ISP abort end.\n");
5238 }
5239
5240 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5241 &base_vha->dpc_flags)) {
5242 qla2x00_update_fcports(base_vha);
5243 }
5244
5245 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5246 int ret;
5247 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5248 if (ret != QLA_SUCCESS)
5249 ql_log(ql_log_warn, base_vha, 0x121,
5250 "Failed to enable receiving of RSCN "
5251 "requests: 0x%x.\n", ret);
5252 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5253 }
5254
5255 if (IS_QLAFX00(ha))
5256 goto loop_resync_check;
5257
5258 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5259 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5260 "Quiescence mode scheduled.\n");
5261 if (IS_P3P_TYPE(ha)) {
5262 if (IS_QLA82XX(ha))
5263 qla82xx_device_state_handler(base_vha);
5264 if (IS_QLA8044(ha))
5265 qla8044_device_state_handler(base_vha);
5266 clear_bit(ISP_QUIESCE_NEEDED,
5267 &base_vha->dpc_flags);
5268 if (!ha->flags.quiesce_owner) {
5269 qla2x00_perform_loop_resync(base_vha);
5270 if (IS_QLA82XX(ha)) {
5271 qla82xx_idc_lock(ha);
5272 qla82xx_clear_qsnt_ready(
5273 base_vha);
5274 qla82xx_idc_unlock(ha);
5275 } else if (IS_QLA8044(ha)) {
5276 qla8044_idc_lock(ha);
5277 qla8044_clear_qsnt_ready(
5278 base_vha);
5279 qla8044_idc_unlock(ha);
5280 }
5281 }
5282 } else {
5283 clear_bit(ISP_QUIESCE_NEEDED,
5284 &base_vha->dpc_flags);
5285 qla2x00_quiesce_io(base_vha);
5286 }
5287 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5288 "Quiescence mode end.\n");
5289 }
5290
5291 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5292 &base_vha->dpc_flags) &&
5293 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5294
5295 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5296 "Reset marker scheduled.\n");
5297 qla2x00_rst_aen(base_vha);
5298 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5299 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5300 "Reset marker end.\n");
5301 }
5302
5303 /* Retry each device up to login retry count */
5304 if ((test_and_clear_bit(RELOGIN_NEEDED,
5305 &base_vha->dpc_flags)) &&
5306 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5307 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5308
5309 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5310 "Relogin scheduled.\n");
5311 qla2x00_relogin(base_vha);
5312 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5313 "Relogin end.\n");
5314 }
5315 loop_resync_check:
5316 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5317 &base_vha->dpc_flags)) {
5318
5319 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5320 "Loop resync scheduled.\n");
5321
5322 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5323 &base_vha->dpc_flags))) {
5324
5325 qla2x00_loop_resync(base_vha);
5326
5327 clear_bit(LOOP_RESYNC_ACTIVE,
5328 &base_vha->dpc_flags);
5329 }
5330
5331 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5332 "Loop resync end.\n");
5333 }
5334
5335 if (IS_QLAFX00(ha))
5336 goto intr_on_check;
5337
5338 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5339 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5340 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5341 qla2xxx_flash_npiv_conf(base_vha);
5342 }
5343
5344 intr_on_check:
5345 if (!ha->interrupts_on)
5346 ha->isp_ops->enable_intrs(ha);
5347
5348 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5349 &base_vha->dpc_flags)) {
5350 if (ha->beacon_blink_led == 1)
5351 ha->isp_ops->beacon_blink(base_vha);
5352 }
5353
5354 if (!IS_QLAFX00(ha))
5355 qla2x00_do_dpc_all_vps(base_vha);
5356
5357 ha->dpc_active = 0;
5358 end_loop:
5359 set_current_state(TASK_INTERRUPTIBLE);
5360 } /* End of while(1) */
5361 __set_current_state(TASK_RUNNING);
5362
5363 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5364 "DPC handler exiting.\n");
5365
5366 /*
5367 * Make sure that nobody tries to wake us up again.
5368 */
5369 ha->dpc_active = 0;
5370
5371 /* Cleanup any residual CTX SRBs. */
5372 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5373
5374 return 0;
5375 }
5376
5377 void
5378 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5379 {
5380 struct qla_hw_data *ha = vha->hw;
5381 struct task_struct *t = ha->dpc_thread;
5382
5383 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5384 wake_up_process(t);
5385 }
5386
5387 /*
5388 * qla2x00_rst_aen
5389 * Processes asynchronous reset.
5390 *
5391 * Input:
5392 * ha = adapter block pointer.
5393 */
5394 static void
5395 qla2x00_rst_aen(scsi_qla_host_t *vha)
5396 {
5397 if (vha->flags.online && !vha->flags.reset_active &&
5398 !atomic_read(&vha->loop_down_timer) &&
5399 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5400 do {
5401 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5402
5403 /*
5404 * Issue marker command only when we are going to start
5405 * the I/O.
5406 */
5407 vha->marker_needed = 1;
5408 } while (!atomic_read(&vha->loop_down_timer) &&
5409 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5410 }
5411 }
5412
5413 /**************************************************************************
5414 * qla2x00_timer
5415 *
5416 * Description:
5417 * One second timer
5418 *
5419 * Context: Interrupt
5420 ***************************************************************************/
5421 void
5422 qla2x00_timer(unsigned long _vha)
5423 {
5424 scsi_qla_host_t *vha = (scsi_qla_host_t *)_vha;
5425 unsigned long cpu_flags = 0;
5426 int start_dpc = 0;
5427 int index;
5428 srb_t *sp;
5429 uint16_t w;
5430 struct qla_hw_data *ha = vha->hw;
5431 struct req_que *req;
5432
5433 if (ha->flags.eeh_busy) {
5434 ql_dbg(ql_dbg_timer, vha, 0x6000,
5435 "EEH = %d, restarting timer.\n",
5436 ha->flags.eeh_busy);
5437 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5438 return;
5439 }
5440
5441 /*
5442 * Hardware read to raise pending EEH errors during mailbox waits. If
5443 * the read returns -1 then disable the board.
5444 */
5445 if (!pci_channel_offline(ha->pdev)) {
5446 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5447 qla2x00_check_reg16_for_disconnect(vha, w);
5448 }
5449
5450 /* Make sure qla82xx_watchdog is run only for physical port */
5451 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5452 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5453 start_dpc++;
5454 if (IS_QLA82XX(ha))
5455 qla82xx_watchdog(vha);
5456 else if (IS_QLA8044(ha))
5457 qla8044_watchdog(vha);
5458 }
5459
5460 if (!vha->vp_idx && IS_QLAFX00(ha))
5461 qlafx00_timer_routine(vha);
5462
5463 /* Loop down handler. */
5464 if (atomic_read(&vha->loop_down_timer) > 0 &&
5465 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5466 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5467 && vha->flags.online) {
5468
5469 if (atomic_read(&vha->loop_down_timer) ==
5470 vha->loop_down_abort_time) {
5471
5472 ql_log(ql_log_info, vha, 0x6008,
5473 "Loop down - aborting the queues before time expires.\n");
5474
5475 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5476 atomic_set(&vha->loop_state, LOOP_DEAD);
5477
5478 /*
5479 * Schedule an ISP abort to return any FCP2-device
5480 * commands.
5481 */
5482 /* NPIV - scan physical port only */
5483 if (!vha->vp_idx) {
5484 spin_lock_irqsave(&ha->hardware_lock,
5485 cpu_flags);
5486 req = ha->req_q_map[0];
5487 for (index = 1;
5488 index < req->num_outstanding_cmds;
5489 index++) {
5490 fc_port_t *sfcp;
5491
5492 sp = req->outstanding_cmds[index];
5493 if (!sp)
5494 continue;
5495 if (sp->type != SRB_SCSI_CMD)
5496 continue;
5497 sfcp = sp->fcport;
5498 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5499 continue;
5500
5501 if (IS_QLA82XX(ha))
5502 set_bit(FCOE_CTX_RESET_NEEDED,
5503 &vha->dpc_flags);
5504 else
5505 set_bit(ISP_ABORT_NEEDED,
5506 &vha->dpc_flags);
5507 break;
5508 }
5509 spin_unlock_irqrestore(&ha->hardware_lock,
5510 cpu_flags);
5511 }
5512 start_dpc++;
5513 }
5514
5515 /* if the loop has been down for 4 minutes, reinit adapter */
5516 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5517 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5518 ql_log(ql_log_warn, vha, 0x6009,
5519 "Loop down - aborting ISP.\n");
5520
5521 if (IS_QLA82XX(ha))
5522 set_bit(FCOE_CTX_RESET_NEEDED,
5523 &vha->dpc_flags);
5524 else
5525 set_bit(ISP_ABORT_NEEDED,
5526 &vha->dpc_flags);
5527 }
5528 }
5529 ql_dbg(ql_dbg_timer, vha, 0x600a,
5530 "Loop down - seconds remaining %d.\n",
5531 atomic_read(&vha->loop_down_timer));
5532 }
5533 /* Check if beacon LED needs to be blinked for physical host only */
5534 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5535 /* There is no beacon_blink function for ISP82xx */
5536 if (!IS_P3P_TYPE(ha)) {
5537 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5538 start_dpc++;
5539 }
5540 }
5541
5542 /* Process any deferred work. */
5543 if (!list_empty(&vha->work_list))
5544 start_dpc++;
5545
5546 /* Schedule the DPC routine if needed */
5547 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5548 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5549 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5550 start_dpc ||
5551 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5552 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5553 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5554 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5555 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5556 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5557 ql_dbg(ql_dbg_timer, vha, 0x600b,
5558 "isp_abort_needed=%d loop_resync_needed=%d "
5559 "fcport_update_needed=%d start_dpc=%d "
5560 "reset_marker_needed=%d",
5561 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5562 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5563 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5564 start_dpc,
5565 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5566 ql_dbg(ql_dbg_timer, vha, 0x600c,
5567 "beacon_blink_needed=%d isp_unrecoverable=%d "
5568 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5569 "relogin_needed=%d.\n",
5570 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5571 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5572 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5573 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5574 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5575 qla2xxx_wake_dpc(vha);
5576 }
5577
5578 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5579 }
5580
5581 /* Firmware interface routines. */
5582
5583 #define FW_BLOBS 11
5584 #define FW_ISP21XX 0
5585 #define FW_ISP22XX 1
5586 #define FW_ISP2300 2
5587 #define FW_ISP2322 3
5588 #define FW_ISP24XX 4
5589 #define FW_ISP25XX 5
5590 #define FW_ISP81XX 6
5591 #define FW_ISP82XX 7
5592 #define FW_ISP2031 8
5593 #define FW_ISP8031 9
5594 #define FW_ISP27XX 10
5595
5596 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5597 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5598 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5599 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5600 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5601 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5602 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5603 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5604 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5605 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5606 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5607
5608
5609 static DEFINE_MUTEX(qla_fw_lock);
5610
5611 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5612 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5613 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5614 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5615 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5616 { .name = FW_FILE_ISP24XX, },
5617 { .name = FW_FILE_ISP25XX, },
5618 { .name = FW_FILE_ISP81XX, },
5619 { .name = FW_FILE_ISP82XX, },
5620 { .name = FW_FILE_ISP2031, },
5621 { .name = FW_FILE_ISP8031, },
5622 { .name = FW_FILE_ISP27XX, },
5623 };
5624
5625 struct fw_blob *
5626 qla2x00_request_firmware(scsi_qla_host_t *vha)
5627 {
5628 struct qla_hw_data *ha = vha->hw;
5629 struct fw_blob *blob;
5630
5631 if (IS_QLA2100(ha)) {
5632 blob = &qla_fw_blobs[FW_ISP21XX];
5633 } else if (IS_QLA2200(ha)) {
5634 blob = &qla_fw_blobs[FW_ISP22XX];
5635 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5636 blob = &qla_fw_blobs[FW_ISP2300];
5637 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5638 blob = &qla_fw_blobs[FW_ISP2322];
5639 } else if (IS_QLA24XX_TYPE(ha)) {
5640 blob = &qla_fw_blobs[FW_ISP24XX];
5641 } else if (IS_QLA25XX(ha)) {
5642 blob = &qla_fw_blobs[FW_ISP25XX];
5643 } else if (IS_QLA81XX(ha)) {
5644 blob = &qla_fw_blobs[FW_ISP81XX];
5645 } else if (IS_QLA82XX(ha)) {
5646 blob = &qla_fw_blobs[FW_ISP82XX];
5647 } else if (IS_QLA2031(ha)) {
5648 blob = &qla_fw_blobs[FW_ISP2031];
5649 } else if (IS_QLA8031(ha)) {
5650 blob = &qla_fw_blobs[FW_ISP8031];
5651 } else if (IS_QLA27XX(ha)) {
5652 blob = &qla_fw_blobs[FW_ISP27XX];
5653 } else {
5654 return NULL;
5655 }
5656
5657 mutex_lock(&qla_fw_lock);
5658 if (blob->fw)
5659 goto out;
5660
5661 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5662 ql_log(ql_log_warn, vha, 0x0063,
5663 "Failed to load firmware image (%s).\n", blob->name);
5664 blob->fw = NULL;
5665 blob = NULL;
5666 goto out;
5667 }
5668
5669 out:
5670 mutex_unlock(&qla_fw_lock);
5671 return blob;
5672 }
5673
5674 static void
5675 qla2x00_release_firmware(void)
5676 {
5677 int idx;
5678
5679 mutex_lock(&qla_fw_lock);
5680 for (idx = 0; idx < FW_BLOBS; idx++)
5681 release_firmware(qla_fw_blobs[idx].fw);
5682 mutex_unlock(&qla_fw_lock);
5683 }
5684
5685 static pci_ers_result_t
5686 qla2xxx_pci_error_detected(struct pci_dev *pdev, enum pci_channel_state state)
5687 {
5688 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5689 struct qla_hw_data *ha = vha->hw;
5690
5691 ql_dbg(ql_dbg_aer, vha, 0x9000,
5692 "PCI error detected, state %x.\n", state);
5693
5694 switch (state) {
5695 case pci_channel_io_normal:
5696 ha->flags.eeh_busy = 0;
5697 return PCI_ERS_RESULT_CAN_RECOVER;
5698 case pci_channel_io_frozen:
5699 ha->flags.eeh_busy = 1;
5700 /* For ISP82XX complete any pending mailbox cmd */
5701 if (IS_QLA82XX(ha)) {
5702 ha->flags.isp82xx_fw_hung = 1;
5703 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5704 qla82xx_clear_pending_mbx(vha);
5705 }
5706 qla2x00_free_irqs(vha);
5707 pci_disable_device(pdev);
5708 /* Return back all IOs */
5709 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5710 return PCI_ERS_RESULT_NEED_RESET;
5711 case pci_channel_io_perm_failure:
5712 ha->flags.pci_channel_io_perm_failure = 1;
5713 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5714 return PCI_ERS_RESULT_DISCONNECT;
5715 }
5716 return PCI_ERS_RESULT_NEED_RESET;
5717 }
5718
5719 static pci_ers_result_t
5720 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5721 {
5722 int risc_paused = 0;
5723 uint32_t stat;
5724 unsigned long flags;
5725 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5726 struct qla_hw_data *ha = base_vha->hw;
5727 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5728 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5729
5730 if (IS_QLA82XX(ha))
5731 return PCI_ERS_RESULT_RECOVERED;
5732
5733 spin_lock_irqsave(&ha->hardware_lock, flags);
5734 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5735 stat = RD_REG_DWORD(&reg->hccr);
5736 if (stat & HCCR_RISC_PAUSE)
5737 risc_paused = 1;
5738 } else if (IS_QLA23XX(ha)) {
5739 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5740 if (stat & HSR_RISC_PAUSED)
5741 risc_paused = 1;
5742 } else if (IS_FWI2_CAPABLE(ha)) {
5743 stat = RD_REG_DWORD(&reg24->host_status);
5744 if (stat & HSRX_RISC_PAUSED)
5745 risc_paused = 1;
5746 }
5747 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5748
5749 if (risc_paused) {
5750 ql_log(ql_log_info, base_vha, 0x9003,
5751 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5752 ha->isp_ops->fw_dump(base_vha, 0);
5753
5754 return PCI_ERS_RESULT_NEED_RESET;
5755 } else
5756 return PCI_ERS_RESULT_RECOVERED;
5757 }
5758
5759 static uint32_t
5760 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5761 {
5762 uint32_t rval = QLA_FUNCTION_FAILED;
5763 uint32_t drv_active = 0;
5764 struct qla_hw_data *ha = base_vha->hw;
5765 int fn;
5766 struct pci_dev *other_pdev = NULL;
5767
5768 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5769 "Entered %s.\n", __func__);
5770
5771 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5772
5773 if (base_vha->flags.online) {
5774 /* Abort all outstanding commands,
5775 * so as to be requeued later */
5776 qla2x00_abort_isp_cleanup(base_vha);
5777 }
5778
5779
5780 fn = PCI_FUNC(ha->pdev->devfn);
5781 while (fn > 0) {
5782 fn--;
5783 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5784 "Finding pci device at function = 0x%x.\n", fn);
5785 other_pdev =
5786 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5787 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5788 fn));
5789
5790 if (!other_pdev)
5791 continue;
5792 if (atomic_read(&other_pdev->enable_cnt)) {
5793 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5794 "Found PCI func available and enable at 0x%x.\n",
5795 fn);
5796 pci_dev_put(other_pdev);
5797 break;
5798 }
5799 pci_dev_put(other_pdev);
5800 }
5801
5802 if (!fn) {
5803 /* Reset owner */
5804 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5805 "This devfn is reset owner = 0x%x.\n",
5806 ha->pdev->devfn);
5807 qla82xx_idc_lock(ha);
5808
5809 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5810 QLA8XXX_DEV_INITIALIZING);
5811
5812 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5813 QLA82XX_IDC_VERSION);
5814
5815 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5816 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5817 "drv_active = 0x%x.\n", drv_active);
5818
5819 qla82xx_idc_unlock(ha);
5820 /* Reset if device is not already reset
5821 * drv_active would be 0 if a reset has already been done
5822 */
5823 if (drv_active)
5824 rval = qla82xx_start_firmware(base_vha);
5825 else
5826 rval = QLA_SUCCESS;
5827 qla82xx_idc_lock(ha);
5828
5829 if (rval != QLA_SUCCESS) {
5830 ql_log(ql_log_info, base_vha, 0x900b,
5831 "HW State: FAILED.\n");
5832 qla82xx_clear_drv_active(ha);
5833 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5834 QLA8XXX_DEV_FAILED);
5835 } else {
5836 ql_log(ql_log_info, base_vha, 0x900c,
5837 "HW State: READY.\n");
5838 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5839 QLA8XXX_DEV_READY);
5840 qla82xx_idc_unlock(ha);
5841 ha->flags.isp82xx_fw_hung = 0;
5842 rval = qla82xx_restart_isp(base_vha);
5843 qla82xx_idc_lock(ha);
5844 /* Clear driver state register */
5845 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5846 qla82xx_set_drv_active(base_vha);
5847 }
5848 qla82xx_idc_unlock(ha);
5849 } else {
5850 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5851 "This devfn is not reset owner = 0x%x.\n",
5852 ha->pdev->devfn);
5853 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5854 QLA8XXX_DEV_READY)) {
5855 ha->flags.isp82xx_fw_hung = 0;
5856 rval = qla82xx_restart_isp(base_vha);
5857 qla82xx_idc_lock(ha);
5858 qla82xx_set_drv_active(base_vha);
5859 qla82xx_idc_unlock(ha);
5860 }
5861 }
5862 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5863
5864 return rval;
5865 }
5866
5867 static pci_ers_result_t
5868 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5869 {
5870 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5871 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5872 struct qla_hw_data *ha = base_vha->hw;
5873 struct rsp_que *rsp;
5874 int rc, retries = 10;
5875
5876 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5877 "Slot Reset.\n");
5878
5879 /* Workaround: qla2xxx driver which access hardware earlier
5880 * needs error state to be pci_channel_io_online.
5881 * Otherwise mailbox command timesout.
5882 */
5883 pdev->error_state = pci_channel_io_normal;
5884
5885 pci_restore_state(pdev);
5886
5887 /* pci_restore_state() clears the saved_state flag of the device
5888 * save restored state which resets saved_state flag
5889 */
5890 pci_save_state(pdev);
5891
5892 if (ha->mem_only)
5893 rc = pci_enable_device_mem(pdev);
5894 else
5895 rc = pci_enable_device(pdev);
5896
5897 if (rc) {
5898 ql_log(ql_log_warn, base_vha, 0x9005,
5899 "Can't re-enable PCI device after reset.\n");
5900 goto exit_slot_reset;
5901 }
5902
5903 rsp = ha->rsp_q_map[0];
5904 if (qla2x00_request_irqs(ha, rsp))
5905 goto exit_slot_reset;
5906
5907 if (ha->isp_ops->pci_config(base_vha))
5908 goto exit_slot_reset;
5909
5910 if (IS_QLA82XX(ha)) {
5911 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5912 ret = PCI_ERS_RESULT_RECOVERED;
5913 goto exit_slot_reset;
5914 } else
5915 goto exit_slot_reset;
5916 }
5917
5918 while (ha->flags.mbox_busy && retries--)
5919 msleep(1000);
5920
5921 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5922 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5923 ret = PCI_ERS_RESULT_RECOVERED;
5924 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5925
5926
5927 exit_slot_reset:
5928 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5929 "slot_reset return %x.\n", ret);
5930
5931 return ret;
5932 }
5933
5934 static void
5935 qla2xxx_pci_resume(struct pci_dev *pdev)
5936 {
5937 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5938 struct qla_hw_data *ha = base_vha->hw;
5939 int ret;
5940
5941 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5942 "pci_resume.\n");
5943
5944 ret = qla2x00_wait_for_hba_online(base_vha);
5945 if (ret != QLA_SUCCESS) {
5946 ql_log(ql_log_fatal, base_vha, 0x9002,
5947 "The device failed to resume I/O from slot/link_reset.\n");
5948 }
5949
5950 pci_cleanup_aer_uncorrect_error_status(pdev);
5951
5952 ha->flags.eeh_busy = 0;
5953 }
5954
5955 static void
5956 qla83xx_disable_laser(scsi_qla_host_t *vha)
5957 {
5958 uint32_t reg, data, fn;
5959 struct qla_hw_data *ha = vha->hw;
5960 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5961
5962 /* pci func #/port # */
5963 ql_dbg(ql_dbg_init, vha, 0x004b,
5964 "Disabling Laser for hba: %p\n", vha);
5965
5966 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5967 (BIT_15|BIT_14|BIT_13|BIT_12));
5968
5969 fn = (fn >> 12);
5970
5971 if (fn & 1)
5972 reg = PORT_1_2031;
5973 else
5974 reg = PORT_0_2031;
5975
5976 data = LASER_OFF_2031;
5977
5978 qla83xx_wr_reg(vha, reg, data);
5979 }
5980
5981 static const struct pci_error_handlers qla2xxx_err_handler = {
5982 .error_detected = qla2xxx_pci_error_detected,
5983 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5984 .slot_reset = qla2xxx_pci_slot_reset,
5985 .resume = qla2xxx_pci_resume,
5986 };
5987
5988 static struct pci_device_id qla2xxx_pci_tbl[] = {
5989 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5990 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5991 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5992 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5993 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5994 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5995 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5996 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5997 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5998 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5999 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6000 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
6001 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6002 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
6003 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
6004 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
6005 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
6006 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
6007 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
6008 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
6009 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
6010 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
6011 { 0 },
6012 };
6013 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6014
6015 static struct pci_driver qla2xxx_pci_driver = {
6016 .name = QLA2XXX_DRIVER_NAME,
6017 .driver = {
6018 .owner = THIS_MODULE,
6019 },
6020 .id_table = qla2xxx_pci_tbl,
6021 .probe = qla2x00_probe_one,
6022 .remove = qla2x00_remove_one,
6023 .shutdown = qla2x00_shutdown,
6024 .err_handler = &qla2xxx_err_handler,
6025 };
6026
6027 static const struct file_operations apidev_fops = {
6028 .owner = THIS_MODULE,
6029 .llseek = noop_llseek,
6030 };
6031
6032 /**
6033 * qla2x00_module_init - Module initialization.
6034 **/
6035 static int __init
6036 qla2x00_module_init(void)
6037 {
6038 int ret = 0;
6039
6040 /* Allocate cache for SRBs. */
6041 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
6042 SLAB_HWCACHE_ALIGN, NULL);
6043 if (srb_cachep == NULL) {
6044 ql_log(ql_log_fatal, NULL, 0x0001,
6045 "Unable to allocate SRB cache...Failing load!.\n");
6046 return -ENOMEM;
6047 }
6048
6049 /* Initialize target kmem_cache and mem_pools */
6050 ret = qlt_init();
6051 if (ret < 0) {
6052 kmem_cache_destroy(srb_cachep);
6053 return ret;
6054 } else if (ret > 0) {
6055 /*
6056 * If initiator mode is explictly disabled by qlt_init(),
6057 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6058 * performing scsi_scan_target() during LOOP UP event.
6059 */
6060 qla2xxx_transport_functions.disable_target_scan = 1;
6061 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6062 }
6063
6064 /* Derive version string. */
6065 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
6066 if (ql2xextended_error_logging)
6067 strcat(qla2x00_version_str, "-debug");
6068
6069 qla2xxx_transport_template =
6070 fc_attach_transport(&qla2xxx_transport_functions);
6071 if (!qla2xxx_transport_template) {
6072 kmem_cache_destroy(srb_cachep);
6073 ql_log(ql_log_fatal, NULL, 0x0002,
6074 "fc_attach_transport failed...Failing load!.\n");
6075 qlt_exit();
6076 return -ENODEV;
6077 }
6078
6079 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6080 if (apidev_major < 0) {
6081 ql_log(ql_log_fatal, NULL, 0x0003,
6082 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6083 }
6084
6085 qla2xxx_transport_vport_template =
6086 fc_attach_transport(&qla2xxx_transport_vport_functions);
6087 if (!qla2xxx_transport_vport_template) {
6088 kmem_cache_destroy(srb_cachep);
6089 qlt_exit();
6090 fc_release_transport(qla2xxx_transport_template);
6091 ql_log(ql_log_fatal, NULL, 0x0004,
6092 "fc_attach_transport vport failed...Failing load!.\n");
6093 return -ENODEV;
6094 }
6095 ql_log(ql_log_info, NULL, 0x0005,
6096 "QLogic Fibre Channel HBA Driver: %s.\n",
6097 qla2x00_version_str);
6098 ret = pci_register_driver(&qla2xxx_pci_driver);
6099 if (ret) {
6100 kmem_cache_destroy(srb_cachep);
6101 qlt_exit();
6102 fc_release_transport(qla2xxx_transport_template);
6103 fc_release_transport(qla2xxx_transport_vport_template);
6104 ql_log(ql_log_fatal, NULL, 0x0006,
6105 "pci_register_driver failed...ret=%d Failing load!.\n",
6106 ret);
6107 }
6108 return ret;
6109 }
6110
6111 /**
6112 * qla2x00_module_exit - Module cleanup.
6113 **/
6114 static void __exit
6115 qla2x00_module_exit(void)
6116 {
6117 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
6118 pci_unregister_driver(&qla2xxx_pci_driver);
6119 qla2x00_release_firmware();
6120 kmem_cache_destroy(srb_cachep);
6121 qlt_exit();
6122 if (ctx_cachep)
6123 kmem_cache_destroy(ctx_cachep);
6124 fc_release_transport(qla2xxx_transport_template);
6125 fc_release_transport(qla2xxx_transport_vport_template);
6126 }
6127
6128 module_init(qla2x00_module_init);
6129 module_exit(qla2x00_module_exit);
6130
6131 MODULE_AUTHOR("QLogic Corporation");
6132 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6133 MODULE_LICENSE("GPL");
6134 MODULE_VERSION(QLA2XXX_VERSION);
6135 MODULE_FIRMWARE(FW_FILE_ISP21XX);
6136 MODULE_FIRMWARE(FW_FILE_ISP22XX);
6137 MODULE_FIRMWARE(FW_FILE_ISP2300);
6138 MODULE_FIRMWARE(FW_FILE_ISP2322);
6139 MODULE_FIRMWARE(FW_FILE_ISP24XX);
6140 MODULE_FIRMWARE(FW_FILE_ISP25XX);
Arne's tree of linux kernel.