2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/addrspace.h>
14 #include <asm/types.h>
15 #include <dm/pinctrl.h>
16 #include <mach/ar71xx_regs.h>
18 #define AR933X_UART_DATA_REG 0x00
19 #define AR933X_UART_CS_REG 0x04
20 #define AR933X_UART_CLK_REG 0x08
22 #define AR933X_UART_DATA_TX_RX_MASK 0xff
23 #define AR933X_UART_DATA_RX_CSR BIT(8)
24 #define AR933X_UART_DATA_TX_CSR BIT(9)
25 #define AR933X_UART_CS_IF_MODE_S 2
26 #define AR933X_UART_CS_IF_MODE_M 0x3
27 #define AR933X_UART_CS_IF_MODE_DTE 1
28 #define AR933X_UART_CS_IF_MODE_DCE 2
29 #define AR933X_UART_CS_TX_RDY_ORIDE BIT(7)
30 #define AR933X_UART_CS_RX_RDY_ORIDE BIT(8)
31 #define AR933X_UART_CLK_STEP_M 0xffff
32 #define AR933X_UART_CLK_SCALE_M 0xfff
33 #define AR933X_UART_CLK_SCALE_S 16
34 #define AR933X_UART_CLK_STEP_S 0
36 struct ar933x_serial_priv
{
41 * Baudrate algorithm come from Linux/drivers/tty/serial/ar933x_uart.c
42 * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
44 static u32
ar933x_serial_get_baud(u32 clk
, u32 scale
, u32 step
)
49 div
= (2 << 16) * (scale
+ 1);
58 static void ar933x_serial_get_scale_step(u32 clk
, u32 baud
,
59 u32
*scale
, u32
*step
)
68 for (tscale
= 0; tscale
< AR933X_UART_CLK_SCALE_M
; tscale
++) {
72 tstep
= baud
* (tscale
+ 1);
76 if (tstep
> AR933X_UART_CLK_STEP_M
)
79 baudrate
= ar933x_serial_get_baud(clk
, tscale
, tstep
);
80 diff
= abs(baudrate
- baud
);
81 if (diff
< min_diff
) {
89 static int ar933x_serial_setbrg(struct udevice
*dev
, int baudrate
)
91 struct ar933x_serial_priv
*priv
= dev_get_priv(dev
);
94 val
= get_serial_clock();
95 ar933x_serial_get_scale_step(val
, baudrate
, &scale
, &step
);
97 val
= (scale
& AR933X_UART_CLK_SCALE_M
)
98 << AR933X_UART_CLK_SCALE_S
;
99 val
|= (step
& AR933X_UART_CLK_STEP_M
)
100 << AR933X_UART_CLK_STEP_S
;
101 writel(val
, priv
->regs
+ AR933X_UART_CLK_REG
);
106 static int ar933x_serial_putc(struct udevice
*dev
, const char c
)
108 struct ar933x_serial_priv
*priv
= dev_get_priv(dev
);
111 data
= readl(priv
->regs
+ AR933X_UART_DATA_REG
);
112 if (!(data
& AR933X_UART_DATA_TX_CSR
))
115 data
= (u32
)c
| AR933X_UART_DATA_TX_CSR
;
116 writel(data
, priv
->regs
+ AR933X_UART_DATA_REG
);
121 static int ar933x_serial_getc(struct udevice
*dev
)
123 struct ar933x_serial_priv
*priv
= dev_get_priv(dev
);
126 data
= readl(priv
->regs
+ AR933X_UART_DATA_REG
);
127 if (!(data
& AR933X_UART_DATA_RX_CSR
))
130 writel(AR933X_UART_DATA_RX_CSR
, priv
->regs
+ AR933X_UART_DATA_REG
);
131 return data
& AR933X_UART_DATA_TX_RX_MASK
;
134 static int ar933x_serial_pending(struct udevice
*dev
, bool input
)
136 struct ar933x_serial_priv
*priv
= dev_get_priv(dev
);
139 data
= readl(priv
->regs
+ AR933X_UART_DATA_REG
);
141 return (data
& AR933X_UART_DATA_RX_CSR
) ? 1 : 0;
143 return (data
& AR933X_UART_DATA_TX_CSR
) ? 0 : 1;
146 static int ar933x_serial_probe(struct udevice
*dev
)
148 struct ar933x_serial_priv
*priv
= dev_get_priv(dev
);
152 addr
= dev_get_addr(dev
);
153 if (addr
== FDT_ADDR_T_NONE
)
156 priv
->regs
= map_physmem(addr
, AR933X_UART_SIZE
,
160 * UART controller configuration:
165 * - set RX ready oride
166 * - set TX ready oride
168 val
= (AR933X_UART_CS_IF_MODE_DCE
<< AR933X_UART_CS_IF_MODE_S
) |
169 AR933X_UART_CS_TX_RDY_ORIDE
| AR933X_UART_CS_RX_RDY_ORIDE
;
170 writel(val
, priv
->regs
+ AR933X_UART_CS_REG
);
174 static const struct dm_serial_ops ar933x_serial_ops
= {
175 .putc
= ar933x_serial_putc
,
176 .pending
= ar933x_serial_pending
,
177 .getc
= ar933x_serial_getc
,
178 .setbrg
= ar933x_serial_setbrg
,
181 static const struct udevice_id ar933x_serial_ids
[] = {
182 { .compatible
= "qca,ar9330-uart" },
186 U_BOOT_DRIVER(serial_ar933x
) = {
187 .name
= "serial_ar933x",
189 .of_match
= ar933x_serial_ids
,
190 .priv_auto_alloc_size
= sizeof(struct ar933x_serial_priv
),
191 .probe
= ar933x_serial_probe
,
192 .ops
= &ar933x_serial_ops
,
193 .flags
= DM_FLAG_PRE_RELOC
,
196 #ifdef CONFIG_DEBUG_UART_AR933X
198 #include <debug_uart.h>
200 static inline void _debug_uart_init(void)
202 void __iomem
*regs
= (void *)CONFIG_DEBUG_UART_BASE
;
203 u32 val
, scale
, step
;
206 * UART controller configuration:
211 * - set RX ready oride
212 * - set TX ready oride
214 val
= (AR933X_UART_CS_IF_MODE_DCE
<< AR933X_UART_CS_IF_MODE_S
) |
215 AR933X_UART_CS_TX_RDY_ORIDE
| AR933X_UART_CS_RX_RDY_ORIDE
;
216 writel(val
, regs
+ AR933X_UART_CS_REG
);
218 ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK
,
219 CONFIG_BAUDRATE
, &scale
, &step
);
221 val
= (scale
& AR933X_UART_CLK_SCALE_M
)
222 << AR933X_UART_CLK_SCALE_S
;
223 val
|= (step
& AR933X_UART_CLK_STEP_M
)
224 << AR933X_UART_CLK_STEP_S
;
225 writel(val
, regs
+ AR933X_UART_CLK_REG
);
228 static inline void _debug_uart_putc(int c
)
230 void __iomem
*regs
= (void *)CONFIG_DEBUG_UART_BASE
;
234 data
= readl(regs
+ AR933X_UART_DATA_REG
);
235 } while (!(data
& AR933X_UART_DATA_TX_CSR
));
237 data
= (u32
)c
| AR933X_UART_DATA_TX_CSR
;
238 writel(data
, regs
+ AR933X_UART_DATA_REG
);