4 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 * UART will work in Data Mover mode.
7 * Based on Linux driver.
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <linux/compiler.h>
21 /* Serial registers - this driver works in uartdm mode*/
23 #define UARTDM_DMRX 0x34 /* Max RX transfer length */
24 #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
26 #define UARTDM_RXFS 0x50 /* RX channel status register */
27 #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
28 #define UARTDM_RXFS_BUF_MASK 0x7
30 #define UARTDM_SR 0xA4 /* Status register */
31 #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
32 #define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
33 #define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
35 #define UARTDM_CR 0xA8 /* Command register */
36 #define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
37 #define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
38 #define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
39 #define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
40 #define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
42 #define UARTDM_IMR 0xB0 /* Interrupt mask register */
43 #define UARTDM_ISR 0xB4 /* Interrupt status register */
44 #define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
46 #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
47 #define UARTDM_RF 0x140 /* UART Receive FIFO register */
50 DECLARE_GLOBAL_DATA_PTR
;
52 struct msm_serial_data
{
54 unsigned chars_cnt
; /* number of buffered chars */
55 uint32_t chars_buf
; /* buffered chars */
58 static int msm_serial_fetch(struct udevice
*dev
)
60 struct msm_serial_data
*priv
= dev_get_priv(dev
);
64 return priv
->chars_cnt
;
66 /* Clear error in case of buffer overrun */
67 if (readl(priv
->base
+ UARTDM_SR
) & UARTDM_SR_UART_OVERRUN
)
68 writel(UARTDM_CR_CMD_RESET_ERR
, priv
->base
+ UARTDM_CR
);
70 /* We need to fetch new character */
71 sr
= readl(priv
->base
+ UARTDM_SR
);
73 if (sr
& UARTDM_SR_RX_READY
) {
74 /* There are at least 4 bytes in fifo */
75 priv
->chars_buf
= readl(priv
->base
+ UARTDM_RF
);
78 /* Check if there is anything in fifo */
79 priv
->chars_cnt
= readl(priv
->base
+ UARTDM_RXFS
);
80 /* Extract number of characters in UART packing buffer*/
81 priv
->chars_cnt
= (priv
->chars_cnt
>>
82 UARTDM_RXFS_BUF_SHIFT
) &
87 /* There is at least one charcter, move it to fifo */
88 writel(UARTDM_CR_CMD_FORCE_STALE
,
89 priv
->base
+ UARTDM_CR
);
91 priv
->chars_buf
= readl(priv
->base
+ UARTDM_RF
);
92 writel(UARTDM_CR_CMD_RESET_STALE_INT
,
93 priv
->base
+ UARTDM_CR
);
94 writel(0x7, priv
->base
+ UARTDM_DMRX
);
97 return priv
->chars_cnt
;
100 static int msm_serial_getc(struct udevice
*dev
)
102 struct msm_serial_data
*priv
= dev_get_priv(dev
);
105 if (!msm_serial_fetch(dev
))
108 c
= priv
->chars_buf
& 0xFF;
109 priv
->chars_buf
>>= 8;
115 static int msm_serial_putc(struct udevice
*dev
, const char ch
)
117 struct msm_serial_data
*priv
= dev_get_priv(dev
);
119 if (!(readl(priv
->base
+ UARTDM_SR
) & UARTDM_SR_TX_EMPTY
) &&
120 !(readl(priv
->base
+ UARTDM_ISR
) & UARTDM_ISR_TX_READY
))
123 writel(UARTDM_CR_CMD_RESET_TX_READY
, priv
->base
+ UARTDM_CR
);
125 writel(1, priv
->base
+ UARTDM_NCF_TX
);
126 writel(ch
, priv
->base
+ UARTDM_TF
);
131 static int msm_serial_pending(struct udevice
*dev
, bool input
)
134 if (msm_serial_fetch(dev
))
141 static const struct dm_serial_ops msm_serial_ops
= {
142 .putc
= msm_serial_putc
,
143 .pending
= msm_serial_pending
,
144 .getc
= msm_serial_getc
,
147 static int msm_uart_clk_init(struct udevice
*dev
)
149 uint clk_rate
= fdtdec_get_uint(gd
->fdt_blob
, dev_of_offset(dev
),
150 "clock-frequency", 115200);
151 uint clkd
[2]; /* clk_id and clk_no */
153 struct udevice
*clk_dev
;
157 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(dev
), "clock",
162 clk_offset
= fdt_node_offset_by_phandle(gd
->fdt_blob
, clkd
[0]);
166 ret
= uclass_get_device_by_of_offset(UCLASS_CLK
, clk_offset
, &clk_dev
);
171 ret
= clk_request(clk_dev
, &clk
);
175 ret
= clk_set_rate(&clk
, clk_rate
);
183 static int msm_serial_probe(struct udevice
*dev
)
185 struct msm_serial_data
*priv
= dev_get_priv(dev
);
187 msm_uart_clk_init(dev
); /* Ignore return value and hope clock was
188 properly initialized by earlier loaders */
190 if (readl(priv
->base
+ UARTDM_SR
) & UARTDM_SR_UART_OVERRUN
)
191 writel(UARTDM_CR_CMD_RESET_ERR
, priv
->base
+ UARTDM_CR
);
193 writel(0, priv
->base
+ UARTDM_IMR
);
194 writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE
, priv
->base
+ UARTDM_CR
);
195 msm_serial_fetch(dev
);
200 static int msm_serial_ofdata_to_platdata(struct udevice
*dev
)
202 struct msm_serial_data
*priv
= dev_get_priv(dev
);
204 priv
->base
= devfdt_get_addr(dev
);
205 if (priv
->base
== FDT_ADDR_T_NONE
)
211 static const struct udevice_id msm_serial_ids
[] = {
212 { .compatible
= "qcom,msm-uartdm-v1.4" },
216 U_BOOT_DRIVER(serial_msm
) = {
217 .name
= "serial_msm",
219 .of_match
= msm_serial_ids
,
220 .ofdata_to_platdata
= msm_serial_ofdata_to_platdata
,
221 .priv_auto_alloc_size
= sizeof(struct msm_serial_data
),
222 .probe
= msm_serial_probe
,
223 .ops
= &msm_serial_ops
,