3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
24 DECLARE_GLOBAL_DATA_PTR
;
26 #ifndef CONFIG_DM_SERIAL
28 static volatile unsigned char *const port
[] = CONFIG_PL01x_PORTS
;
29 static enum pl01x_type pl01x_type
__attribute__ ((section(".data")));
30 static struct pl01x_regs
*base_regs
__attribute__ ((section(".data")));
31 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
35 static int pl01x_putc(struct pl01x_regs
*regs
, char c
)
37 /* Wait until there is space in the FIFO */
38 if (readl(®s
->fr
) & UART_PL01x_FR_TXFF
)
41 /* Send the character */
47 static int pl01x_getc(struct pl01x_regs
*regs
)
51 /* Wait until there is data in the FIFO */
52 if (readl(®s
->fr
) & UART_PL01x_FR_RXFE
)
55 data
= readl(®s
->dr
);
57 /* Check for an error flag */
58 if (data
& 0xFFFFFF00) {
60 writel(0xFFFFFFFF, ®s
->ecr
);
67 static int pl01x_tstc(struct pl01x_regs
*regs
)
70 return !(readl(®s
->fr
) & UART_PL01x_FR_RXFE
);
73 static int pl01x_generic_serial_init(struct pl01x_regs
*regs
,
78 /* disable everything */
79 writel(0, ®s
->pl010_cr
);
82 /* disable everything */
83 writel(0, ®s
->pl011_cr
);
92 static int pl011_set_line_control(struct pl01x_regs
*regs
)
96 * Internal update of baud rate register require line
97 * control register write
99 lcr
= UART_PL011_LCRH_WLEN_8
| UART_PL011_LCRH_FEN
;
100 writel(lcr
, ®s
->pl011_lcrh
);
104 static int pl01x_generic_setbrg(struct pl01x_regs
*regs
, enum pl01x_type type
,
105 int clock
, int baudrate
)
109 unsigned int divisor
;
111 /* disable everything */
112 writel(0, ®s
->pl010_cr
);
116 divisor
= UART_PL010_BAUD_9600
;
119 divisor
= UART_PL010_BAUD_19200
;
122 divisor
= UART_PL010_BAUD_38400
;
125 divisor
= UART_PL010_BAUD_57600
;
128 divisor
= UART_PL010_BAUD_115200
;
131 divisor
= UART_PL010_BAUD_38400
;
134 writel((divisor
& 0xf00) >> 8, ®s
->pl010_lcrm
);
135 writel(divisor
& 0xff, ®s
->pl010_lcrl
);
138 * Set line control for the PL010 to be 8 bits, 1 stop bit,
139 * no parity, fifo enabled
141 writel(UART_PL010_LCRH_WLEN_8
| UART_PL010_LCRH_FEN
,
143 /* Finally, enable the UART */
144 writel(UART_PL010_CR_UARTEN
, ®s
->pl010_cr
);
149 unsigned int divider
;
150 unsigned int remainder
;
151 unsigned int fraction
;
156 * IBRD = UART_CLK / (16 * BAUD_RATE)
157 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
158 * / (16 * BAUD_RATE))
160 temp
= 16 * baudrate
;
161 divider
= clock
/ temp
;
162 remainder
= clock
% temp
;
163 temp
= (8 * remainder
) / baudrate
;
164 fraction
= (temp
>> 1) + (temp
& 1);
166 writel(divider
, ®s
->pl011_ibrd
);
167 writel(fraction
, ®s
->pl011_fbrd
);
169 pl011_set_line_control(regs
);
170 /* Finally, enable the UART */
171 writel(UART_PL011_CR_UARTEN
| UART_PL011_CR_TXE
|
172 UART_PL011_CR_RXE
| UART_PL011_CR_RTS
, ®s
->pl011_cr
);
182 #ifndef CONFIG_DM_SERIAL
183 static void pl01x_serial_init_baud(int baudrate
)
187 #if defined(CONFIG_PL010_SERIAL)
188 pl01x_type
= TYPE_PL010
;
189 #elif defined(CONFIG_PL011_SERIAL)
190 pl01x_type
= TYPE_PL011
;
191 clock
= CONFIG_PL011_CLOCK
;
193 base_regs
= (struct pl01x_regs
*)port
[CONFIG_CONS_INDEX
];
195 pl01x_generic_serial_init(base_regs
, pl01x_type
);
196 pl01x_generic_setbrg(base_regs
, pl01x_type
, clock
, baudrate
);
200 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
201 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
202 * Versatile PB has four UARTs.
204 int pl01x_serial_init(void)
206 pl01x_serial_init_baud(CONFIG_BAUDRATE
);
211 static void pl01x_serial_putc(const char c
)
214 while (pl01x_putc(base_regs
, '\r') == -EAGAIN
);
216 while (pl01x_putc(base_regs
, c
) == -EAGAIN
);
219 static int pl01x_serial_getc(void)
222 int ch
= pl01x_getc(base_regs
);
233 static int pl01x_serial_tstc(void)
235 return pl01x_tstc(base_regs
);
238 static void pl01x_serial_setbrg(void)
241 * Flush FIFO and wait for non-busy before changing baudrate to avoid
244 while (!(readl(&base_regs
->fr
) & UART_PL01x_FR_TXFE
))
246 while (readl(&base_regs
->fr
) & UART_PL01x_FR_BUSY
)
248 pl01x_serial_init_baud(gd
->baudrate
);
251 static struct serial_device pl01x_serial_drv
= {
252 .name
= "pl01x_serial",
253 .start
= pl01x_serial_init
,
255 .setbrg
= pl01x_serial_setbrg
,
256 .putc
= pl01x_serial_putc
,
257 .puts
= default_serial_puts
,
258 .getc
= pl01x_serial_getc
,
259 .tstc
= pl01x_serial_tstc
,
262 void pl01x_serial_initialize(void)
264 serial_register(&pl01x_serial_drv
);
267 __weak
struct serial_device
*default_serial_console(void)
269 return &pl01x_serial_drv
;
272 #endif /* nCONFIG_DM_SERIAL */
274 #ifdef CONFIG_DM_SERIAL
276 static int pl01x_serial_setbrg(struct udevice
*dev
, int baudrate
)
278 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
279 struct pl01x_priv
*priv
= dev_get_priv(dev
);
281 if (!plat
->skip_init
) {
282 pl01x_generic_setbrg(priv
->regs
, priv
->type
, plat
->clock
,
289 int pl01x_serial_probe(struct udevice
*dev
)
291 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
292 struct pl01x_priv
*priv
= dev_get_priv(dev
);
294 priv
->regs
= (struct pl01x_regs
*)plat
->base
;
295 priv
->type
= plat
->type
;
296 if (!plat
->skip_init
)
297 return pl01x_generic_serial_init(priv
->regs
, priv
->type
);
302 static int pl01x_serial_getc(struct udevice
*dev
)
304 struct pl01x_priv
*priv
= dev_get_priv(dev
);
306 return pl01x_getc(priv
->regs
);
309 static int pl01x_serial_putc(struct udevice
*dev
, const char ch
)
311 struct pl01x_priv
*priv
= dev_get_priv(dev
);
313 return pl01x_putc(priv
->regs
, ch
);
316 static int pl01x_serial_pending(struct udevice
*dev
, bool input
)
318 struct pl01x_priv
*priv
= dev_get_priv(dev
);
319 unsigned int fr
= readl(&priv
->regs
->fr
);
322 return pl01x_tstc(priv
->regs
);
324 return fr
& UART_PL01x_FR_TXFF
? 0 : 1;
327 const struct dm_serial_ops pl01x_serial_ops
= {
328 .putc
= pl01x_serial_putc
,
329 .pending
= pl01x_serial_pending
,
330 .getc
= pl01x_serial_getc
,
331 .setbrg
= pl01x_serial_setbrg
,
334 #if CONFIG_IS_ENABLED(OF_CONTROL)
335 static const struct udevice_id pl01x_serial_id
[] ={
336 {.compatible
= "arm,pl011", .data
= TYPE_PL011
},
337 {.compatible
= "arm,pl010", .data
= TYPE_PL010
},
341 int pl01x_serial_ofdata_to_platdata(struct udevice
*dev
)
343 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
346 addr
= devfdt_get_addr(dev
);
347 if (addr
== FDT_ADDR_T_NONE
)
351 plat
->clock
= dev_read_u32_default(dev
, "clock", 1);
352 plat
->type
= dev_get_driver_data(dev
);
353 plat
->skip_init
= dev_read_bool(dev
, "skip-init");
359 U_BOOT_DRIVER(serial_pl01x
) = {
360 .name
= "serial_pl01x",
362 .of_match
= of_match_ptr(pl01x_serial_id
),
363 .ofdata_to_platdata
= of_match_ptr(pl01x_serial_ofdata_to_platdata
),
364 .platdata_auto_alloc_size
= sizeof(struct pl01x_serial_platdata
),
365 .probe
= pl01x_serial_probe
,
366 .ops
= &pl01x_serial_ops
,
367 .flags
= DM_FLAG_PRE_RELOC
,
368 .priv_auto_alloc_size
= sizeof(struct pl01x_priv
),
373 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
375 #include <debug_uart.h>
377 static void _debug_uart_init(void)
379 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
380 struct pl01x_regs
*regs
= (struct pl01x_regs
*)CONFIG_DEBUG_UART_BASE
;
381 enum pl01x_type type
= CONFIG_IS_ENABLED(DEBUG_UART_PL011
) ?
382 TYPE_PL011
: TYPE_PL010
;
384 pl01x_generic_serial_init(regs
, type
);
385 pl01x_generic_setbrg(regs
, type
,
386 CONFIG_DEBUG_UART_CLOCK
, CONFIG_BAUDRATE
);
390 static inline void _debug_uart_putc(int ch
)
392 struct pl01x_regs
*regs
= (struct pl01x_regs
*)CONFIG_DEBUG_UART_BASE
;
394 pl01x_putc(regs
, ch
);