3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
24 #ifndef CONFIG_DM_SERIAL
26 static volatile unsigned char *const port
[] = CONFIG_PL01x_PORTS
;
27 static enum pl01x_type pl01x_type
__attribute__ ((section(".data")));
28 static struct pl01x_regs
*base_regs
__attribute__ ((section(".data")));
29 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
31 DECLARE_GLOBAL_DATA_PTR
;
34 static int pl01x_putc(struct pl01x_regs
*regs
, char c
)
36 /* Wait until there is space in the FIFO */
37 if (readl(®s
->fr
) & UART_PL01x_FR_TXFF
)
40 /* Send the character */
46 static int pl01x_getc(struct pl01x_regs
*regs
)
50 /* Wait until there is data in the FIFO */
51 if (readl(®s
->fr
) & UART_PL01x_FR_RXFE
)
54 data
= readl(®s
->dr
);
56 /* Check for an error flag */
57 if (data
& 0xFFFFFF00) {
59 writel(0xFFFFFFFF, ®s
->ecr
);
66 static int pl01x_tstc(struct pl01x_regs
*regs
)
69 return !(readl(®s
->fr
) & UART_PL01x_FR_RXFE
);
72 static int pl01x_generic_serial_init(struct pl01x_regs
*regs
,
77 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
78 if (type
== TYPE_PL011
) {
79 /* Empty RX fifo if necessary */
80 if (readl(®s
->pl011_cr
) & UART_PL011_CR_UARTEN
) {
81 while (!(readl(®s
->fr
) & UART_PL01x_FR_RXFE
))
87 /* First, disable everything */
88 writel(0, ®s
->pl010_cr
);
90 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
91 lcr
= UART_PL011_LCRH_WLEN_8
| UART_PL011_LCRH_FEN
;
92 writel(lcr
, ®s
->pl011_lcrh
);
98 #ifdef CONFIG_PL011_SERIAL_RLCR
102 * Program receive line control register after waiting
103 * 10 bus cycles. Delay be writing to readonly register
106 for (i
= 0; i
< 10; i
++)
107 writel(lcr
, ®s
->fr
);
109 writel(lcr
, ®s
->pl011_rlcr
);
110 /* lcrh needs to be set again for change to be effective */
111 writel(lcr
, ®s
->pl011_lcrh
);
122 static int pl01x_generic_setbrg(struct pl01x_regs
*regs
, enum pl01x_type type
,
123 int clock
, int baudrate
)
127 unsigned int divisor
;
131 divisor
= UART_PL010_BAUD_9600
;
134 divisor
= UART_PL010_BAUD_9600
;
137 divisor
= UART_PL010_BAUD_38400
;
140 divisor
= UART_PL010_BAUD_57600
;
143 divisor
= UART_PL010_BAUD_115200
;
146 divisor
= UART_PL010_BAUD_38400
;
149 writel((divisor
& 0xf00) >> 8, ®s
->pl010_lcrm
);
150 writel(divisor
& 0xff, ®s
->pl010_lcrl
);
152 /* Finally, enable the UART */
153 writel(UART_PL010_CR_UARTEN
, ®s
->pl010_cr
);
158 unsigned int divider
;
159 unsigned int remainder
;
160 unsigned int fraction
;
165 * IBRD = UART_CLK / (16 * BAUD_RATE)
166 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
167 * / (16 * BAUD_RATE))
169 temp
= 16 * baudrate
;
170 divider
= clock
/ temp
;
171 remainder
= clock
% temp
;
172 temp
= (8 * remainder
) / baudrate
;
173 fraction
= (temp
>> 1) + (temp
& 1);
175 writel(divider
, ®s
->pl011_ibrd
);
176 writel(fraction
, ®s
->pl011_fbrd
);
178 /* Finally, enable the UART */
179 writel(UART_PL011_CR_UARTEN
| UART_PL011_CR_TXE
|
180 UART_PL011_CR_RXE
| UART_PL011_CR_RTS
, ®s
->pl011_cr
);
190 #ifndef CONFIG_DM_SERIAL
191 static void pl01x_serial_init_baud(int baudrate
)
195 #if defined(CONFIG_PL010_SERIAL)
196 pl01x_type
= TYPE_PL010
;
197 #elif defined(CONFIG_PL011_SERIAL)
198 pl01x_type
= TYPE_PL011
;
199 clock
= CONFIG_PL011_CLOCK
;
201 base_regs
= (struct pl01x_regs
*)port
[CONFIG_CONS_INDEX
];
203 pl01x_generic_serial_init(base_regs
, pl01x_type
);
204 pl01x_generic_setbrg(base_regs
, TYPE_PL010
, clock
, baudrate
);
208 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
209 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
210 * Versatile PB has four UARTs.
212 int pl01x_serial_init(void)
214 pl01x_serial_init_baud(CONFIG_BAUDRATE
);
219 static void pl01x_serial_putc(const char c
)
222 while (pl01x_putc(base_regs
, '\r') == -EAGAIN
);
224 while (pl01x_putc(base_regs
, c
) == -EAGAIN
);
227 static int pl01x_serial_getc(void)
230 int ch
= pl01x_getc(base_regs
);
241 static int pl01x_serial_tstc(void)
243 return pl01x_tstc(base_regs
);
246 static void pl01x_serial_setbrg(void)
249 * Flush FIFO and wait for non-busy before changing baudrate to avoid
252 while (!(readl(&base_regs
->fr
) & UART_PL01x_FR_TXFE
))
254 while (readl(&base_regs
->fr
) & UART_PL01x_FR_BUSY
)
256 pl01x_serial_init_baud(gd
->baudrate
);
259 static struct serial_device pl01x_serial_drv
= {
260 .name
= "pl01x_serial",
261 .start
= pl01x_serial_init
,
263 .setbrg
= pl01x_serial_setbrg
,
264 .putc
= pl01x_serial_putc
,
265 .puts
= default_serial_puts
,
266 .getc
= pl01x_serial_getc
,
267 .tstc
= pl01x_serial_tstc
,
270 void pl01x_serial_initialize(void)
272 serial_register(&pl01x_serial_drv
);
275 __weak
struct serial_device
*default_serial_console(void)
277 return &pl01x_serial_drv
;
280 #endif /* nCONFIG_DM_SERIAL */
282 #ifdef CONFIG_DM_SERIAL
285 struct pl01x_regs
*regs
;
286 enum pl01x_type type
;
289 static int pl01x_serial_setbrg(struct udevice
*dev
, int baudrate
)
291 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
292 struct pl01x_priv
*priv
= dev_get_priv(dev
);
294 pl01x_generic_setbrg(priv
->regs
, priv
->type
, plat
->clock
, baudrate
);
299 static int pl01x_serial_probe(struct udevice
*dev
)
301 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
302 struct pl01x_priv
*priv
= dev_get_priv(dev
);
304 priv
->regs
= (struct pl01x_regs
*)plat
->base
;
305 priv
->type
= plat
->type
;
306 return pl01x_generic_serial_init(priv
->regs
, priv
->type
);
309 static int pl01x_serial_getc(struct udevice
*dev
)
311 struct pl01x_priv
*priv
= dev_get_priv(dev
);
313 return pl01x_getc(priv
->regs
);
316 static int pl01x_serial_putc(struct udevice
*dev
, const char ch
)
318 struct pl01x_priv
*priv
= dev_get_priv(dev
);
320 return pl01x_putc(priv
->regs
, ch
);
323 static int pl01x_serial_pending(struct udevice
*dev
, bool input
)
325 struct pl01x_priv
*priv
= dev_get_priv(dev
);
326 unsigned int fr
= readl(&priv
->regs
->fr
);
329 return pl01x_tstc(priv
->regs
);
331 return fr
& UART_PL01x_FR_TXFF
? 0 : 1;
334 static const struct dm_serial_ops pl01x_serial_ops
= {
335 .putc
= pl01x_serial_putc
,
336 .pending
= pl01x_serial_pending
,
337 .getc
= pl01x_serial_getc
,
338 .setbrg
= pl01x_serial_setbrg
,
341 U_BOOT_DRIVER(serial_pl01x
) = {
342 .name
= "serial_pl01x",
344 .probe
= pl01x_serial_probe
,
345 .ops
= &pl01x_serial_ops
,
346 .flags
= DM_FLAG_PRE_RELOC
,