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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/serial/serial_pl01x.c
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
33 #include "serial_pl01x.h"
36 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
37 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
38 * Versatile PB has four UARTs.
40 #define CONSOLE_PORT CONFIG_CONS_INDEX
41 static volatile unsigned char *const port
[] = CONFIG_PL01x_PORTS
;
42 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
44 static void pl01x_putc (int portnum
, char c
);
45 static int pl01x_getc (int portnum
);
46 static int pl01x_tstc (int portnum
);
47 unsigned int baudrate
= CONFIG_BAUDRATE
;
48 DECLARE_GLOBAL_DATA_PTR
;
50 static struct pl01x_regs
*pl01x_get_regs(int portnum
)
52 return (struct pl01x_regs
*) port
[portnum
];
55 #ifdef CONFIG_PL010_SERIAL
57 int serial_init (void)
59 struct pl01x_regs
*regs
= pl01x_get_regs(CONSOLE_PORT
);
62 /* First, disable everything */
63 writel(0, ®s
->pl010_cr
);
68 divisor
= UART_PL010_BAUD_9600
;
72 divisor
= UART_PL010_BAUD_9600
;
76 divisor
= UART_PL010_BAUD_38400
;
80 divisor
= UART_PL010_BAUD_57600
;
84 divisor
= UART_PL010_BAUD_115200
;
88 divisor
= UART_PL010_BAUD_38400
;
91 writel((divisor
& 0xf00) >> 8, ®s
->pl010_lcrm
);
92 writel(divisor
& 0xff, ®s
->pl010_lcrl
);
94 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
95 writel(UART_PL010_LCRH_WLEN_8
| UART_PL010_LCRH_FEN
, ®s
->pl010_lcrh
);
97 /* Finally, enable the UART */
98 writel(UART_PL010_CR_UARTEN
, ®s
->pl010_cr
);
103 #endif /* CONFIG_PL010_SERIAL */
105 #ifdef CONFIG_PL011_SERIAL
107 int serial_init (void)
109 struct pl01x_regs
*regs
= pl01x_get_regs(CONSOLE_PORT
);
111 unsigned int divider
;
112 unsigned int remainder
;
113 unsigned int fraction
;
116 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
117 /* Empty RX fifo if necessary */
118 if (readl(®s
->pl011_cr
) & UART_PL011_CR_UARTEN
) {
119 while (!(readl(®s
->fr
) & UART_PL01x_FR_RXFE
))
124 /* First, disable everything */
125 writel(0, ®s
->pl011_cr
);
130 * IBRD = UART_CLK / (16 * BAUD_RATE)
131 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
133 temp
= 16 * baudrate
;
134 divider
= CONFIG_PL011_CLOCK
/ temp
;
135 remainder
= CONFIG_PL011_CLOCK
% temp
;
136 temp
= (8 * remainder
) / baudrate
;
137 fraction
= (temp
>> 1) + (temp
& 1);
139 writel(divider
, ®s
->pl011_ibrd
);
140 writel(fraction
, ®s
->pl011_fbrd
);
142 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
143 lcr
= UART_PL011_LCRH_WLEN_8
| UART_PL011_LCRH_FEN
;
144 writel(lcr
, ®s
->pl011_lcrh
);
146 #ifdef CONFIG_PL011_SERIAL_RLCR
151 * Program receive line control register after waiting
152 * 10 bus cycles. Delay be writing to readonly register
155 for (i
= 0; i
< 10; i
++)
156 writel(lcr
, ®s
->fr
);
158 writel(lcr
, ®s
->pl011_rlcr
);
159 /* lcrh needs to be set again for change to be effective */
160 writel(lcr
, ®s
->pl011_lcrh
);
163 /* Finally, enable the UART */
164 writel(UART_PL011_CR_UARTEN
| UART_PL011_CR_TXE
| UART_PL011_CR_RXE
,
170 #endif /* CONFIG_PL011_SERIAL */
172 void serial_putc (const char c
)
175 pl01x_putc (CONSOLE_PORT
, '\r');
177 pl01x_putc (CONSOLE_PORT
, c
);
180 void serial_puts (const char *s
)
187 int serial_getc (void)
189 return pl01x_getc (CONSOLE_PORT
);
192 int serial_tstc (void)
194 return pl01x_tstc (CONSOLE_PORT
);
197 void serial_setbrg (void)
199 struct pl01x_regs
*regs
= pl01x_get_regs(CONSOLE_PORT
);
201 baudrate
= gd
->baudrate
;
203 * Flush FIFO and wait for non-busy before changing baudrate to avoid
206 while (!(readl(®s
->fr
) & UART_PL01x_FR_TXFE
))
208 while (readl(®s
->fr
) & UART_PL01x_FR_BUSY
)
213 static void pl01x_putc (int portnum
, char c
)
215 struct pl01x_regs
*regs
= pl01x_get_regs(portnum
);
217 /* Wait until there is space in the FIFO */
218 while (readl(®s
->fr
) & UART_PL01x_FR_TXFF
)
221 /* Send the character */
222 writel(c
, ®s
->dr
);
225 static int pl01x_getc (int portnum
)
227 struct pl01x_regs
*regs
= pl01x_get_regs(portnum
);
230 /* Wait until there is data in the FIFO */
231 while (readl(®s
->fr
) & UART_PL01x_FR_RXFE
)
234 data
= readl(®s
->dr
);
236 /* Check for an error flag */
237 if (data
& 0xFFFFFF00) {
238 /* Clear the error */
239 writel(0xFFFFFFFF, ®s
->ecr
);
246 static int pl01x_tstc (int portnum
)
248 struct pl01x_regs
*regs
= pl01x_get_regs(portnum
);
251 return !(readl(®s
->fr
) & UART_PL01x_FR_RXFE
);