2 * SuperH SCIF device driver.
3 * Copyright (C) 2013 Renesas Electronics Corporation
4 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
5 * Copyright (C) 2002 - 2008 Paul Mundt
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/processor.h>
16 #include <linux/compiler.h>
17 #include <dm/platform_data/serial_sh.h>
18 #include "serial_sh.h"
20 DECLARE_GLOBAL_DATA_PTR
;
22 #if defined(CONFIG_CPU_SH7760) || \
23 defined(CONFIG_CPU_SH7780) || \
24 defined(CONFIG_CPU_SH7785) || \
25 defined(CONFIG_CPU_SH7786)
26 static int scif_rxfill(struct uart_port
*port
)
28 return sci_in(port
, SCRFDR
) & 0xff;
30 #elif defined(CONFIG_CPU_SH7763)
31 static int scif_rxfill(struct uart_port
*port
)
33 if ((port
->mapbase
== 0xffe00000) ||
34 (port
->mapbase
== 0xffe08000)) {
36 return sci_in(port
, SCRFDR
) & 0xff;
39 return sci_in(port
, SCFDR
) & SCIF2_RFDC_MASK
;
42 #elif defined(CONFIG_ARCH_SH7372)
43 static int scif_rxfill(struct uart_port
*port
)
45 if (port
->type
== PORT_SCIFA
)
46 return sci_in(port
, SCFDR
) & SCIF_RFDC_MASK
;
48 return sci_in(port
, SCRFDR
);
51 static int scif_rxfill(struct uart_port
*port
)
53 return sci_in(port
, SCFDR
) & SCIF_RFDC_MASK
;
57 static void sh_serial_init_generic(struct uart_port
*port
)
59 sci_out(port
, SCSCR
, SCSCR_INIT(port
));
60 sci_out(port
, SCSCR
, SCSCR_INIT(port
));
61 sci_out(port
, SCSMR
, 0);
62 sci_out(port
, SCSMR
, 0);
63 sci_out(port
, SCFCR
, SCFCR_RFRST
|SCFCR_TFRST
);
65 sci_out(port
, SCFCR
, 0);
69 sh_serial_setbrg_generic(struct uart_port
*port
, int clk
, int baudrate
)
71 if (port
->clk_mode
== EXT_CLK
) {
72 unsigned short dl
= DL_VALUE(baudrate
, clk
);
73 sci_out(port
, DL
, dl
);
74 /* Need wait: Clock * 1/dl * 1/16 */
75 udelay((1000000 * dl
* 16 / clk
) * 1000 + 1);
77 sci_out(port
, SCBRR
, SCBRR_VALUE(baudrate
, clk
));
81 static void handle_error(struct uart_port
*port
)
84 sci_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
86 sci_out(port
, SCLSR
, 0x00);
89 static int serial_raw_putc(struct uart_port
*port
, const char c
)
91 /* Tx fifo is empty */
92 if (!(sci_in(port
, SCxSR
) & SCxSR_TEND(port
)))
95 sci_out(port
, SCxTDR
, c
);
96 sci_out(port
, SCxSR
, sci_in(port
, SCxSR
) & ~SCxSR_TEND(port
));
101 static int serial_rx_fifo_level(struct uart_port
*port
)
103 return scif_rxfill(port
);
106 static int sh_serial_tstc_generic(struct uart_port
*port
)
108 if (sci_in(port
, SCxSR
) & SCIF_ERRORS
) {
113 return serial_rx_fifo_level(port
) ? 1 : 0;
116 static int serial_getc_check(struct uart_port
*port
)
118 unsigned short status
;
120 status
= sci_in(port
, SCxSR
);
122 if (status
& SCIF_ERRORS
)
124 if (sci_in(port
, SCLSR
) & SCxSR_ORER(port
))
126 return status
& (SCIF_DR
| SCxSR_RDxF(port
));
129 static int sh_serial_getc_generic(struct uart_port
*port
)
131 unsigned short status
;
134 if (!serial_getc_check(port
))
137 ch
= sci_in(port
, SCxRDR
);
138 status
= sci_in(port
, SCxSR
);
140 sci_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
142 if (status
& SCIF_ERRORS
)
145 if (sci_in(port
, SCLSR
) & SCxSR_ORER(port
))
151 #ifdef CONFIG_DM_SERIAL
153 static int sh_serial_pending(struct udevice
*dev
, bool input
)
155 struct uart_port
*priv
= dev_get_priv(dev
);
157 return sh_serial_tstc_generic(priv
);
160 static int sh_serial_putc(struct udevice
*dev
, const char ch
)
162 struct uart_port
*priv
= dev_get_priv(dev
);
164 return serial_raw_putc(priv
, ch
);
167 static int sh_serial_getc(struct udevice
*dev
)
169 struct uart_port
*priv
= dev_get_priv(dev
);
171 return sh_serial_getc_generic(priv
);
174 static int sh_serial_setbrg(struct udevice
*dev
, int baudrate
)
176 struct sh_serial_platdata
*plat
= dev_get_platdata(dev
);
177 struct uart_port
*priv
= dev_get_priv(dev
);
179 sh_serial_setbrg_generic(priv
, plat
->clk
, baudrate
);
184 static int sh_serial_probe(struct udevice
*dev
)
186 struct sh_serial_platdata
*plat
= dev_get_platdata(dev
);
187 struct uart_port
*priv
= dev_get_priv(dev
);
189 priv
->membase
= (unsigned char *)plat
->base
;
190 priv
->mapbase
= plat
->base
;
191 priv
->type
= plat
->type
;
192 priv
->clk_mode
= plat
->clk_mode
;
194 sh_serial_init_generic(priv
);
199 static const struct dm_serial_ops sh_serial_ops
= {
200 .putc
= sh_serial_putc
,
201 .pending
= sh_serial_pending
,
202 .getc
= sh_serial_getc
,
203 .setbrg
= sh_serial_setbrg
,
206 #ifdef CONFIG_OF_CONTROL
207 static const struct udevice_id sh_serial_id
[] ={
208 {.compatible
= "renesas,sci", .data
= PORT_SCI
},
209 {.compatible
= "renesas,scif", .data
= PORT_SCIF
},
210 {.compatible
= "renesas,scifa", .data
= PORT_SCIFA
},
214 static int sh_serial_ofdata_to_platdata(struct udevice
*dev
)
216 struct sh_serial_platdata
*plat
= dev_get_platdata(dev
);
219 addr
= fdtdec_get_addr(gd
->fdt_blob
, dev_of_offset(dev
), "reg");
220 if (addr
== FDT_ADDR_T_NONE
)
224 plat
->clk
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
), "clock",
226 plat
->type
= dev_get_driver_data(dev
);
231 U_BOOT_DRIVER(serial_sh
) = {
234 .of_match
= of_match_ptr(sh_serial_id
),
235 .ofdata_to_platdata
= of_match_ptr(sh_serial_ofdata_to_platdata
),
236 .platdata_auto_alloc_size
= sizeof(struct sh_serial_platdata
),
237 .probe
= sh_serial_probe
,
238 .ops
= &sh_serial_ops
,
239 .flags
= DM_FLAG_PRE_RELOC
,
240 .priv_auto_alloc_size
= sizeof(struct uart_port
),
243 #else /* CONFIG_DM_SERIAL */
245 #if defined(CONFIG_CONS_SCIF0)
246 # define SCIF_BASE SCIF0_BASE
247 #elif defined(CONFIG_CONS_SCIF1)
248 # define SCIF_BASE SCIF1_BASE
249 #elif defined(CONFIG_CONS_SCIF2)
250 # define SCIF_BASE SCIF2_BASE
251 #elif defined(CONFIG_CONS_SCIF3)
252 # define SCIF_BASE SCIF3_BASE
253 #elif defined(CONFIG_CONS_SCIF4)
254 # define SCIF_BASE SCIF4_BASE
255 #elif defined(CONFIG_CONS_SCIF5)
256 # define SCIF_BASE SCIF5_BASE
257 #elif defined(CONFIG_CONS_SCIF6)
258 # define SCIF_BASE SCIF6_BASE
259 #elif defined(CONFIG_CONS_SCIF7)
260 # define SCIF_BASE SCIF7_BASE
262 # error "Default SCIF doesn't set....."
265 #if defined(CONFIG_SCIF_A)
266 #define SCIF_BASE_PORT PORT_SCIFA
267 #elif defined(CONFIG_SCI)
268 #define SCIF_BASE_PORT PORT_SCI
270 #define SCIF_BASE_PORT PORT_SCIF
273 static struct uart_port sh_sci
= {
274 .membase
= (unsigned char *)SCIF_BASE
,
275 .mapbase
= SCIF_BASE
,
276 .type
= SCIF_BASE_PORT
,
277 #ifdef CONFIG_SCIF_USE_EXT_CLK
282 static void sh_serial_setbrg(void)
284 DECLARE_GLOBAL_DATA_PTR
;
285 struct uart_port
*port
= &sh_sci
;
287 sh_serial_setbrg_generic(port
, CONFIG_SH_SCIF_CLK_FREQ
, gd
->baudrate
);
290 static int sh_serial_init(void)
292 struct uart_port
*port
= &sh_sci
;
294 sh_serial_init_generic(port
);
300 static void sh_serial_putc(const char c
)
302 struct uart_port
*port
= &sh_sci
;
306 if (serial_raw_putc(port
, '\r') != -EAGAIN
)
311 if (serial_raw_putc(port
, c
) != -EAGAIN
)
316 static int sh_serial_tstc(void)
318 struct uart_port
*port
= &sh_sci
;
320 return sh_serial_tstc_generic(port
);
323 static int sh_serial_getc(void)
325 struct uart_port
*port
= &sh_sci
;
329 ch
= sh_serial_getc_generic(port
);
337 static struct serial_device sh_serial_drv
= {
339 .start
= sh_serial_init
,
341 .setbrg
= sh_serial_setbrg
,
342 .putc
= sh_serial_putc
,
343 .puts
= default_serial_puts
,
344 .getc
= sh_serial_getc
,
345 .tstc
= sh_serial_tstc
,
348 void sh_serial_initialize(void)
350 serial_register(&sh_serial_drv
);
353 __weak
struct serial_device
*default_serial_console(void)
355 return &sh_serial_drv
;
357 #endif /* CONFIG_DM_SERIAL */