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serial: sh: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2
[u-boot.git] / drivers / serial / serial_sh.h
1 /*
2 * Copy and modify from linux/drivers/serial/sh-sci.h
3 */
4
5 #include <dm/platform_data/serial_sh.h>
6
7 struct uart_port {
8 unsigned long iobase; /* in/out[bwl] */
9 unsigned char *membase; /* read/write[bwl] */
10 unsigned long mapbase; /* for ioremap */
11 enum sh_serial_type type; /* port type */
12 enum sh_clk_mode clk_mode; /* clock mode */
13 };
14
15 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
16 #include <asm/regs306x.h>
17 #endif
18 #if defined(CONFIG_H8S2678)
19 #include <asm/regs267x.h>
20 #endif
21
22 #if defined(CONFIG_CPU_SH7706) || \
23 defined(CONFIG_CPU_SH7707) || \
24 defined(CONFIG_CPU_SH7708) || \
25 defined(CONFIG_CPU_SH7709)
26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
27 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
29 #elif defined(CONFIG_CPU_SH7705)
30 # define SCIF0 0xA4400000
31 # define SCIF2 0xA4410000
32 # define SCSMR_Ir 0xA44A0000
33 # define IRDA_SCIF SCIF0
34 # define SCPCR 0xA4000116
35 # define SCPDR 0xA4000136
36
37 /* Set the clock source,
38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
40 */
41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
42 #elif defined(CONFIG_CPU_SH7720) || \
43 defined(CONFIG_CPU_SH7721) || \
44 defined(CONFIG_ARCH_SH7367) || \
45 defined(CONFIG_ARCH_SH7377) || \
46 defined(CONFIG_ARCH_SH7372) || \
47 defined(CONFIG_SH73A0) || \
48 defined(CONFIG_R8A7740)
49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
50 # define PORT_PTCR 0xA405011EUL
51 # define PORT_PVCR 0xA4050122UL
52 # define SCIF_ORER 0x0200 /* overrun error bit */
53 #elif defined(CONFIG_SH_RTS7751R2D)
54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56 # define SCIF_ORER 0x0001 /* overrun error bit */
57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58 #elif defined(CONFIG_CPU_SH7750) || \
59 defined(CONFIG_CPU_SH7750R) || \
60 defined(CONFIG_CPU_SH7750S) || \
61 defined(CONFIG_CPU_SH7091) || \
62 defined(CONFIG_CPU_SH7751) || \
63 defined(CONFIG_CPU_SH7751R)
64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66 # define SCIF_ORER 0x0001 /* overrun error bit */
67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
70 #elif defined(CONFIG_CPU_SH7760)
71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
74 # define SCIF_ORER 0x0001 /* overrun error bit */
75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78 # define SCIF_ORER 0x0001 /* overrun error bit */
79 # define PACR 0xa4050100
80 # define PBCR 0xa4050102
81 # define SCSCR_INIT(port) 0x3B
82 #elif defined(CONFIG_CPU_SH7343)
83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
86 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
88 #elif defined(CONFIG_CPU_SH7722)
89 # define PADR 0xA4050120
90 # undef PSDR
91 # define PSDR 0xA405013e
92 # define PWDR 0xA4050166
93 # define PSCR 0xA405011E
94 # define SCIF_ORER 0x0001 /* overrun error bit */
95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96 #elif defined(CONFIG_CPU_SH7366)
97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
98 # define SCSPTR0 SCPDR0
99 # define SCIF_ORER 0x0001 /* overrun error bit */
100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101 #elif defined(CONFIG_CPU_SH7723)
102 # define SCSPTR0 0xa4050160
103 # define SCSPTR1 0xa405013e
104 # define SCSPTR2 0xa4050160
105 # define SCSPTR3 0xa405013e
106 # define SCSPTR4 0xa4050128
107 # define SCSPTR5 0xa4050128
108 # define SCIF_ORER 0x0001 /* overrun error bit */
109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
110 #elif defined(CONFIG_CPU_SH7724)
111 # define SCIF_ORER 0x0001 /* overrun error bit */
112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
115 #elif defined(CONFIG_CPU_SH7734)
116 # define SCSPTR0 0xFFE40020
117 # define SCSPTR1 0xFFE41020
118 # define SCSPTR2 0xFFE42020
119 # define SCSPTR3 0xFFE43020
120 # define SCSPTR4 0xFFE44020
121 # define SCSPTR5 0xFFE45020
122 # define SCIF_ORER 0x0001 /* overrun error bit */
123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
124 #elif defined(CONFIG_CPU_SH4_202)
125 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
126 # define SCIF_ORER 0x0001 /* overrun error bit */
127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
128 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
129 # define SCIF_BASE_ADDR 0x01030000
130 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
131 # define SCIF_PTR2_OFFS 0x0000020
132 # define SCIF_LSR2_OFFS 0x0000024
133 # define SCSPTR\
134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
135 # define SCLSR2\
136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
138 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
141 #elif defined(CONFIG_H8S2678)
142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
144 #elif defined(CONFIG_CPU_SH7757) || \
145 defined(CONFIG_CPU_SH7752) || \
146 defined(CONFIG_CPU_SH7753)
147 # define SCSPTR0 0xfe4b0020
148 # define SCSPTR1 0xfe4b0020
149 # define SCSPTR2 0xfe4b0020
150 # define SCIF_ORER 0x0001
151 # define SCSCR_INIT(port) 0x38
152 # define SCIF_ONLY
153 #elif defined(CONFIG_CPU_SH7763)
154 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
155 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
156 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
157 # define SCIF_ORER 0x0001 /* overrun error bit */
158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
159 #elif defined(CONFIG_CPU_SH7770)
160 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
161 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
162 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
163 # define SCIF_ORER 0x0001 /* overrun error bit */
164 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
165 #elif defined(CONFIG_CPU_SH7780)
166 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
167 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
168 # define SCIF_ORER 0x0001 /* Overrun error bit */
169
170 #if defined(CONFIG_SH_SH2007)
171 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
172 # define SCSCR_INIT(port) 0x38
173 #else
174 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
175 # define SCSCR_INIT(port) 0x3a
176 #endif
177
178 #elif defined(CONFIG_CPU_SH7785) || \
179 defined(CONFIG_CPU_SH7786)
180 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
181 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
182 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
183 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
184 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
185 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
186 # define SCIF_ORER 0x0001 /* Overrun error bit */
187 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
188 #elif defined(CONFIG_CPU_SH7201) || \
189 defined(CONFIG_CPU_SH7203) || \
190 defined(CONFIG_CPU_SH7206) || \
191 defined(CONFIG_CPU_SH7263) || \
192 defined(CONFIG_CPU_SH7264)
193 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
194 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
195 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
196 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
197 # if defined(CONFIG_CPU_SH7201)
198 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
199 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
200 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
201 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
202 # endif
203 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
204 #elif defined(CONFIG_CPU_SH7269)
205 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
206 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
207 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
208 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
209 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
210 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
211 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
212 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
213 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
214 #elif defined(CONFIG_CPU_SH7619)
215 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
216 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
217 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
218 # define SCIF_ORER 0x0001 /* overrun error bit */
219 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
220 #elif defined(CONFIG_CPU_SHX3)
221 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
222 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
223 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
224 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
225 # define SCIF_ORER 0x0001 /* Overrun error bit */
226 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
227 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3)
228 # if defined(CONFIG_SCIF_A)
229 # define SCIF_ORER 0x0200
230 # else
231 # define SCIF_ORER 0x0001
232 # endif
233 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
234 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
235 #else
236 # error CPU subtype not defined
237 #endif
238
239 /* SCSCR */
240 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
241 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
242 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
243 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
244 #if defined(CONFIG_CPU_SH7750) || \
245 defined(CONFIG_CPU_SH7091) || \
246 defined(CONFIG_CPU_SH7750R) || \
247 defined(CONFIG_CPU_SH7722) || \
248 defined(CONFIG_CPU_SH7734) || \
249 defined(CONFIG_CPU_SH7750S) || \
250 defined(CONFIG_CPU_SH7751) || \
251 defined(CONFIG_CPU_SH7751R) || \
252 defined(CONFIG_CPU_SH7763) || \
253 defined(CONFIG_CPU_SH7780) || \
254 defined(CONFIG_CPU_SH7785) || \
255 defined(CONFIG_CPU_SH7786) || \
256 defined(CONFIG_CPU_SHX3)
257 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
258 #elif defined(CONFIG_CPU_SH7724)
259 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
260 #else
261 #define SCI_CTRL_FLAGS_REIE 0
262 #endif
263 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
264 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
265 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
266 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
267
268 /* SCxSR SCI */
269 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
270 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
271 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
272 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
273 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
274 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
275 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
276 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
277
278 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
279
280 /* SCxSR SCIF */
281 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
282 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
283 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
284 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
285 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
286 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
287 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
288 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
289
290 #if defined(CONFIG_CPU_SH7705) || \
291 defined(CONFIG_CPU_SH7720) || \
292 defined(CONFIG_CPU_SH7721) || \
293 defined(CONFIG_ARCH_SH7367) || \
294 defined(CONFIG_ARCH_SH7377) || \
295 defined(CONFIG_ARCH_SH7372) || \
296 defined(CONFIG_SH73A0) || \
297 defined(CONFIG_R8A7740)
298 # define SCIF_ORER 0x0200
299 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
300 # define SCIF_RFDC_MASK 0x007f
301 # define SCIF_TXROOM_MAX 64
302 #elif defined(CONFIG_CPU_SH7763)
303 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
304 # define SCIF_RFDC_MASK 0x007f
305 # define SCIF_TXROOM_MAX 64
306 /* SH7763 SCIF2 support */
307 # define SCIF2_RFDC_MASK 0x001f
308 # define SCIF2_TXROOM_MAX 16
309 #elif defined(CONFIG_RCAR_GEN2)
310 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
311 # if defined(CONFIG_SCIF_A)
312 # define SCIF_RFDC_MASK 0x007f
313 # else
314 # define SCIF_RFDC_MASK 0x001f
315 # endif
316 #else
317 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
318 # define SCIF_RFDC_MASK 0x001f
319 # define SCIF_TXROOM_MAX 16
320 #endif
321
322 #ifndef SCIF_ORER
323 #define SCIF_ORER 0x0000
324 #endif
325
326 #define SCxSR_TEND(port)\
327 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
328 #define SCxSR_ERRORS(port)\
329 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
330 #define SCxSR_RDxF(port)\
331 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
332 #define SCxSR_TDxE(port)\
333 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
334 #define SCxSR_FER(port)\
335 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
336 #define SCxSR_PER(port)\
337 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
338 #define SCxSR_BRK(port)\
339 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
340 #define SCxSR_ORER(port)\
341 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
342
343 #if defined(CONFIG_CPU_SH7705) || \
344 defined(CONFIG_CPU_SH7720) || \
345 defined(CONFIG_CPU_SH7721) || \
346 defined(CONFIG_ARCH_SH7367) || \
347 defined(CONFIG_ARCH_SH7377) || \
348 defined(CONFIG_ARCH_SH7372) || \
349 defined(CONFIG_SH73A0) || \
350 defined(CONFIG_R8A7740)
351 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
352 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
353 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
354 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
355 #else
356 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
357 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
358 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
359 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
360 #endif
361
362 /* SCFCR */
363 #define SCFCR_RFRST 0x0002
364 #define SCFCR_TFRST 0x0004
365 #define SCFCR_TCRST 0x4000
366 #define SCFCR_MCE 0x0008
367
368 #define SCI_MAJOR 204
369 #define SCI_MINOR_START 8
370
371 /* Generic serial flags */
372 #define SCI_RX_THROTTLE 0x0000001
373
374 #define SCI_MAGIC 0xbabeface
375
376 /*
377 * Events are used to schedule things to happen at timer-interrupt
378 * time, instead of at rs interrupt time.
379 */
380 #define SCI_EVENT_WRITE_WAKEUP 0
381
382 #define SCI_IN(size, offset)\
383 if ((size) == 8) {\
384 return readb(port->membase + (offset));\
385 } else {\
386 return readw(port->membase + (offset));\
387 }
388 #define SCI_OUT(size, offset, value)\
389 if ((size) == 8) {\
390 writeb(value, port->membase + (offset));\
391 } else if ((size) == 16) {\
392 writew(value, port->membase + (offset));\
393 }
394
395 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
396 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
397 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
398 SCI_IN(scif_size, scif_offset)\
399 } else { /* PORT_SCI or PORT_SCIFA */\
400 SCI_IN(sci_size, sci_offset);\
401 }\
402 }\
403 static inline void sci_##name##_out(struct uart_port *port,\
404 unsigned int value) {\
405 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
406 SCI_OUT(scif_size, scif_offset, value)\
407 } else { /* PORT_SCI or PORT_SCIFA */\
408 SCI_OUT(sci_size, sci_offset, value);\
409 }\
410 }
411
412 #ifdef CONFIG_H8300
413 /* h8300 don't have SCIF */
414 #define CPU_SCIF_FNS(name) \
415 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
416 return 0;\
417 }\
418 static inline void sci_##name##_out(struct uart_port *port,\
419 unsigned int value) {\
420 }
421 #else
422 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
423 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
424 SCI_IN(scif_size, scif_offset);\
425 }\
426 static inline void sci_##name##_out(struct uart_port *port,\
427 unsigned int value) {\
428 SCI_OUT(scif_size, scif_offset, value);\
429 }
430 #endif
431
432 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
433 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
434 SCI_IN(sci_size, sci_offset);\
435 }\
436 static inline void sci_##name##_out(struct uart_port *port,\
437 unsigned int value) {\
438 SCI_OUT(sci_size, sci_offset, value);\
439 }
440
441 #if defined(CONFIG_CPU_SH3) || \
442 defined(CONFIG_ARCH_SH7367) || \
443 defined(CONFIG_ARCH_SH7377) || \
444 defined(CONFIG_ARCH_SH7372) || \
445 defined(CONFIG_SH73A0) || \
446 defined(CONFIG_R8A7740)
447 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
448 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
449 sh4_sci_offset, sh4_sci_size, \
450 sh3_scif_offset, sh3_scif_size, \
451 sh4_scif_offset, sh4_scif_size, \
452 h8_sci_offset, h8_sci_size) \
453 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
454 sh4_scif_offset, sh4_scif_size)
455 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
456 sh4_scif_offset, sh4_scif_size) \
457 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
458 #elif defined(CONFIG_CPU_SH7705) || \
459 defined(CONFIG_CPU_SH7720) || \
460 defined(CONFIG_CPU_SH7721) || \
461 defined(CONFIG_ARCH_SH7367) || \
462 defined(CONFIG_ARCH_SH7377) || \
463 defined(CONFIG_SH73A0)
464 #define SCIF_FNS(name, scif_offset, scif_size) \
465 CPU_SCIF_FNS(name, scif_offset, scif_size)
466 #elif defined(CONFIG_ARCH_SH7372) || \
467 defined(CONFIG_R8A7740)
468 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
469 sh4_scifb_offset, sh4_scifb_size) \
470 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
471 sh4_scifb_offset, sh4_scifb_size)
472 #define SCIF_FNS(name, scif_offset, scif_size) \
473 CPU_SCIF_FNS(name, scif_offset, scif_size)
474 #else
475 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
476 sh4_sci_offset, sh4_sci_size, \
477 sh3_scif_offset, sh3_scif_size,\
478 sh4_scif_offset, sh4_scif_size, \
479 h8_sci_offset, h8_sci_size) \
480 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
481 sh3_scif_offset, sh3_scif_size)
482 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
483 sh4_scif_offset, sh4_scif_size) \
484 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
485 #endif
486 #elif defined(__H8300H__) || defined(__H8300S__)
487 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
488 sh4_sci_offset, sh4_sci_size, \
489 sh3_scif_offset, sh3_scif_size,\
490 sh4_scif_offset, sh4_scif_size, \
491 h8_sci_offset, h8_sci_size) \
492 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
493 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
494 sh4_scif_offset, sh4_scif_size) \
495 CPU_SCIF_FNS(name)
496 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
497 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
498 sh4_scif_offset, sh4_scif_size) \
499 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
500 sh4_scif_offset, sh4_scif_size)
501 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
502 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
503 #else
504 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
505 sh4_sci_offset, sh4_sci_size, \
506 sh3_scif_offset, sh3_scif_size,\
507 sh4_scif_offset, sh4_scif_size, \
508 h8_sci_offset, h8_sci_size) \
509 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
510 sh4_scif_offset, sh4_scif_size)
511 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
512 sh4_scif_offset, sh4_scif_size) \
513 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
514 #endif
515
516 #if defined(CONFIG_CPU_SH7705) || \
517 defined(CONFIG_CPU_SH7720) || \
518 defined(CONFIG_CPU_SH7721) || \
519 defined(CONFIG_ARCH_SH7367) || \
520 defined(CONFIG_ARCH_SH7377) || \
521 defined(CONFIG_SH73A0)
522
523 SCIF_FNS(SCSMR, 0x00, 16)
524 SCIF_FNS(SCBRR, 0x04, 8)
525 SCIF_FNS(SCSCR, 0x08, 16)
526 SCIF_FNS(SCTDSR, 0x0c, 8)
527 SCIF_FNS(SCFER, 0x10, 16)
528 SCIF_FNS(SCxSR, 0x14, 16)
529 SCIF_FNS(SCFCR, 0x18, 16)
530 SCIF_FNS(SCFDR, 0x1c, 16)
531 SCIF_FNS(SCxTDR, 0x20, 8)
532 SCIF_FNS(SCxRDR, 0x24, 8)
533 SCIF_FNS(SCLSR, 0x00, 0)
534 SCIF_FNS(DL, 0x00, 0) /* dummy */
535 #elif defined(CONFIG_ARCH_SH7372) || \
536 defined(CONFIG_R8A7740)
537 SCIF_FNS(SCSMR, 0x00, 16)
538 SCIF_FNS(SCBRR, 0x04, 8)
539 SCIF_FNS(SCSCR, 0x08, 16)
540 SCIF_FNS(SCTDSR, 0x0c, 16)
541 SCIF_FNS(SCFER, 0x10, 16)
542 SCIF_FNS(SCxSR, 0x14, 16)
543 SCIF_FNS(SCFCR, 0x18, 16)
544 SCIF_FNS(SCFDR, 0x1c, 16)
545 SCIF_FNS(SCTFDR, 0x38, 16)
546 SCIF_FNS(SCRFDR, 0x3c, 16)
547 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
548 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
549 SCIF_FNS(SCLSR, 0x00, 0)
550 SCIF_FNS(DL, 0x00, 0) /* dummy */
551 #elif defined(CONFIG_CPU_SH7723) ||\
552 defined(CONFIG_CPU_SH7724)
553 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
554 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
555 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
556 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
557 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
558 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
559 SCIx_FNS(SCSPTR, 0, 0, 0, 0)
560 SCIF_FNS(SCTDSR, 0x0c, 8)
561 SCIF_FNS(SCFER, 0x10, 16)
562 SCIF_FNS(SCFCR, 0x18, 16)
563 SCIF_FNS(SCFDR, 0x1c, 16)
564 SCIF_FNS(SCLSR, 0x24, 16)
565 SCIF_FNS(DL, 0x00, 0) /* dummy */
566 #elif defined(CONFIG_RCAR_GEN2)
567 /* SCIFA and SCIF register offsets and size */
568 SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
569 SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
570 SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
571 SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
572 SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
573 SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
574 SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
575 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
576 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
577 SCIF_FNS(DL, 0, 0, 0x30, 16)
578 SCIF_FNS(CKS, 0, 0, 0x34, 16)
579 #if defined(CONFIG_SCIF_A)
580 SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
581 #else
582 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
583 #endif
584 #else
585 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
586 /* name off sz off sz off sz off sz off sz*/
587 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
588 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
589 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
590 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
591 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
592 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
593 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
594 #if defined(CONFIG_CPU_SH7760) || \
595 defined(CONFIG_CPU_SH7780) || \
596 defined(CONFIG_CPU_SH7785) || \
597 defined(CONFIG_CPU_SH7786)
598 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
599 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
600 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
601 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
602 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
603 #elif defined(CONFIG_CPU_SH7763)
604 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
605 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
606 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
607 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
608 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
609 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
610 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
611 #else
612
613 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
614 #if defined(CONFIG_CPU_SH7722)
615 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
616 #else
617 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
618 #endif
619 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
620 #endif
621 SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
622 #endif
623 #define sci_in(port, reg) sci_##reg##_in(port)
624 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
625
626 /* H8/300 series SCI pins assignment */
627 #if defined(__H8300H__) || defined(__H8300S__)
628 static const struct __attribute__((packed)) {
629 int port; /* GPIO port no */
630 unsigned short rx, tx; /* GPIO bit no */
631 } h8300_sci_pins[] = {
632 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
633 { /* SCI0 */
634 .port = H8300_GPIO_P9,
635 .rx = H8300_GPIO_B2,
636 .tx = H8300_GPIO_B0,
637 },
638 { /* SCI1 */
639 .port = H8300_GPIO_P9,
640 .rx = H8300_GPIO_B3,
641 .tx = H8300_GPIO_B1,
642 },
643 { /* SCI2 */
644 .port = H8300_GPIO_PB,
645 .rx = H8300_GPIO_B7,
646 .tx = H8300_GPIO_B6,
647 }
648 #elif defined(CONFIG_H8S2678)
649 { /* SCI0 */
650 .port = H8300_GPIO_P3,
651 .rx = H8300_GPIO_B2,
652 .tx = H8300_GPIO_B0,
653 },
654 { /* SCI1 */
655 .port = H8300_GPIO_P3,
656 .rx = H8300_GPIO_B3,
657 .tx = H8300_GPIO_B1,
658 },
659 { /* SCI2 */
660 .port = H8300_GPIO_P5,
661 .rx = H8300_GPIO_B1,
662 .tx = H8300_GPIO_B0,
663 }
664 #endif
665 };
666 #endif
667
668 #if defined(CONFIG_CPU_SH7706) || \
669 defined(CONFIG_CPU_SH7707) || \
670 defined(CONFIG_CPU_SH7708) || \
671 defined(CONFIG_CPU_SH7709)
672 static inline int sci_rxd_in(struct uart_port *port)
673 {
674 if (port->mapbase == 0xfffffe80)
675 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
676 return 1;
677 }
678 #elif defined(CONFIG_CPU_SH7750) || \
679 defined(CONFIG_CPU_SH7751) || \
680 defined(CONFIG_CPU_SH7751R) || \
681 defined(CONFIG_CPU_SH7750R) || \
682 defined(CONFIG_CPU_SH7750S) || \
683 defined(CONFIG_CPU_SH7091)
684 static inline int sci_rxd_in(struct uart_port *port)
685 {
686 if (port->mapbase == 0xffe00000)
687 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
688 return 1;
689 }
690 #elif defined(__H8300H__) || defined(__H8300S__)
691 static inline int sci_rxd_in(struct uart_port *port)
692 {
693 int ch = (port->mapbase - SMR0) >> 3;
694 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
695 }
696 #else /* default case for non-SCI processors */
697 static inline int sci_rxd_in(struct uart_port *port)
698 {
699 return 1;
700 }
701 #endif
702
703 /*
704 * Values for the BitRate Register (SCBRR)
705 *
706 * The values are actually divisors for a frequency which can
707 * be internal to the SH3 (14.7456MHz) or derived from an external
708 * clock source. This driver assumes the internal clock is used;
709 * to support using an external clock source, config options or
710 * possibly command-line options would need to be added.
711 *
712 * Also, to support speeds below 2400 (why?) the lower 2 bits of
713 * the SCSMR register would also need to be set to non-zero values.
714 *
715 * -- Greg Banks 27Feb2000
716 *
717 * Answer: The SCBRR register is only eight bits, and the value in
718 * it gets larger with lower baud rates. At around 2400 (depending on
719 * the peripherial module clock) you run out of bits. However the
720 * lower two bits of SCSMR allow the module clock to be divided down,
721 * scaling the value which is needed in SCBRR.
722 *
723 * -- Stuart Menefy - 23 May 2000
724 *
725 * I meant, why would anyone bother with bitrates below 2400.
726 *
727 * -- Greg Banks - 7Jul2000
728 *
729 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
730 * tape reader as a console!
731 *
732 * -- Mitch Davis - 15 Jul 2000
733 */
734
735 #if (defined(CONFIG_CPU_SH7780) || \
736 defined(CONFIG_CPU_SH7785) || \
737 defined(CONFIG_CPU_SH7786)) && \
738 !defined(CONFIG_SH_SH2007)
739 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
740 #elif defined(CONFIG_CPU_SH7705) || \
741 defined(CONFIG_CPU_SH7720) || \
742 defined(CONFIG_CPU_SH7721) || \
743 defined(CONFIG_ARCH_SH7367) || \
744 defined(CONFIG_ARCH_SH7377) || \
745 defined(CONFIG_ARCH_SH7372) || \
746 defined(CONFIG_SH73A0) || \
747 defined(CONFIG_R8A7740)
748 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
749 #elif defined(CONFIG_CPU_SH7723) ||\
750 defined(CONFIG_CPU_SH7724)
751 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
752 {
753 if (port->type == PORT_SCIF)
754 return (clk+16*bps)/(32*bps)-1;
755 else
756 return ((clk*2)+16*bps)/(16*bps)-1;
757 }
758 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
759 #elif defined(__H8300H__) || defined(__H8300S__)
760 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
761 #elif defined(CONFIG_RCAR_GEN2)
762 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
763 #if defined(CONFIG_SCIF_A)
764 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
765 #else
766 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
767 #endif
768 #else /* Generic SH */
769 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
770 #endif
771
772 #ifndef DL_VALUE
773 #define DL_VALUE(bps, clk) 0
774 #endif
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