drivers/serial/serial_sh.h

   1 /*
   2  * Copy and modify from linux/drivers/serial/sh-sci.h
   3  */
   4
   5 #include <dm/platform_data/serial_sh.h>
   6
   7 struct uart_port {
   8         unsigned long   iobase;         /* in/out[bwl] */
   9         unsigned char   *membase;       /* read/write[bwl] */
  10         unsigned long   mapbase;        /* for ioremap */
  11         enum sh_serial_type type;       /* port type */
  12         enum sh_clk_mode clk_mode;      /* clock mode */
  13 };
  14
  15 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  16 #include <asm/regs306x.h>
  17 #endif
  18 #if defined(CONFIG_H8S2678)
  19 #include <asm/regs267x.h>
  20 #endif
  21
  22 #if defined(CONFIG_CPU_SH7706) || \
  23         defined(CONFIG_CPU_SH7707) || \
  24         defined(CONFIG_CPU_SH7708) || \
  25         defined(CONFIG_CPU_SH7709)
  26 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  27 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  28 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  29 #elif defined(CONFIG_CPU_SH7705)
  30 # define SCIF0          0xA4400000
  31 # define SCIF2          0xA4410000
  32 # define SCSMR_Ir       0xA44A0000
  33 # define IRDA_SCIF      SCIF0
  34 # define SCPCR 0xA4000116
  35 # define SCPDR 0xA4000136
  36
  37 /* Set the clock source,
  38  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  39  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  40  */
  41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  42 #elif defined(CONFIG_CPU_SH7720) || \
  43         defined(CONFIG_CPU_SH7721) || \
  44         defined(CONFIG_ARCH_SH7367) || \
  45         defined(CONFIG_ARCH_SH7377) || \
  46         defined(CONFIG_ARCH_SH7372) || \
  47         defined(CONFIG_SH73A0) || \
  48         defined(CONFIG_R8A7740)
  49 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  50 # define PORT_PTCR         0xA405011EUL
  51 # define PORT_PVCR         0xA4050122UL
  52 # define SCIF_ORER         0x0200   /* overrun error bit */
  53 #elif defined(CONFIG_SH_RTS7751R2D)
  54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
  55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  56 # define SCIF_ORER 0x0001   /* overrun error bit */
  57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  58 #elif defined(CONFIG_CPU_SH7750)  || \
  59         defined(CONFIG_CPU_SH7750R) || \
  60         defined(CONFIG_CPU_SH7750S) || \
  61         defined(CONFIG_CPU_SH7091)  || \
  62         defined(CONFIG_CPU_SH7751)  || \
  63         defined(CONFIG_CPU_SH7751R)
  64 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  66 # define SCIF_ORER 0x0001   /* overrun error bit */
  67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  68         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  69         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
  70 #elif defined(CONFIG_CPU_SH7760)
  71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  74 # define SCIF_ORER 0x0001  /* overrun error bit */
  75 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
  77 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  78 # define SCIF_ORER 0x0001   /* overrun error bit */
  79 # define PACR 0xa4050100
  80 # define PBCR 0xa4050102
  81 # define SCSCR_INIT(port)          0x3B
  82 #elif defined(CONFIG_CPU_SH7343)
  83 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  84 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  85 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  86 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  87 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  88 #elif defined(CONFIG_CPU_SH7722)
  89 # define PADR                   0xA4050120
  90 # undef PSDR
  91 # define PSDR                   0xA405013e
  92 # define PWDR                   0xA4050166
  93 # define PSCR                   0xA405011E
  94 # define SCIF_ORER              0x0001  /* overrun error bit */
  95 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  96 #elif defined(CONFIG_CPU_SH7366)
  97 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  98 # define SCSPTR0                SCPDR0
  99 # define SCIF_ORER              0x0001  /* overrun error bit */
 100 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 101 #elif defined(CONFIG_CPU_SH7723)
 102 # define SCSPTR0                0xa4050160
 103 # define SCSPTR1                0xa405013e
 104 # define SCSPTR2                0xa4050160
 105 # define SCSPTR3                0xa405013e
 106 # define SCSPTR4                0xa4050128
 107 # define SCSPTR5                0xa4050128
 108 # define SCIF_ORER              0x0001  /* overrun error bit */
 109 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 110 #elif defined(CONFIG_CPU_SH7734)
 111 # define SCSPTR0 0xFFE40020
 112 # define SCSPTR1 0xFFE41020
 113 # define SCSPTR2 0xFFE42020
 114 # define SCSPTR3 0xFFE43020
 115 # define SCSPTR4 0xFFE44020
 116 # define SCSPTR5 0xFFE45020
 117 # define SCIF_ORER 0x0001  /* overrun error bit */
 118 # define SCSCR_INIT(port) 0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 119 #elif defined(CONFIG_CPU_SH4_202)
 120 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 121 # define SCIF_ORER 0x0001   /* overrun error bit */
 122 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 123 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
 124 # define SCIF_BASE_ADDR    0x01030000
 125 # define SCIF_ADDR_SH5     (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
 126 # define SCIF_PTR2_OFFS    0x0000020
 127 # define SCIF_LSR2_OFFS    0x0000024
 128 # define SCSPTR\
 129                 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 130 # define SCLSR2\
 131                 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 132 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 133 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 134 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 135 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
 136 #elif defined(CONFIG_H8S2678)
 137 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 138 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
 139 #elif defined(CONFIG_CPU_SH7757) || \
 140         defined(CONFIG_CPU_SH7752) || \
 141         defined(CONFIG_CPU_SH7753)
 142 # define SCSPTR0 0xfe4b0020
 143 # define SCSPTR1 0xfe4b0020
 144 # define SCSPTR2 0xfe4b0020
 145 # define SCIF_ORER 0x0001
 146 # define SCSCR_INIT(port)       0x38
 147 # define SCIF_ONLY
 148 #elif defined(CONFIG_CPU_SH7763)
 149 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 150 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 151 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 152 # define SCIF_ORER 0x0001  /* overrun error bit */
 153 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 154 #elif defined(CONFIG_CPU_SH7770)
 155 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 156 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 157 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 158 # define SCIF_ORER 0x0001  /* overrun error bit */
 159 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 160 #elif defined(CONFIG_CPU_SH7780)
 161 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 162 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 163 # define SCIF_ORER      0x0001          /* Overrun error bit */
 164
 165 #if defined(CONFIG_SH_SH2007)
 166 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
 167 # define SCSCR_INIT(port)       0x38
 168 #else
 169 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
 170 # define SCSCR_INIT(port)       0x3a
 171 #endif
 172
 173 #elif defined(CONFIG_CPU_SH7785) || \
 174         defined(CONFIG_CPU_SH7786)
 175 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 176 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 177 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 178 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 179 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 180 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 181 # define SCIF_ORER      0x0001          /* Overrun error bit */
 182 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 183 #elif defined(CONFIG_CPU_SH7201) || \
 184         defined(CONFIG_CPU_SH7203) || \
 185         defined(CONFIG_CPU_SH7206) || \
 186         defined(CONFIG_CPU_SH7263) || \
 187         defined(CONFIG_CPU_SH7264)
 188 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 189 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 190 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 191 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 192 # if defined(CONFIG_CPU_SH7201)
 193 #  define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
 194 #  define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
 195 #  define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
 196 #  define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
 197 # endif
 198 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 199 #elif defined(CONFIG_CPU_SH7269)
 200 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
 201 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
 202 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
 203 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
 204 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
 205 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
 206 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
 207 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
 208 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 209 #elif defined(CONFIG_CPU_SH7619)
 210 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 211 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 212 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 213 # define SCIF_ORER 0x0001  /* overrun error bit */
 214 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 215 #elif defined(CONFIG_CPU_SHX3)
 216 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 217 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 218 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 219 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 220 # define SCIF_ORER 0x0001               /* Overrun error bit */
 221 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 222 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
 223       defined(CONFIG_R7S72100)
 224 # if defined(CONFIG_SCIF_A)
 225 #  define SCIF_ORER     0x0200
 226 # else
 227 #  define SCIF_ORER     0x0001
 228 # endif
 229 # define SCSCR_INIT(port)       (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
 230                                 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 231 #else
 232 # error CPU subtype not defined
 233 #endif
 234
 235 /* SCSCR */
 236 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 237 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 238 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 239 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 240 #if defined(CONFIG_CPU_SH7750)  || \
 241         defined(CONFIG_CPU_SH7091)  || \
 242         defined(CONFIG_CPU_SH7750R) || \
 243         defined(CONFIG_CPU_SH7722)  || \
 244         defined(CONFIG_CPU_SH7734)  || \
 245         defined(CONFIG_CPU_SH7750S) || \
 246         defined(CONFIG_CPU_SH7751)  || \
 247         defined(CONFIG_CPU_SH7751R) || \
 248         defined(CONFIG_CPU_SH7763)  || \
 249         defined(CONFIG_CPU_SH7780)  || \
 250         defined(CONFIG_CPU_SH7785)  || \
 251         defined(CONFIG_CPU_SH7786)  || \
 252         defined(CONFIG_CPU_SHX3)
 253 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 254 #else
 255 #define SCI_CTRL_FLAGS_REIE 0
 256 #endif
 257 /*              SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 258 /*              SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 259 /*              SCI_CTRL_FLAGS_CKE1 0x02  * all */
 260 /*              SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 261
 262 /* SCxSR SCI */
 263 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 264 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 265 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 266 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 267 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 268 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 269 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 270 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 271
 272 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 273
 274 /* SCxSR SCIF */
 275 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 276 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 277 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 278 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 279 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 280 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 281 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 282 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 283
 284 #if defined(CONFIG_CPU_SH7705) || \
 285         defined(CONFIG_CPU_SH7720) || \
 286         defined(CONFIG_CPU_SH7721) || \
 287         defined(CONFIG_ARCH_SH7367) || \
 288         defined(CONFIG_ARCH_SH7377) || \
 289         defined(CONFIG_ARCH_SH7372) || \
 290         defined(CONFIG_SH73A0) || \
 291         defined(CONFIG_R8A7740)
 292 # define SCIF_ORER    0x0200
 293 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 294 # define SCIF_RFDC_MASK 0x007f
 295 # define SCIF_TXROOM_MAX 64
 296 #elif defined(CONFIG_CPU_SH7763)
 297 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 298 # define SCIF_RFDC_MASK 0x007f
 299 # define SCIF_TXROOM_MAX 64
 300 /* SH7763 SCIF2 support */
 301 # define SCIF2_RFDC_MASK 0x001f
 302 # define SCIF2_TXROOM_MAX 16
 303 #elif defined(CONFIG_RCAR_GEN2)
 304 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 305 # if defined(CONFIG_SCIF_A)
 306 #  define SCIF_RFDC_MASK        0x007f
 307 # else
 308 #  define SCIF_RFDC_MASK        0x001f
 309 # endif
 310 #else
 311 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 312 # define SCIF_RFDC_MASK 0x001f
 313 # define SCIF_TXROOM_MAX 16
 314 #endif
 315
 316 #ifndef SCIF_ORER
 317 #define SCIF_ORER       0x0000
 318 #endif
 319
 320 #define SCxSR_TEND(port)\
 321                 (((port)->type == PORT_SCI) ? SCI_TEND  : SCIF_TEND)
 322 #define SCxSR_ERRORS(port)\
 323                 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 324 #define SCxSR_RDxF(port)\
 325                 (((port)->type == PORT_SCI) ? SCI_RDRF  : SCIF_RDF)
 326 #define SCxSR_TDxE(port)\
 327                 (((port)->type == PORT_SCI) ? SCI_TDRE  : SCIF_TDFE)
 328 #define SCxSR_FER(port)\
 329                 (((port)->type == PORT_SCI) ? SCI_FER   : SCIF_FER)
 330 #define SCxSR_PER(port)\
 331                 (((port)->type == PORT_SCI) ? SCI_PER   : SCIF_PER)
 332 #define SCxSR_BRK(port)\
 333                 ((port)->type == PORT_SCI) ? 0x00               : SCIF_BRK)
 334 #define SCxSR_ORER(port)\
 335                 (((port)->type == PORT_SCI) ? SCI_ORER  : SCIF_ORER)
 336
 337 #if defined(CONFIG_CPU_SH7705) || \
 338         defined(CONFIG_CPU_SH7720) || \
 339         defined(CONFIG_CPU_SH7721) || \
 340         defined(CONFIG_ARCH_SH7367) || \
 341         defined(CONFIG_ARCH_SH7377) || \
 342         defined(CONFIG_ARCH_SH7372) || \
 343         defined(CONFIG_SH73A0) || \
 344         defined(CONFIG_R8A7740)
 345 # define SCxSR_RDxF_CLEAR(port)  (sci_in(port, SCxSR) & 0xfffc)
 346 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 347 # define SCxSR_TDxE_CLEAR(port)  (sci_in(port, SCxSR) & 0xffdf)
 348 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
 349 #else
 350 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 351 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 352 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 353 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 354 #endif
 355
 356 /* SCFCR */
 357 #define SCFCR_RFRST 0x0002
 358 #define SCFCR_TFRST 0x0004
 359 #define SCFCR_TCRST 0x4000
 360 #define SCFCR_MCE   0x0008
 361
 362 #define SCI_MAJOR               204
 363 #define SCI_MINOR_START         8
 364
 365 /* Generic serial flags */
 366 #define SCI_RX_THROTTLE         0x0000001
 367
 368 #define SCI_MAGIC 0xbabeface
 369
 370 /*
 371  * Events are used to schedule things to happen at timer-interrupt
 372  * time, instead of at rs interrupt time.
 373  */
 374 #define SCI_EVENT_WRITE_WAKEUP  0
 375
 376 #define SCI_IN(size, offset)\
 377         if ((size) == 8) {\
 378                 return readb(port->membase + (offset));\
 379         } else {\
 380                 return readw(port->membase + (offset));\
 381         }
 382 #define SCI_OUT(size, offset, value)\
 383         if ((size) == 8) {\
 384                 writeb(value, port->membase + (offset));\
 385         } else if ((size) == 16) {\
 386                 writew(value, port->membase + (offset));\
 387         }
 388
 389 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 390         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 391                 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
 392                         SCI_IN(scif_size, scif_offset)\
 393                 } else { /* PORT_SCI or PORT_SCIFA */\
 394                         SCI_IN(sci_size, sci_offset);\
 395                 }\
 396         }\
 397 static inline void sci_##name##_out(struct uart_port *port,\
 398                                 unsigned int value) {\
 399         if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
 400                 SCI_OUT(scif_size, scif_offset, value)\
 401         } else {        /* PORT_SCI or PORT_SCIFA */\
 402                 SCI_OUT(sci_size, sci_offset, value);\
 403         }\
 404 }
 405
 406 #ifdef CONFIG_H8300
 407 /* h8300 don't have SCIF */
 408 #define CPU_SCIF_FNS(name)                                              \
 409         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 410                 return 0;\
 411         }\
 412         static inline void sci_##name##_out(struct uart_port *port,\
 413                                         unsigned int value) {\
 414         }
 415 #else
 416 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                      \
 417         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 418                 SCI_IN(scif_size, scif_offset);\
 419         }\
 420         static inline void sci_##name##_out(struct uart_port *port,\
 421                                         unsigned int value) {\
 422                 SCI_OUT(scif_size, scif_offset, value);\
 423         }
 424 #endif
 425
 426 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
 427         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 428                 SCI_IN(sci_size, sci_offset);\
 429         }\
 430         static inline void sci_##name##_out(struct uart_port *port,\
 431                                         unsigned int value) {\
 432                 SCI_OUT(sci_size, sci_offset, value);\
 433         }
 434
 435 #if defined(CONFIG_CPU_SH3) || \
 436         defined(CONFIG_ARCH_SH7367) || \
 437         defined(CONFIG_ARCH_SH7377) || \
 438         defined(CONFIG_ARCH_SH7372) || \
 439         defined(CONFIG_SH73A0) || \
 440         defined(CONFIG_R8A7740)
 441 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
 442 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 443                                 sh4_sci_offset, sh4_sci_size, \
 444                                 sh3_scif_offset, sh3_scif_size, \
 445                                 sh4_scif_offset, sh4_scif_size, \
 446                                 h8_sci_offset, h8_sci_size) \
 447         CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
 448                                 sh4_scif_offset, sh4_scif_size)
 449 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
 450                                 sh4_scif_offset, sh4_scif_size) \
 451         CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 452 #elif defined(CONFIG_CPU_SH7705) || \
 453         defined(CONFIG_CPU_SH7720) || \
 454         defined(CONFIG_CPU_SH7721) || \
 455         defined(CONFIG_ARCH_SH7367) || \
 456         defined(CONFIG_ARCH_SH7377) || \
 457         defined(CONFIG_SH73A0)
 458 #define SCIF_FNS(name, scif_offset, scif_size) \
 459         CPU_SCIF_FNS(name, scif_offset, scif_size)
 460 #elif defined(CONFIG_ARCH_SH7372) || \
 461         defined(CONFIG_R8A7740)
 462 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 463                                 sh4_scifb_offset, sh4_scifb_size) \
 464         CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 465                                 sh4_scifb_offset, sh4_scifb_size)
 466 #define SCIF_FNS(name, scif_offset, scif_size) \
 467         CPU_SCIF_FNS(name, scif_offset, scif_size)
 468 #else
 469 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 470                                 sh4_sci_offset, sh4_sci_size, \
 471                                 sh3_scif_offset, sh3_scif_size,\
 472                                 sh4_scif_offset, sh4_scif_size, \
 473                                 h8_sci_offset, h8_sci_size) \
 474         CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 475                                 sh3_scif_offset, sh3_scif_size)
 476 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
 477                                 sh4_scif_offset, sh4_scif_size) \
 478         CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 479 #endif
 480 #elif defined(__H8300H__) || defined(__H8300S__)
 481 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 482                                 sh4_sci_offset, sh4_sci_size, \
 483                                 sh3_scif_offset, sh3_scif_size,\
 484                                 sh4_scif_offset, sh4_scif_size, \
 485                                 h8_sci_offset, h8_sci_size) \
 486         CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 487 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
 488                                         sh4_scif_offset, sh4_scif_size) \
 489         CPU_SCIF_FNS(name)
 490 #elif defined(CONFIG_CPU_SH7723)
 491                 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 492                                         sh4_scif_offset, sh4_scif_size) \
 493                         CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 494                                         sh4_scif_offset, sh4_scif_size)
 495                 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
 496                         CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 497 #else
 498 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 499                                 sh4_sci_offset, sh4_sci_size, \
 500                                 sh3_scif_offset, sh3_scif_size,\
 501                                 sh4_scif_offset, sh4_scif_size, \
 502                                 h8_sci_offset, h8_sci_size) \
 503         CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
 504                                         sh4_scif_offset, sh4_scif_size)
 505 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
 506                                 sh4_scif_offset, sh4_scif_size) \
 507         CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 508 #endif
 509
 510 #if defined(CONFIG_CPU_SH7705) || \
 511         defined(CONFIG_CPU_SH7720) || \
 512         defined(CONFIG_CPU_SH7721) || \
 513         defined(CONFIG_ARCH_SH7367) || \
 514         defined(CONFIG_ARCH_SH7377) || \
 515         defined(CONFIG_SH73A0)
 516
 517 SCIF_FNS(SCSMR,  0x00, 16)
 518 SCIF_FNS(SCBRR,  0x04,  8)
 519 SCIF_FNS(SCSCR,  0x08, 16)
 520 SCIF_FNS(SCTDSR, 0x0c,  8)
 521 SCIF_FNS(SCFER,  0x10, 16)
 522 SCIF_FNS(SCxSR,  0x14, 16)
 523 SCIF_FNS(SCFCR,  0x18, 16)
 524 SCIF_FNS(SCFDR,  0x1c, 16)
 525 SCIF_FNS(SCxTDR, 0x20,  8)
 526 SCIF_FNS(SCxRDR, 0x24,  8)
 527 SCIF_FNS(SCLSR,  0x00,  0)
 528 SCIF_FNS(DL,     0x00,  0) /* dummy */
 529 #elif defined(CONFIG_ARCH_SH7372) || \
 530         defined(CONFIG_R8A7740)
 531 SCIF_FNS(SCSMR,  0x00, 16)
 532 SCIF_FNS(SCBRR,  0x04,  8)
 533 SCIF_FNS(SCSCR,  0x08, 16)
 534 SCIF_FNS(SCTDSR, 0x0c, 16)
 535 SCIF_FNS(SCFER,  0x10, 16)
 536 SCIF_FNS(SCxSR,  0x14, 16)
 537 SCIF_FNS(SCFCR,  0x18, 16)
 538 SCIF_FNS(SCFDR,  0x1c, 16)
 539 SCIF_FNS(SCTFDR, 0x38, 16)
 540 SCIF_FNS(SCRFDR, 0x3c, 16)
 541 SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
 542 SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
 543 SCIF_FNS(SCLSR,  0x00,  0)
 544 SCIF_FNS(DL,     0x00,  0) /* dummy */
 545 #elif defined(CONFIG_CPU_SH7723)
 546 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 547 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 548 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
 549 SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
 550 SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
 551 SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
 552 SCIx_FNS(SCSPTR, 0,     0,    0,  0)
 553 SCIF_FNS(SCTDSR, 0x0c,  8)
 554 SCIF_FNS(SCFER,  0x10, 16)
 555 SCIF_FNS(SCFCR,  0x18, 16)
 556 SCIF_FNS(SCFDR,  0x1c, 16)
 557 SCIF_FNS(SCLSR,  0x24, 16)
 558 SCIF_FNS(DL,     0x00,  0) /* dummy */
 559 #elif defined(CONFIG_RCAR_GEN2)
 560 /* SCIFA and SCIF register offsets and size */
 561 SCIx_FNS(SCSMR,  0,  0, 0x00, 16, 0,  0, 0x00, 16, 0,  0)
 562 SCIx_FNS(SCBRR,  0,  0, 0x04,  8, 0,  0, 0x04,  8, 0,  0)
 563 SCIx_FNS(SCSCR,  0,  0, 0x08, 16, 0,  0, 0x08, 16, 0,  0)
 564 SCIx_FNS(SCxTDR, 0,  0, 0x20,  8, 0,  0, 0x0C,  8, 0,  0)
 565 SCIx_FNS(SCxSR,  0,  0, 0x14, 16, 0,  0, 0x10, 16, 0,  0)
 566 SCIx_FNS(SCxRDR, 0,  0, 0x24,  8, 0,  0, 0x14,  8, 0,  0)
 567 SCIF_FNS(SCFCR,  0,  0, 0x18, 16)
 568 SCIF_FNS(SCFDR,  0,  0, 0x1C, 16)
 569 SCIF_FNS(SCSPTR, 0,  0, 0x20, 16)
 570 SCIF_FNS(DL,     0,  0, 0x30, 16)
 571 SCIF_FNS(CKS,    0,  0, 0x34, 16)
 572 #if defined(CONFIG_SCIF_A)
 573 SCIF_FNS(SCLSR,  0,  0, 0x14, 16)
 574 #else
 575 SCIF_FNS(SCLSR,  0,  0, 0x24, 16)
 576 #endif
 577 #else
 578 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 579 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 580 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 581 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 582 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 583 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 584 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 585 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 586 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 587 #if defined(CONFIG_CPU_SH7760) || \
 588         defined(CONFIG_CPU_SH7780) || \
 589         defined(CONFIG_CPU_SH7785) || \
 590         defined(CONFIG_CPU_SH7786)
 591 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 592 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 593 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 594 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 595 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 596 #elif defined(CONFIG_CPU_SH7763)
 597 SCIF_FNS(SCFDR,                         0,  0, 0x1C, 16)
 598 SCIF_FNS(SCSPTR2,                       0,  0, 0x20, 16)
 599 SCIF_FNS(SCLSR2,                        0,  0, 0x24, 16)
 600 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 601 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 602 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 603 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 604 #else
 605
 606 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 607 #if defined(CONFIG_CPU_SH7722)
 608 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 609 #else
 610 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 611 #endif
 612 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 613 #endif
 614 SCIF_FNS(DL,                            0,  0, 0x0,  0) /* dummy */
 615 #endif
 616 #define sci_in(port, reg) sci_##reg##_in(port)
 617 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 618
 619 /* H8/300 series SCI pins assignment */
 620 #if defined(__H8300H__) || defined(__H8300S__)
 621 static const struct __attribute__((packed)) {
 622         int port;             /* GPIO port no */
 623         unsigned short rx, tx; /* GPIO bit no */
 624 } h8300_sci_pins[] = {
 625 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 626         {    /* SCI0 */
 627                 .port = H8300_GPIO_P9,
 628                 .rx   = H8300_GPIO_B2,
 629                 .tx   = H8300_GPIO_B0,
 630         },
 631         {    /* SCI1 */
 632                 .port = H8300_GPIO_P9,
 633                 .rx   = H8300_GPIO_B3,
 634                 .tx   = H8300_GPIO_B1,
 635         },
 636         {    /* SCI2 */
 637                 .port = H8300_GPIO_PB,
 638                 .rx   = H8300_GPIO_B7,
 639                 .tx   = H8300_GPIO_B6,
 640         }
 641 #elif defined(CONFIG_H8S2678)
 642         {    /* SCI0 */
 643                 .port = H8300_GPIO_P3,
 644                 .rx   = H8300_GPIO_B2,
 645                 .tx   = H8300_GPIO_B0,
 646         },
 647         {    /* SCI1 */
 648                 .port = H8300_GPIO_P3,
 649                 .rx   = H8300_GPIO_B3,
 650                 .tx   = H8300_GPIO_B1,
 651         },
 652         {    /* SCI2 */
 653                 .port = H8300_GPIO_P5,
 654                 .rx   = H8300_GPIO_B1,
 655                 .tx   = H8300_GPIO_B0,
 656         }
 657 #endif
 658 };
 659 #endif
 660
 661 #if defined(CONFIG_CPU_SH7706) || \
 662         defined(CONFIG_CPU_SH7707) || \
 663         defined(CONFIG_CPU_SH7708) || \
 664         defined(CONFIG_CPU_SH7709)
 665 static inline int sci_rxd_in(struct uart_port *port)
 666 {
 667         if (port->mapbase == 0xfffffe80)
 668                 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 669         return 1;
 670 }
 671 #elif defined(CONFIG_CPU_SH7750)  || \
 672         defined(CONFIG_CPU_SH7751)  || \
 673         defined(CONFIG_CPU_SH7751R) || \
 674         defined(CONFIG_CPU_SH7750R) || \
 675         defined(CONFIG_CPU_SH7750S) || \
 676         defined(CONFIG_CPU_SH7091)
 677 static inline int sci_rxd_in(struct uart_port *port)
 678 {
 679         if (port->mapbase == 0xffe00000)
 680                 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 681         return 1;
 682 }
 683 #elif defined(__H8300H__) || defined(__H8300S__)
 684 static inline int sci_rxd_in(struct uart_port *port)
 685 {
 686         int ch = (port->mapbase - SMR0) >> 3;
 687         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 688 }
 689 #else /* default case for non-SCI processors */
 690 static inline int sci_rxd_in(struct uart_port *port)
 691 {
 692         return 1;
 693 }
 694 #endif
 695
 696 /*
 697  * Values for the BitRate Register (SCBRR)
 698  *
 699  * The values are actually divisors for a frequency which can
 700  * be internal to the SH3 (14.7456MHz) or derived from an external
 701  * clock source.  This driver assumes the internal clock is used;
 702  * to support using an external clock source, config options or
 703  * possibly command-line options would need to be added.
 704  *
 705  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 706  * the SCSMR register would also need to be set to non-zero values.
 707  *
 708  * -- Greg Banks 27Feb2000
 709  *
 710  * Answer: The SCBRR register is only eight bits, and the value in
 711  * it gets larger with lower baud rates. At around 2400 (depending on
 712  * the peripherial module clock) you run out of bits. However the
 713  * lower two bits of SCSMR allow the module clock to be divided down,
 714  * scaling the value which is needed in SCBRR.
 715  *
 716  * -- Stuart Menefy - 23 May 2000
 717  *
 718  * I meant, why would anyone bother with bitrates below 2400.
 719  *
 720  * -- Greg Banks - 7Jul2000
 721  *
 722  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 723  * tape reader as a console!
 724  *
 725  * -- Mitch Davis - 15 Jul 2000
 726  */
 727
 728 #if (defined(CONFIG_CPU_SH7780)  || \
 729         defined(CONFIG_CPU_SH7785)  || \
 730         defined(CONFIG_CPU_SH7786)) && \
 731         !defined(CONFIG_SH_SH2007)
 732 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 733 #elif defined(CONFIG_CPU_SH7705) || \
 734         defined(CONFIG_CPU_SH7720) || \
 735         defined(CONFIG_CPU_SH7721) || \
 736         defined(CONFIG_ARCH_SH7367) || \
 737         defined(CONFIG_ARCH_SH7377) || \
 738         defined(CONFIG_ARCH_SH7372) || \
 739         defined(CONFIG_SH73A0) || \
 740         defined(CONFIG_R8A7740)
 741 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 742 #elif defined(CONFIG_CPU_SH7723)
 743 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 744 {
 745         if (port->type == PORT_SCIF)
 746                 return (clk+16*bps)/(32*bps)-1;
 747         else
 748                 return ((clk*2)+16*bps)/(16*bps)-1;
 749 }
 750 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 751 #elif defined(__H8300H__) || defined(__H8300S__)
 752 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 753 #elif defined(CONFIG_RCAR_GEN2)
 754 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
 755  #if defined(CONFIG_SCIF_A)
 756   #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
 757  #else
 758   #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
 759  #endif
 760 #else /* Generic SH */
 761 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 762 #endif
 763
 764 #ifndef DL_VALUE
 765 #define DL_VALUE(bps, clk) 0
 766 #endif