drivers/serial/serial_sh.h

   1 /*
   2  * Copy and modify from linux/drivers/serial/sh-sci.h
   3  */
   4
   5 struct uart_port {
   6         unsigned long   iobase;         /* in/out[bwl] */
   7         unsigned char   *membase;       /* read/write[bwl] */
   8         unsigned long   mapbase;        /* for ioremap */
   9         unsigned int    type;           /* port type */
  10 };
  11
  12 #define PORT_SCI        52
  13 #define PORT_SCIF       53
  14 #define PORT_SCIFA      83
  15 #define PORT_SCIFB      93
  16
  17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  18 #include <asm/regs306x.h>
  19 #endif
  20 #if defined(CONFIG_H8S2678)
  21 #include <asm/regs267x.h>
  22 #endif
  23
  24 #if defined(CONFIG_CPU_SH7706) || \
  25         defined(CONFIG_CPU_SH7707) || \
  26         defined(CONFIG_CPU_SH7708) || \
  27         defined(CONFIG_CPU_SH7709)
  28 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  29 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  30 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  31 #elif defined(CONFIG_CPU_SH7705)
  32 # define SCIF0          0xA4400000
  33 # define SCIF2          0xA4410000
  34 # define SCSMR_Ir       0xA44A0000
  35 # define IRDA_SCIF      SCIF0
  36 # define SCPCR 0xA4000116
  37 # define SCPDR 0xA4000136
  38
  39 /* Set the clock source,
  40  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  41  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  42  */
  43 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  44 #elif defined(CONFIG_CPU_SH7720) || \
  45         defined(CONFIG_CPU_SH7721) || \
  46         defined(CONFIG_ARCH_SH7367) || \
  47         defined(CONFIG_ARCH_SH7377) || \
  48         defined(CONFIG_ARCH_SH7372)
  49 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  50 # define PORT_PTCR         0xA405011EUL
  51 # define PORT_PVCR         0xA4050122UL
  52 # define SCIF_ORER         0x0200   /* overrun error bit */
  53 #elif defined(CONFIG_SH_RTS7751R2D)
  54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
  55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  56 # define SCIF_ORER 0x0001   /* overrun error bit */
  57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  58 #elif defined(CONFIG_CPU_SH7750)  || \
  59         defined(CONFIG_CPU_SH7750R) || \
  60         defined(CONFIG_CPU_SH7750S) || \
  61         defined(CONFIG_CPU_SH7091)  || \
  62         defined(CONFIG_CPU_SH7751)  || \
  63         defined(CONFIG_CPU_SH7751R)
  64 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  66 # define SCIF_ORER 0x0001   /* overrun error bit */
  67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  68         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  69         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
  70 #elif defined(CONFIG_CPU_SH7760)
  71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  74 # define SCIF_ORER 0x0001  /* overrun error bit */
  75 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
  77 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  78 # define SCIF_ORER 0x0001   /* overrun error bit */
  79 # define PACR 0xa4050100
  80 # define PBCR 0xa4050102
  81 # define SCSCR_INIT(port)          0x3B
  82 #elif defined(CONFIG_CPU_SH7343)
  83 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  84 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  85 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  86 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  87 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  88 #elif defined(CONFIG_CPU_SH7722)
  89 # define PADR                   0xA4050120
  90 # undef PSDR
  91 # define PSDR                   0xA405013e
  92 # define PWDR                   0xA4050166
  93 # define PSCR                   0xA405011E
  94 # define SCIF_ORER              0x0001  /* overrun error bit */
  95 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  96 #elif defined(CONFIG_CPU_SH7366)
  97 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  98 # define SCSPTR0                SCPDR0
  99 # define SCIF_ORER              0x0001  /* overrun error bit */
 100 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 101 #elif defined(CONFIG_CPU_SH7723)
 102 # define SCSPTR0                0xa4050160
 103 # define SCSPTR1                0xa405013e
 104 # define SCSPTR2                0xa4050160
 105 # define SCSPTR3                0xa405013e
 106 # define SCSPTR4                0xa4050128
 107 # define SCSPTR5                0xa4050128
 108 # define SCIF_ORER              0x0001  /* overrun error bit */
 109 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 110 #elif defined(CONFIG_CPU_SH7724)
 111 # define SCIF_ORER              0x0001  /* overrun error bit */
 112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
 113         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
 114         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
 115 #elif defined(CONFIG_CPU_SH4_202)
 116 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 117 # define SCIF_ORER 0x0001   /* overrun error bit */
 118 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 119 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
 120 # define SCIF_BASE_ADDR    0x01030000
 121 # define SCIF_ADDR_SH5     (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
 122 # define SCIF_PTR2_OFFS    0x0000020
 123 # define SCIF_LSR2_OFFS    0x0000024
 124 # define SCSPTR\
 125                 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 126 # define SCLSR2\
 127                 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 128 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 129 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 130 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 131 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
 132 #elif defined(CONFIG_H8S2678)
 133 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 134 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
 135 #elif defined(CONFIG_CPU_SH7757)
 136 # define SCSPTR0 0xfe4b0020
 137 # define SCSPTR1 0xfe4b0020
 138 # define SCSPTR2 0xfe4b0020
 139 # define SCIF_ORER 0x0001
 140 # define SCSCR_INIT(port)       0x38
 141 # define SCIF_ONLY
 142 #elif defined(CONFIG_CPU_SH7763)
 143 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 144 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 145 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 146 # define SCIF_ORER 0x0001  /* overrun error bit */
 147 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 148 #elif defined(CONFIG_CPU_SH7770)
 149 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 150 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 151 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 152 # define SCIF_ORER 0x0001  /* overrun error bit */
 153 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 154 #elif defined(CONFIG_CPU_SH7780)
 155 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 156 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 157 # define SCIF_ORER      0x0001          /* Overrun error bit */
 158
 159 #if defined(CONFIG_SH_SH2007)
 160 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
 161 # define SCSCR_INIT(port)       0x38
 162 #else
 163 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
 164 # define SCSCR_INIT(port)       0x3a
 165 #endif
 166
 167 #elif defined(CONFIG_CPU_SH7785) || \
 168         defined(CONFIG_CPU_SH7786)
 169 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 170 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 171 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 172 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 173 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 174 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 175 # define SCIF_ORER      0x0001          /* Overrun error bit */
 176 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 177 #elif defined(CONFIG_CPU_SH7201) || \
 178         defined(CONFIG_CPU_SH7203) || \
 179         defined(CONFIG_CPU_SH7206) || \
 180         defined(CONFIG_CPU_SH7263)
 181 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 182 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 183 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 184 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 185 # if defined(CONFIG_CPU_SH7201)
 186 #  define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
 187 #  define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
 188 #  define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
 189 #  define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
 190 # endif
 191 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 192 #elif defined(CONFIG_CPU_SH7619)
 193 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 194 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 195 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 196 # define SCIF_ORER 0x0001  /* overrun error bit */
 197 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 198 #elif defined(CONFIG_CPU_SHX3)
 199 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 200 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 201 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 202 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 203 # define SCIF_ORER 0x0001               /* Overrun error bit */
 204 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 205 #else
 206 # error CPU subtype not defined
 207 #endif
 208
 209 /* SCSCR */
 210 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 211 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 212 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 213 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 214 #if defined(CONFIG_CPU_SH7750)  || \
 215         defined(CONFIG_CPU_SH7091)  || \
 216         defined(CONFIG_CPU_SH7750R) || \
 217         defined(CONFIG_CPU_SH7722)  || \
 218         defined(CONFIG_CPU_SH7750S) || \
 219         defined(CONFIG_CPU_SH7751)  || \
 220         defined(CONFIG_CPU_SH7751R) || \
 221         defined(CONFIG_CPU_SH7763)  || \
 222         defined(CONFIG_CPU_SH7780)  || \
 223         defined(CONFIG_CPU_SH7785)  || \
 224         defined(CONFIG_CPU_SH7786)  || \
 225         defined(CONFIG_CPU_SHX3)
 226 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 227 #elif defined(CONFIG_CPU_SH7724)
 228 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
 229 #else
 230 #define SCI_CTRL_FLAGS_REIE 0
 231 #endif
 232 /*              SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 233 /*              SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 234 /*              SCI_CTRL_FLAGS_CKE1 0x02  * all */
 235 /*              SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 236
 237 /* SCxSR SCI */
 238 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 239 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 240 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 241 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 242 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 243 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 244 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 245 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 246
 247 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 248
 249 /* SCxSR SCIF */
 250 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 251 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 252 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 253 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 254 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 255 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 256 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 257 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 258
 259 #if defined(CONFIG_CPU_SH7705) || \
 260         defined(CONFIG_CPU_SH7720) || \
 261         defined(CONFIG_CPU_SH7721) || \
 262         defined(CONFIG_ARCH_SH7367) || \
 263         defined(CONFIG_ARCH_SH7377) || \
 264         defined(CONFIG_ARCH_SH7372)
 265 # define SCIF_ORER    0x0200
 266 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 267 # define SCIF_RFDC_MASK 0x007f
 268 # define SCIF_TXROOM_MAX 64
 269 #elif defined(CONFIG_CPU_SH7763)
 270 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 271 # define SCIF_RFDC_MASK 0x007f
 272 # define SCIF_TXROOM_MAX 64
 273 /* SH7763 SCIF2 support */
 274 # define SCIF2_RFDC_MASK 0x001f
 275 # define SCIF2_TXROOM_MAX 16
 276 #else
 277 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 278 # define SCIF_RFDC_MASK 0x001f
 279 # define SCIF_TXROOM_MAX 16
 280 #endif
 281
 282 #ifndef SCIF_ORER
 283 #define SCIF_ORER       0x0000
 284 #endif
 285
 286 #define SCxSR_TEND(port)\
 287                 (((port)->type == PORT_SCI) ? SCI_TEND  : SCIF_TEND)
 288 #define SCxSR_ERRORS(port)\
 289                 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 290 #define SCxSR_RDxF(port)\
 291                 (((port)->type == PORT_SCI) ? SCI_RDRF  : SCIF_RDF)
 292 #define SCxSR_TDxE(port)\
 293                 (((port)->type == PORT_SCI) ? SCI_TDRE  : SCIF_TDFE)
 294 #define SCxSR_FER(port)\
 295                 (((port)->type == PORT_SCI) ? SCI_FER   : SCIF_FER)
 296 #define SCxSR_PER(port)\
 297                 (((port)->type == PORT_SCI) ? SCI_PER   : SCIF_PER)
 298 #define SCxSR_BRK(port)\
 299                 ((port)->type == PORT_SCI) ? 0x00               : SCIF_BRK)
 300 #define SCxSR_ORER(port)\
 301                 (((port)->type == PORT_SCI) ? SCI_ORER  : SCIF_ORER)
 302
 303 #if defined(CONFIG_CPU_SH7705) || \
 304         defined(CONFIG_CPU_SH7720) || \
 305         defined(CONFIG_CPU_SH7721) || \
 306         defined(CONFIG_ARCH_SH7367) || \
 307         defined(CONFIG_ARCH_SH7377) || \
 308         defined(CONFIG_ARCH_SH7372)
 309 # define SCxSR_RDxF_CLEAR(port)  (sci_in(port, SCxSR) & 0xfffc)
 310 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 311 # define SCxSR_TDxE_CLEAR(port)  (sci_in(port, SCxSR) & 0xffdf)
 312 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
 313 #else
 314 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 315 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 316 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 317 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 318 #endif
 319
 320 /* SCFCR */
 321 #define SCFCR_RFRST 0x0002
 322 #define SCFCR_TFRST 0x0004
 323 #define SCFCR_TCRST 0x4000
 324 #define SCFCR_MCE   0x0008
 325
 326 #define SCI_MAJOR               204
 327 #define SCI_MINOR_START         8
 328
 329 /* Generic serial flags */
 330 #define SCI_RX_THROTTLE         0x0000001
 331
 332 #define SCI_MAGIC 0xbabeface
 333
 334 /*
 335  * Events are used to schedule things to happen at timer-interrupt
 336  * time, instead of at rs interrupt time.
 337  */
 338 #define SCI_EVENT_WRITE_WAKEUP  0
 339
 340 #define SCI_IN(size, offset)\
 341         if ((size) == 8) {\
 342                 return readb(port->membase + (offset));\
 343         } else {\
 344                 return readw(port->membase + (offset));\
 345         }
 346 #define SCI_OUT(size, offset, value)\
 347         if ((size) == 8) {\
 348                 writeb(value, port->membase + (offset));\
 349         } else if ((size) == 16) {\
 350                 writew(value, port->membase + (offset));\
 351         }
 352
 353 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 354         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 355                 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
 356                         SCI_IN(scif_size, scif_offset)\
 357                 } else { /* PORT_SCI or PORT_SCIFA */\
 358                         SCI_IN(sci_size, sci_offset);\
 359                 }\
 360         }\
 361 static inline void sci_##name##_out(struct uart_port *port,\
 362                                 unsigned int value) {\
 363         if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
 364                 SCI_OUT(scif_size, scif_offset, value)\
 365         } else {        /* PORT_SCI or PORT_SCIFA */\
 366                 SCI_OUT(sci_size, sci_offset, value);\
 367         }\
 368 }
 369
 370 #ifdef CONFIG_H8300
 371 /* h8300 don't have SCIF */
 372 #define CPU_SCIF_FNS(name)                                              \
 373         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 374                 return 0;\
 375         }\
 376         static inline void sci_##name##_out(struct uart_port *port,\
 377                                         unsigned int value) {\
 378         }
 379 #else
 380 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                      \
 381         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 382                 SCI_IN(scif_size, scif_offset);\
 383         }\
 384         static inline void sci_##name##_out(struct uart_port *port,\
 385                                         unsigned int value) {\
 386                 SCI_OUT(scif_size, scif_offset, value);\
 387         }
 388 #endif
 389
 390 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
 391         static inline unsigned int sci_##name##_in(struct uart_port *port) {\
 392                 SCI_IN(sci_size, sci_offset);\
 393         }\
 394         static inline void sci_##name##_out(struct uart_port *port,\
 395                                         unsigned int value) {\
 396                 SCI_OUT(sci_size, sci_offset, value);\
 397         }
 398
 399 #if defined(CONFIG_SH3) || \
 400         defined(CONFIG_ARCH_SH7367) || \
 401         defined(CONFIG_ARCH_SH7377) || \
 402         defined(CONFIG_ARCH_SH7372)
 403 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
 404 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 405                                 sh4_sci_offset, sh4_sci_size, \
 406                                 sh3_scif_offset, sh3_scif_size, \
 407                                 sh4_scif_offset, sh4_scif_size, \
 408                                 h8_sci_offset, h8_sci_size) \
 409         CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
 410                                 sh4_scif_offset, sh4_scif_size)
 411 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
 412                                 sh4_scif_offset, sh4_scif_size) \
 413         CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 414 #elif defined(CONFIG_CPU_SH7705) || \
 415         defined(CONFIG_CPU_SH7720) || \
 416         defined(CONFIG_CPU_SH7721) || \
 417         defined(CONFIG_ARCH_SH7367) || \
 418         defined(CONFIG_ARCH_SH7377)
 419 #define SCIF_FNS(name, scif_offset, scif_size) \
 420         CPU_SCIF_FNS(name, scif_offset, scif_size)
 421 #elif defined(CONFIG_ARCH_SH7372)
 422 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 423                                 sh4_scifb_offset, sh4_scifb_size) \
 424         CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 425                                 sh4_scifb_offset, sh4_scifb_size)
 426 #define SCIF_FNS(name, scif_offset, scif_size) \
 427         CPU_SCIF_FNS(name, scif_offset, scif_size)
 428 #else
 429 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 430                                 sh4_sci_offset, sh4_sci_size, \
 431                                 sh3_scif_offset, sh3_scif_size,\
 432                                 sh4_scif_offset, sh4_scif_size, \
 433                                 h8_sci_offset, h8_sci_size) \
 434         CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 435                                 sh3_scif_offset, sh3_scif_size)
 436 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
 437                                 sh4_scif_offset, sh4_scif_size) \
 438         CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 439 #endif
 440 #elif defined(__H8300H__) || defined(__H8300S__)
 441 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 442                                 sh4_sci_offset, sh4_sci_size, \
 443                                 sh3_scif_offset, sh3_scif_size,\
 444                                 sh4_scif_offset, sh4_scif_size, \
 445                                 h8_sci_offset, h8_sci_size) \
 446         CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 447 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
 448                                         sh4_scif_offset, sh4_scif_size) \
 449         CPU_SCIF_FNS(name)
 450 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
 451                 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 452                                         sh4_scif_offset, sh4_scif_size) \
 453                         CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 454                                         sh4_scif_offset, sh4_scif_size)
 455                 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
 456                         CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 457 #else
 458 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 459                                 sh4_sci_offset, sh4_sci_size, \
 460                                 sh3_scif_offset, sh3_scif_size,\
 461                                 sh4_scif_offset, sh4_scif_size, \
 462                                 h8_sci_offset, h8_sci_size) \
 463         CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
 464                                         sh4_scif_offset, sh4_scif_size)
 465 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
 466                                 sh4_scif_offset, sh4_scif_size) \
 467         CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 468 #endif
 469
 470 #if defined(CONFIG_CPU_SH7705) || \
 471         defined(CONFIG_CPU_SH7720) || \
 472         defined(CONFIG_CPU_SH7721) || \
 473         defined(CONFIG_ARCH_SH7367) || \
 474         defined(CONFIG_ARCH_SH7377)
 475
 476 SCIF_FNS(SCSMR,  0x00, 16)
 477 SCIF_FNS(SCBRR,  0x04,  8)
 478 SCIF_FNS(SCSCR,  0x08, 16)
 479 SCIF_FNS(SCTDSR, 0x0c,  8)
 480 SCIF_FNS(SCFER,  0x10, 16)
 481 SCIF_FNS(SCxSR,  0x14, 16)
 482 SCIF_FNS(SCFCR,  0x18, 16)
 483 SCIF_FNS(SCFDR,  0x1c, 16)
 484 SCIF_FNS(SCxTDR, 0x20,  8)
 485 SCIF_FNS(SCxRDR, 0x24,  8)
 486 SCIF_FNS(SCLSR,  0x00,  0)
 487 #elif defined(CONFIG_ARCH_SH7372)
 488 SCIF_FNS(SCSMR,  0x00, 16)
 489 SCIF_FNS(SCBRR,  0x04,  8)
 490 SCIF_FNS(SCSCR,  0x08, 16)
 491 SCIF_FNS(SCTDSR, 0x0c, 16)
 492 SCIF_FNS(SCFER,  0x10, 16)
 493 SCIF_FNS(SCxSR,  0x14, 16)
 494 SCIF_FNS(SCFCR,  0x18, 16)
 495 SCIF_FNS(SCFDR,  0x1c, 16)
 496 SCIF_FNS(SCTFDR, 0x38, 16)
 497 SCIF_FNS(SCRFDR, 0x3c, 16)
 498 SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
 499 SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
 500 SCIF_FNS(SCLSR,  0x00,  0)
 501 #elif defined(CONFIG_CPU_SH7723) ||\
 502         defined(CONFIG_CPU_SH7724)
 503 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 504 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 505 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
 506 SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
 507 SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
 508 SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
 509 SCIx_FNS(SCSPTR, 0,     0,    0,  0)
 510 SCIF_FNS(SCTDSR, 0x0c,  8)
 511 SCIF_FNS(SCFER,  0x10, 16)
 512 SCIF_FNS(SCFCR,  0x18, 16)
 513 SCIF_FNS(SCFDR,  0x1c, 16)
 514 SCIF_FNS(SCLSR,  0x24, 16)
 515 #else
 516 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 517 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 518 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 519 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 520 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 521 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 522 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 523 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 524 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 525 #if defined(CONFIG_CPU_SH7760) || \
 526         defined(CONFIG_CPU_SH7780) || \
 527         defined(CONFIG_CPU_SH7785) || \
 528         defined(CONFIG_CPU_SH7786)
 529 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 530 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 531 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 532 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 533 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 534 #elif defined(CONFIG_CPU_SH7763)
 535 SCIF_FNS(SCFDR,                         0,  0, 0x1C, 16)
 536 SCIF_FNS(SCSPTR2,                       0,  0, 0x20, 16)
 537 SCIF_FNS(SCLSR2,                        0,  0, 0x24, 16)
 538 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 539 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 540 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 541 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 542 #else
 543 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 544 #if defined(CONFIG_CPU_SH7722)
 545 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 546 #else
 547 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 548 #endif
 549 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 550 #endif
 551 #endif
 552 #define sci_in(port, reg) sci_##reg##_in(port)
 553 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 554
 555 /* H8/300 series SCI pins assignment */
 556 #if defined(__H8300H__) || defined(__H8300S__)
 557 static const struct __attribute__((packed)) {
 558         int port;             /* GPIO port no */
 559         unsigned short rx, tx; /* GPIO bit no */
 560 } h8300_sci_pins[] = {
 561 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 562         {    /* SCI0 */
 563                 .port = H8300_GPIO_P9,
 564                 .rx   = H8300_GPIO_B2,
 565                 .tx   = H8300_GPIO_B0,
 566         },
 567         {    /* SCI1 */
 568                 .port = H8300_GPIO_P9,
 569                 .rx   = H8300_GPIO_B3,
 570                 .tx   = H8300_GPIO_B1,
 571         },
 572         {    /* SCI2 */
 573                 .port = H8300_GPIO_PB,
 574                 .rx   = H8300_GPIO_B7,
 575                 .tx   = H8300_GPIO_B6,
 576         }
 577 #elif defined(CONFIG_H8S2678)
 578         {    /* SCI0 */
 579                 .port = H8300_GPIO_P3,
 580                 .rx   = H8300_GPIO_B2,
 581                 .tx   = H8300_GPIO_B0,
 582         },
 583         {    /* SCI1 */
 584                 .port = H8300_GPIO_P3,
 585                 .rx   = H8300_GPIO_B3,
 586                 .tx   = H8300_GPIO_B1,
 587         },
 588         {    /* SCI2 */
 589                 .port = H8300_GPIO_P5,
 590                 .rx   = H8300_GPIO_B1,
 591                 .tx   = H8300_GPIO_B0,
 592         }
 593 #endif
 594 };
 595 #endif
 596
 597 #if defined(CONFIG_CPU_SH7706) || \
 598         defined(CONFIG_CPU_SH7707) || \
 599         defined(CONFIG_CPU_SH7708) || \
 600         defined(CONFIG_CPU_SH7709)
 601 static inline int sci_rxd_in(struct uart_port *port)
 602 {
 603         if (port->mapbase == 0xfffffe80)
 604                 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 605         return 1;
 606 }
 607 #elif defined(CONFIG_CPU_SH7750)  || \
 608         defined(CONFIG_CPU_SH7751)  || \
 609         defined(CONFIG_CPU_SH7751R) || \
 610         defined(CONFIG_CPU_SH7750R) || \
 611         defined(CONFIG_CPU_SH7750S) || \
 612         defined(CONFIG_CPU_SH7091)
 613 static inline int sci_rxd_in(struct uart_port *port)
 614 {
 615         if (port->mapbase == 0xffe00000)
 616                 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 617         return 1;
 618 }
 619 #elif defined(__H8300H__) || defined(__H8300S__)
 620 static inline int sci_rxd_in(struct uart_port *port)
 621 {
 622         int ch = (port->mapbase - SMR0) >> 3;
 623         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 624 }
 625 #else /* default case for non-SCI processors */
 626 static inline int sci_rxd_in(struct uart_port *port)
 627 {
 628         return 1;
 629 }
 630 #endif
 631
 632 /*
 633  * Values for the BitRate Register (SCBRR)
 634  *
 635  * The values are actually divisors for a frequency which can
 636  * be internal to the SH3 (14.7456MHz) or derived from an external
 637  * clock source.  This driver assumes the internal clock is used;
 638  * to support using an external clock source, config options or
 639  * possibly command-line options would need to be added.
 640  *
 641  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 642  * the SCSMR register would also need to be set to non-zero values.
 643  *
 644  * -- Greg Banks 27Feb2000
 645  *
 646  * Answer: The SCBRR register is only eight bits, and the value in
 647  * it gets larger with lower baud rates. At around 2400 (depending on
 648  * the peripherial module clock) you run out of bits. However the
 649  * lower two bits of SCSMR allow the module clock to be divided down,
 650  * scaling the value which is needed in SCBRR.
 651  *
 652  * -- Stuart Menefy - 23 May 2000
 653  *
 654  * I meant, why would anyone bother with bitrates below 2400.
 655  *
 656  * -- Greg Banks - 7Jul2000
 657  *
 658  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 659  * tape reader as a console!
 660  *
 661  * -- Mitch Davis - 15 Jul 2000
 662  */
 663
 664 #if (defined(CONFIG_CPU_SH7780)  || \
 665         defined(CONFIG_CPU_SH7785)  || \
 666         defined(CONFIG_CPU_SH7786)) && \
 667         !defined(CONFIG_SH_SH2007)
 668 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 669 #elif defined(CONFIG_CPU_SH7705) || \
 670         defined(CONFIG_CPU_SH7720) || \
 671         defined(CONFIG_CPU_SH7721) || \
 672         defined(CONFIG_ARCH_SH7367) || \
 673         defined(CONFIG_ARCH_SH7377) || \
 674         defined(CONFIG_ARCH_SH7372)
 675 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 676 #elif defined(CONFIG_CPU_SH7723) ||\
 677         defined(CONFIG_CPU_SH7724)
 678 static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 679 {
 680         if (port.type == PORT_SCIF)
 681                 return (clk+16*bps)/(32*bps)-1;
 682         else
 683                 return ((clk*2)+16*bps)/(16*bps)-1;
 684 }
 685 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 686 #elif defined(__H8300H__) || defined(__H8300S__)
 687 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 688 #else /* Generic SH */
 689 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 690 #endif