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1 /*
2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <linux/io.h>
12 #include <linux/serial_reg.h>
13 #include <linux/sizes.h>
14 #include <linux/errno.h>
15 #include <serial.h>
16 #include <fdtdec.h>
17
18 /*
19 * Note: Register map is slightly different from that of 16550.
20 */
21 struct uniphier_serial {
22 u32 rx; /* In: Receive buffer */
23 #define tx rx /* Out: Transmit buffer */
24 u32 ier; /* Interrupt Enable Register */
25 u32 iir; /* In: Interrupt ID Register */
26 u32 char_fcr; /* Charactor / FIFO Control Register */
27 u32 lcr_mcr; /* Line/Modem Control Register */
28 #define LCR_SHIFT 8
29 #define LCR_MASK (0xff << (LCR_SHIFT))
30 u32 lsr; /* In: Line Status Register */
31 u32 msr; /* In: Modem Status Register */
32 u32 __rsv0;
33 u32 __rsv1;
34 u32 dlr; /* Divisor Latch Register */
35 };
36
37 struct uniphier_serial_private_data {
38 struct uniphier_serial __iomem *membase;
39 unsigned int uartclk;
40 };
41
42 #define uniphier_serial_port(dev) \
43 ((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase
44
45 static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
46 {
47 struct uniphier_serial_private_data *priv = dev_get_priv(dev);
48 struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
49 const unsigned int mode_x_div = 16;
50 unsigned int divisor;
51
52 divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate);
53
54 writel(divisor, &port->dlr);
55
56 return 0;
57 }
58
59 static int uniphier_serial_getc(struct udevice *dev)
60 {
61 struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
62
63 if (!(readl(&port->lsr) & UART_LSR_DR))
64 return -EAGAIN;
65
66 return readl(&port->rx);
67 }
68
69 static int uniphier_serial_putc(struct udevice *dev, const char c)
70 {
71 struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
72
73 if (!(readl(&port->lsr) & UART_LSR_THRE))
74 return -EAGAIN;
75
76 writel(c, &port->tx);
77
78 return 0;
79 }
80
81 static int uniphier_serial_pending(struct udevice *dev, bool input)
82 {
83 struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
84
85 if (input)
86 return readl(&port->lsr) & UART_LSR_DR;
87 else
88 return !(readl(&port->lsr) & UART_LSR_THRE);
89 }
90
91 static int uniphier_serial_probe(struct udevice *dev)
92 {
93 DECLARE_GLOBAL_DATA_PTR;
94 struct uniphier_serial_private_data *priv = dev_get_priv(dev);
95 struct uniphier_serial __iomem *port;
96 fdt_addr_t base;
97 u32 tmp;
98
99 base = devfdt_get_addr(dev);
100 if (base == FDT_ADDR_T_NONE)
101 return -EINVAL;
102
103 port = devm_ioremap(dev, base, SZ_64);
104 if (!port)
105 return -ENOMEM;
106
107 priv->membase = port;
108
109 priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
110 "clock-frequency", 0);
111
112 tmp = readl(&port->lcr_mcr);
113 tmp &= ~LCR_MASK;
114 tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
115 writel(tmp, &port->lcr_mcr);
116
117 return 0;
118 }
119
120 static const struct udevice_id uniphier_uart_of_match[] = {
121 { .compatible = "socionext,uniphier-uart" },
122 { /* sentinel */ }
123 };
124
125 static const struct dm_serial_ops uniphier_serial_ops = {
126 .setbrg = uniphier_serial_setbrg,
127 .getc = uniphier_serial_getc,
128 .putc = uniphier_serial_putc,
129 .pending = uniphier_serial_pending,
130 };
131
132 U_BOOT_DRIVER(uniphier_serial) = {
133 .name = "uniphier-uart",
134 .id = UCLASS_SERIAL,
135 .of_match = uniphier_uart_of_match,
136 .probe = uniphier_serial_probe,
137 .priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data),
138 .ops = &uniphier_serial_ops,
139 };