drivers/serial/serial_zynq.c

   1 /*
   2  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <debug_uart.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <watchdog.h>
  15 #include <asm/io.h>
  16 #include <linux/compiler.h>
  17 #include <serial.h>
  18 #include <asm/arch/hardware.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define ZYNQ_UART_SR_TXEMPTY    (1 << 3) /* TX FIFO empty */
  23 #define ZYNQ_UART_SR_TXACTIVE   (1 << 11)  /* TX active */
  24 #define ZYNQ_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
  25
  26 #define ZYNQ_UART_CR_TX_EN      0x00000010 /* TX enabled */
  27 #define ZYNQ_UART_CR_RX_EN      0x00000004 /* RX enabled */
  28 #define ZYNQ_UART_CR_TXRST      0x00000002 /* TX logic reset */
  29 #define ZYNQ_UART_CR_RXRST      0x00000001 /* RX logic reset */
  30
  31 #define ZYNQ_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  32
  33 struct uart_zynq {
  34         u32 control; /* 0x0 - Control Register [8:0] */
  35         u32 mode; /* 0x4 - Mode Register [10:0] */
  36         u32 reserved1[4];
  37         u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  38         u32 reserved2[4];
  39         u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  40         u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  41         u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  42 };
  43
  44 struct zynq_uart_priv {
  45         struct uart_zynq *regs;
  46 };
  47
  48 /* Set up the baud rate in gd struct */
  49 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  50                                      unsigned long clock, unsigned long baud)
  51 {
  52         /* Calculation results. */
  53         unsigned int calc_bauderror, bdiv, bgen;
  54         unsigned long calc_baud = 0;
  55
  56         /* Covering case where input clock is so slow */
  57         if (clock < 1000000 && baud > 4800)
  58                 baud = 4800;
  59
  60         /*                master clock
  61          * Baud rate = ------------------
  62          *              bgen * (bdiv + 1)
  63          *
  64          * Find acceptable values for baud generation.
  65          */
  66         for (bdiv = 4; bdiv < 255; bdiv++) {
  67                 bgen = clock / (baud * (bdiv + 1));
  68                 if (bgen < 2 || bgen > 65535)
  69                         continue;
  70
  71                 calc_baud = clock / (bgen * (bdiv + 1));
  72
  73                 /*
  74                  * Use first calculated baudrate with
  75                  * an acceptable (<3%) error
  76                  */
  77                 if (baud > calc_baud)
  78                         calc_bauderror = baud - calc_baud;
  79                 else
  80                         calc_bauderror = calc_baud - baud;
  81                 if (((calc_bauderror * 100) / baud) < 3)
  82                         break;
  83         }
  84
  85         writel(bdiv, &regs->baud_rate_divider);
  86         writel(bgen, &regs->baud_rate_gen);
  87 }
  88
  89 /* Initialize the UART, with...some settings. */
  90 static void _uart_zynq_serial_init(struct uart_zynq *regs)
  91 {
  92         /* RX/TX enabled & reset */
  93         writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  94                                         ZYNQ_UART_CR_RXRST, &regs->control);
  95         writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  96 }
  97
  98 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
  99 {
 100         if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
 101                 return -EAGAIN;
 102
 103         writel(c, &regs->tx_rx_fifo);
 104
 105         return 0;
 106 }
 107
 108 int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 109 {
 110         struct zynq_uart_priv *priv = dev_get_priv(dev);
 111         unsigned long clock;
 112
 113         int ret;
 114         struct clk clk;
 115
 116         ret = clk_get_by_index(dev, 0, &clk);
 117         if (ret < 0) {
 118                 dev_err(dev, "failed to get clock\n");
 119                 return ret;
 120         }
 121
 122         clock = clk_get_rate(&clk);
 123         if (IS_ERR_VALUE(clock)) {
 124                 dev_err(dev, "failed to get rate\n");
 125                 return clock;
 126         }
 127         debug("%s: CLK %ld\n", __func__, clock);
 128
 129         ret = clk_enable(&clk);
 130         if (ret && ret != -ENOSYS) {
 131                 dev_err(dev, "failed to enable clock\n");
 132                 return ret;
 133         }
 134
 135         _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
 136
 137         return 0;
 138 }
 139
 140 static int zynq_serial_probe(struct udevice *dev)
 141 {
 142         struct zynq_uart_priv *priv = dev_get_priv(dev);
 143
 144         _uart_zynq_serial_init(priv->regs);
 145
 146         return 0;
 147 }
 148
 149 static int zynq_serial_getc(struct udevice *dev)
 150 {
 151         struct zynq_uart_priv *priv = dev_get_priv(dev);
 152         struct uart_zynq *regs = priv->regs;
 153
 154         if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
 155                 return -EAGAIN;
 156
 157         return readl(&regs->tx_rx_fifo);
 158 }
 159
 160 static int zynq_serial_putc(struct udevice *dev, const char ch)
 161 {
 162         struct zynq_uart_priv *priv = dev_get_priv(dev);
 163
 164         return _uart_zynq_serial_putc(priv->regs, ch);
 165 }
 166
 167 static int zynq_serial_pending(struct udevice *dev, bool input)
 168 {
 169         struct zynq_uart_priv *priv = dev_get_priv(dev);
 170         struct uart_zynq *regs = priv->regs;
 171
 172         if (input)
 173                 return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
 174         else
 175                 return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
 176 }
 177
 178 static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
 179 {
 180         struct zynq_uart_priv *priv = dev_get_priv(dev);
 181
 182         priv->regs = (struct uart_zynq *)devfdt_get_addr(dev);
 183
 184         return 0;
 185 }
 186
 187 static const struct dm_serial_ops zynq_serial_ops = {
 188         .putc = zynq_serial_putc,
 189         .pending = zynq_serial_pending,
 190         .getc = zynq_serial_getc,
 191         .setbrg = zynq_serial_setbrg,
 192 };
 193
 194 static const struct udevice_id zynq_serial_ids[] = {
 195         { .compatible = "xlnx,xuartps" },
 196         { .compatible = "cdns,uart-r1p8" },
 197         { .compatible = "cdns,uart-r1p12" },
 198         { }
 199 };
 200
 201 U_BOOT_DRIVER(serial_zynq) = {
 202         .name   = "serial_zynq",
 203         .id     = UCLASS_SERIAL,
 204         .of_match = zynq_serial_ids,
 205         .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
 206         .priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
 207         .probe = zynq_serial_probe,
 208         .ops    = &zynq_serial_ops,
 209         .flags = DM_FLAG_PRE_RELOC,
 210 };
 211
 212 #ifdef CONFIG_DEBUG_UART_ZYNQ
 213 static inline void _debug_uart_init(void)
 214 {
 215         struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 216
 217         _uart_zynq_serial_init(regs);
 218         _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
 219                                  CONFIG_BAUDRATE);
 220 }
 221
 222 static inline void _debug_uart_putc(int ch)
 223 {
 224         struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 225
 226         while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
 227                 WATCHDOG_RESET();
 228 }
 229
 230 DEBUG_UART_FUNCS
 231
 232 #endif