drivers/serial/serial_zynq.c

   1 /*
   2  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <debug_uart.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <watchdog.h>
  15 #include <asm/io.h>
  16 #include <linux/compiler.h>
  17 #include <serial.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/arch/hardware.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define ZYNQ_UART_SR_TXEMPTY    (1 << 3) /* TX FIFO empty */
  24 #define ZYNQ_UART_SR_TXACTIVE   (1 << 11)  /* TX active */
  25 #define ZYNQ_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
  26
  27 #define ZYNQ_UART_CR_TX_EN      0x00000010 /* TX enabled */
  28 #define ZYNQ_UART_CR_RX_EN      0x00000004 /* RX enabled */
  29 #define ZYNQ_UART_CR_TXRST      0x00000002 /* TX logic reset */
  30 #define ZYNQ_UART_CR_RXRST      0x00000001 /* RX logic reset */
  31
  32 #define ZYNQ_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  33
  34 struct uart_zynq {
  35         u32 control; /* 0x0 - Control Register [8:0] */
  36         u32 mode; /* 0x4 - Mode Register [10:0] */
  37         u32 reserved1[4];
  38         u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  39         u32 reserved2[4];
  40         u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  41         u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  42         u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  43 };
  44
  45 struct zynq_uart_priv {
  46         struct uart_zynq *regs;
  47 };
  48
  49 /* Set up the baud rate in gd struct */
  50 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  51                                      unsigned long clock, unsigned long baud)
  52 {
  53         /* Calculation results. */
  54         unsigned int calc_bauderror, bdiv, bgen;
  55         unsigned long calc_baud = 0;
  56
  57         /* Covering case where input clock is so slow */
  58         if (clock < 1000000 && baud > 4800)
  59                 baud = 4800;
  60
  61         /*                master clock
  62          * Baud rate = ------------------
  63          *              bgen * (bdiv + 1)
  64          *
  65          * Find acceptable values for baud generation.
  66          */
  67         for (bdiv = 4; bdiv < 255; bdiv++) {
  68                 bgen = clock / (baud * (bdiv + 1));
  69                 if (bgen < 2 || bgen > 65535)
  70                         continue;
  71
  72                 calc_baud = clock / (bgen * (bdiv + 1));
  73
  74                 /*
  75                  * Use first calculated baudrate with
  76                  * an acceptable (<3%) error
  77                  */
  78                 if (baud > calc_baud)
  79                         calc_bauderror = baud - calc_baud;
  80                 else
  81                         calc_bauderror = calc_baud - baud;
  82                 if (((calc_bauderror * 100) / baud) < 3)
  83                         break;
  84         }
  85
  86         writel(bdiv, &regs->baud_rate_divider);
  87         writel(bgen, &regs->baud_rate_gen);
  88 }
  89
  90 /* Initialize the UART, with...some settings. */
  91 static void _uart_zynq_serial_init(struct uart_zynq *regs)
  92 {
  93         /* RX/TX enabled & reset */
  94         writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  95                                         ZYNQ_UART_CR_RXRST, &regs->control);
  96         writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  97 }
  98
  99 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
 100 {
 101         if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
 102                 return -EAGAIN;
 103
 104         writel(c, &regs->tx_rx_fifo);
 105
 106         return 0;
 107 }
 108
 109 int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 110 {
 111         struct zynq_uart_priv *priv = dev_get_priv(dev);
 112         unsigned long clock;
 113
 114 #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 115         int ret;
 116         struct clk clk;
 117
 118         ret = clk_get_by_index(dev, 0, &clk);
 119         if (ret < 0) {
 120                 dev_err(dev, "failed to get clock\n");
 121                 return ret;
 122         }
 123
 124         clock = clk_get_rate(&clk);
 125         if (IS_ERR_VALUE(clock)) {
 126                 dev_err(dev, "failed to get rate\n");
 127                 return clock;
 128         }
 129         debug("%s: CLK %ld\n", __func__, clock);
 130
 131         ret = clk_enable(&clk);
 132         if (ret && ret != -ENOSYS) {
 133                 dev_err(dev, "failed to enable clock\n");
 134                 return ret;
 135         }
 136 #else
 137         clock = get_uart_clk(0);
 138 #endif
 139         _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
 140
 141         return 0;
 142 }
 143
 144 static int zynq_serial_probe(struct udevice *dev)
 145 {
 146         struct zynq_uart_priv *priv = dev_get_priv(dev);
 147
 148         _uart_zynq_serial_init(priv->regs);
 149
 150         return 0;
 151 }
 152
 153 static int zynq_serial_getc(struct udevice *dev)
 154 {
 155         struct zynq_uart_priv *priv = dev_get_priv(dev);
 156         struct uart_zynq *regs = priv->regs;
 157
 158         if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
 159                 return -EAGAIN;
 160
 161         return readl(&regs->tx_rx_fifo);
 162 }
 163
 164 static int zynq_serial_putc(struct udevice *dev, const char ch)
 165 {
 166         struct zynq_uart_priv *priv = dev_get_priv(dev);
 167
 168         return _uart_zynq_serial_putc(priv->regs, ch);
 169 }
 170
 171 static int zynq_serial_pending(struct udevice *dev, bool input)
 172 {
 173         struct zynq_uart_priv *priv = dev_get_priv(dev);
 174         struct uart_zynq *regs = priv->regs;
 175
 176         if (input)
 177                 return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
 178         else
 179                 return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
 180 }
 181
 182 static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
 183 {
 184         struct zynq_uart_priv *priv = dev_get_priv(dev);
 185
 186         priv->regs = (struct uart_zynq *)dev_get_addr(dev);
 187
 188         return 0;
 189 }
 190
 191 static const struct dm_serial_ops zynq_serial_ops = {
 192         .putc = zynq_serial_putc,
 193         .pending = zynq_serial_pending,
 194         .getc = zynq_serial_getc,
 195         .setbrg = zynq_serial_setbrg,
 196 };
 197
 198 static const struct udevice_id zynq_serial_ids[] = {
 199         { .compatible = "xlnx,xuartps" },
 200         { .compatible = "cdns,uart-r1p8" },
 201         { .compatible = "cdns,uart-r1p12" },
 202         { }
 203 };
 204
 205 U_BOOT_DRIVER(serial_zynq) = {
 206         .name   = "serial_zynq",
 207         .id     = UCLASS_SERIAL,
 208         .of_match = zynq_serial_ids,
 209         .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
 210         .priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
 211         .probe = zynq_serial_probe,
 212         .ops    = &zynq_serial_ops,
 213         .flags = DM_FLAG_PRE_RELOC,
 214 };
 215
 216 #ifdef CONFIG_DEBUG_UART_ZYNQ
 217 static inline void _debug_uart_init(void)
 218 {
 219         struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 220
 221         _uart_zynq_serial_init(regs);
 222         _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
 223                                  CONFIG_BAUDRATE);
 224 }
 225
 226 static inline void _debug_uart_putc(int ch)
 227 {
 228         struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 229
 230         while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
 231                 WATCHDOG_RESET();
 232 }
 233
 234 DEBUG_UART_FUNCS
 235
 236 #endif