drivers/serial/serial_zynq.c

   1 /*
   2  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <fdtdec.h>
  10 #include <watchdog.h>
  11 #include <asm/io.h>
  12 #include <linux/compiler.h>
  13 #include <serial.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/hardware.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define ZYNQ_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
  20 #define ZYNQ_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
  21
  22 #define ZYNQ_UART_CR_TX_EN      0x00000010 /* TX enabled */
  23 #define ZYNQ_UART_CR_RX_EN      0x00000004 /* RX enabled */
  24 #define ZYNQ_UART_CR_TXRST      0x00000002 /* TX logic reset */
  25 #define ZYNQ_UART_CR_RXRST      0x00000001 /* RX logic reset */
  26
  27 #define ZYNQ_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  28
  29 struct uart_zynq {
  30         u32 control; /* 0x0 - Control Register [8:0] */
  31         u32 mode; /* 0x4 - Mode Register [10:0] */
  32         u32 reserved1[4];
  33         u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  34         u32 reserved2[4];
  35         u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  36         u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  37         u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  38 };
  39
  40 static struct uart_zynq *uart_zynq_ports[2] = {
  41         [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
  42         [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
  43 };
  44
  45 /* Set up the baud rate in gd struct */
  46 static void uart_zynq_serial_setbrg(const int port)
  47 {
  48         /* Calculation results. */
  49         unsigned int calc_bauderror, bdiv, bgen;
  50         unsigned long calc_baud = 0;
  51         unsigned long baud = gd->baudrate;
  52         unsigned long clock = get_uart_clk(port);
  53         struct uart_zynq *regs = uart_zynq_ports[port];
  54
  55         /*                master clock
  56          * Baud rate = ------------------
  57          *              bgen * (bdiv + 1)
  58          *
  59          * Find acceptable values for baud generation.
  60          */
  61         for (bdiv = 4; bdiv < 255; bdiv++) {
  62                 bgen = clock / (baud * (bdiv + 1));
  63                 if (bgen < 2 || bgen > 65535)
  64                         continue;
  65
  66                 calc_baud = clock / (bgen * (bdiv + 1));
  67
  68                 /*
  69                  * Use first calculated baudrate with
  70                  * an acceptable (<3%) error
  71                  */
  72                 if (baud > calc_baud)
  73                         calc_bauderror = baud - calc_baud;
  74                 else
  75                         calc_bauderror = calc_baud - baud;
  76                 if (((calc_bauderror * 100) / baud) < 3)
  77                         break;
  78         }
  79
  80         writel(bdiv, &regs->baud_rate_divider);
  81         writel(bgen, &regs->baud_rate_gen);
  82 }
  83
  84 /* Initialize the UART, with...some settings. */
  85 static int uart_zynq_serial_init(const int port)
  86 {
  87         struct uart_zynq *regs = uart_zynq_ports[port];
  88
  89         if (!regs)
  90                 return -1;
  91
  92         /* RX/TX enabled & reset */
  93         writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  94                                         ZYNQ_UART_CR_RXRST, &regs->control);
  95         writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  96         uart_zynq_serial_setbrg(port);
  97
  98         return 0;
  99 }
 100
 101 static void uart_zynq_serial_putc(const char c, const int port)
 102 {
 103         struct uart_zynq *regs = uart_zynq_ports[port];
 104
 105         while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
 106                 WATCHDOG_RESET();
 107
 108         if (c == '\n') {
 109                 writel('\r', &regs->tx_rx_fifo);
 110                 while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
 111                         WATCHDOG_RESET();
 112         }
 113         writel(c, &regs->tx_rx_fifo);
 114 }
 115
 116 static void uart_zynq_serial_puts(const char *s, const int port)
 117 {
 118         while (*s)
 119                 uart_zynq_serial_putc(*s++, port);
 120 }
 121
 122 static int uart_zynq_serial_tstc(const int port)
 123 {
 124         struct uart_zynq *regs = uart_zynq_ports[port];
 125
 126         return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
 127 }
 128
 129 static int uart_zynq_serial_getc(const int port)
 130 {
 131         struct uart_zynq *regs = uart_zynq_ports[port];
 132
 133         while (!uart_zynq_serial_tstc(port))
 134                 WATCHDOG_RESET();
 135         return readl(&regs->tx_rx_fifo);
 136 }
 137
 138 /* Multi serial device functions */
 139 #define DECLARE_PSSERIAL_FUNCTIONS(port) \
 140         static int uart_zynq##port##_init(void) \
 141                                 { return uart_zynq_serial_init(port); } \
 142         static void uart_zynq##port##_setbrg(void) \
 143                                 { return uart_zynq_serial_setbrg(port); } \
 144         static int uart_zynq##port##_getc(void) \
 145                                 { return uart_zynq_serial_getc(port); } \
 146         static int uart_zynq##port##_tstc(void) \
 147                                 { return uart_zynq_serial_tstc(port); } \
 148         static void uart_zynq##port##_putc(const char c) \
 149                                 { uart_zynq_serial_putc(c, port); } \
 150         static void uart_zynq##port##_puts(const char *s) \
 151                                 { uart_zynq_serial_puts(s, port); }
 152
 153 /* Serial device descriptor */
 154 #define INIT_PSSERIAL_STRUCTURE(port, __name) { \
 155           .name   = __name,                     \
 156           .start  = uart_zynq##port##_init,     \
 157           .stop   = NULL,                       \
 158           .setbrg = uart_zynq##port##_setbrg,   \
 159           .getc   = uart_zynq##port##_getc,     \
 160           .tstc   = uart_zynq##port##_tstc,     \
 161           .putc   = uart_zynq##port##_putc,     \
 162           .puts   = uart_zynq##port##_puts,     \
 163 }
 164
 165 DECLARE_PSSERIAL_FUNCTIONS(0);
 166 static struct serial_device uart_zynq_serial0_device =
 167         INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
 168 DECLARE_PSSERIAL_FUNCTIONS(1);
 169 static struct serial_device uart_zynq_serial1_device =
 170         INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
 171
 172 #ifdef CONFIG_OF_CONTROL
 173 __weak struct serial_device *default_serial_console(void)
 174 {
 175         const void *blob = gd->fdt_blob;
 176         int node;
 177         unsigned int base_addr;
 178
 179         node = fdt_path_offset(blob, "serial0");
 180         if (node < 0)
 181                 return NULL;
 182
 183         base_addr = fdtdec_get_addr(blob, node, "reg");
 184         if (base_addr == FDT_ADDR_T_NONE)
 185                 return NULL;
 186
 187         if (base_addr == ZYNQ_SERIAL_BASEADDR0)
 188                 return &uart_zynq_serial0_device;
 189
 190         if (base_addr == ZYNQ_SERIAL_BASEADDR1)
 191                 return &uart_zynq_serial1_device;
 192
 193         return NULL;
 194 }
 195 #else
 196 __weak struct serial_device *default_serial_console(void)
 197 {
 198 #if defined(CONFIG_ZYNQ_SERIAL_UART0)
 199         if (uart_zynq_ports[0])
 200                 return &uart_zynq_serial0_device;
 201 #endif
 202 #if defined(CONFIG_ZYNQ_SERIAL_UART1)
 203         if (uart_zynq_ports[1])
 204                 return &uart_zynq_serial1_device;
 205 #endif
 206         return NULL;
 207 }
 208 #endif
 209
 210 void zynq_serial_initialize(void)
 211 {
 212         serial_register(&uart_zynq_serial0_device);
 213         serial_register(&uart_zynq_serial1_device);
 214 }