2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <debug_uart.h>
15 #include <linux/compiler.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/hardware.h>
20 DECLARE_GLOBAL_DATA_PTR
;
22 #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
23 #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
24 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
26 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
27 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
28 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
29 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
31 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
34 u32 control
; /* 0x0 - Control Register [8:0] */
35 u32 mode
; /* 0x4 - Mode Register [10:0] */
37 u32 baud_rate_gen
; /* 0x18 - Baud Rate Generator [15:0] */
39 u32 channel_sts
; /* 0x2c - Channel Status [11:0] */
40 u32 tx_rx_fifo
; /* 0x30 - FIFO [15:0] or [7:0] */
41 u32 baud_rate_divider
; /* 0x34 - Baud Rate Divider [7:0] */
44 struct zynq_uart_priv
{
45 struct uart_zynq
*regs
;
48 /* Set up the baud rate in gd struct */
49 static void _uart_zynq_serial_setbrg(struct uart_zynq
*regs
,
50 unsigned long clock
, unsigned long baud
)
52 /* Calculation results. */
53 unsigned int calc_bauderror
, bdiv
, bgen
;
54 unsigned long calc_baud
= 0;
56 /* Covering case where input clock is so slow */
57 if (clock
< 1000000 && baud
> 4800)
61 * Baud rate = ------------------
64 * Find acceptable values for baud generation.
66 for (bdiv
= 4; bdiv
< 255; bdiv
++) {
67 bgen
= clock
/ (baud
* (bdiv
+ 1));
68 if (bgen
< 2 || bgen
> 65535)
71 calc_baud
= clock
/ (bgen
* (bdiv
+ 1));
74 * Use first calculated baudrate with
75 * an acceptable (<3%) error
78 calc_bauderror
= baud
- calc_baud
;
80 calc_bauderror
= calc_baud
- baud
;
81 if (((calc_bauderror
* 100) / baud
) < 3)
85 writel(bdiv
, ®s
->baud_rate_divider
);
86 writel(bgen
, ®s
->baud_rate_gen
);
89 /* Initialize the UART, with...some settings. */
90 static void _uart_zynq_serial_init(struct uart_zynq
*regs
)
92 /* RX/TX enabled & reset */
93 writel(ZYNQ_UART_CR_TX_EN
| ZYNQ_UART_CR_RX_EN
| ZYNQ_UART_CR_TXRST
| \
94 ZYNQ_UART_CR_RXRST
, ®s
->control
);
95 writel(ZYNQ_UART_MR_PARITY_NONE
, ®s
->mode
); /* 8 bit, no parity */
98 static int _uart_zynq_serial_putc(struct uart_zynq
*regs
, const char c
)
100 if (readl(®s
->channel_sts
) & ZYNQ_UART_SR_TXFULL
)
103 writel(c
, ®s
->tx_rx_fifo
);
108 int zynq_serial_setbrg(struct udevice
*dev
, int baudrate
)
110 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
111 unsigned long clock
= get_uart_clk(0);
113 _uart_zynq_serial_setbrg(priv
->regs
, clock
, baudrate
);
118 static int zynq_serial_probe(struct udevice
*dev
)
120 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
122 _uart_zynq_serial_init(priv
->regs
);
127 static int zynq_serial_getc(struct udevice
*dev
)
129 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
130 struct uart_zynq
*regs
= priv
->regs
;
132 if (readl(®s
->channel_sts
) & ZYNQ_UART_SR_RXEMPTY
)
135 return readl(®s
->tx_rx_fifo
);
138 static int zynq_serial_putc(struct udevice
*dev
, const char ch
)
140 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
142 return _uart_zynq_serial_putc(priv
->regs
, ch
);
145 static int zynq_serial_pending(struct udevice
*dev
, bool input
)
147 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
148 struct uart_zynq
*regs
= priv
->regs
;
151 return !(readl(®s
->channel_sts
) & ZYNQ_UART_SR_RXEMPTY
);
153 return !!(readl(®s
->channel_sts
) & ZYNQ_UART_SR_TXACTIVE
);
156 static int zynq_serial_ofdata_to_platdata(struct udevice
*dev
)
158 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
161 addr
= fdtdec_get_addr(gd
->fdt_blob
, dev
->of_offset
, "reg");
162 if (addr
== FDT_ADDR_T_NONE
)
165 priv
->regs
= (struct uart_zynq
*)addr
;
170 static const struct dm_serial_ops zynq_serial_ops
= {
171 .putc
= zynq_serial_putc
,
172 .pending
= zynq_serial_pending
,
173 .getc
= zynq_serial_getc
,
174 .setbrg
= zynq_serial_setbrg
,
177 static const struct udevice_id zynq_serial_ids
[] = {
178 { .compatible
= "xlnx,xuartps" },
179 { .compatible
= "cdns,uart-r1p8" },
183 U_BOOT_DRIVER(serial_s5p
) = {
184 .name
= "serial_zynq",
186 .of_match
= zynq_serial_ids
,
187 .ofdata_to_platdata
= zynq_serial_ofdata_to_platdata
,
188 .priv_auto_alloc_size
= sizeof(struct zynq_uart_priv
),
189 .probe
= zynq_serial_probe
,
190 .ops
= &zynq_serial_ops
,
191 .flags
= DM_FLAG_PRE_RELOC
,
194 #ifdef CONFIG_DEBUG_UART_ZYNQ
196 #include <debug_uart.h>
198 void _debug_uart_init(void)
200 struct uart_zynq
*regs
= (struct uart_zynq
*)CONFIG_DEBUG_UART_BASE
;
202 _uart_zynq_serial_init(regs
);
203 _uart_zynq_serial_setbrg(regs
, CONFIG_DEBUG_UART_CLOCK
,
207 static inline void _debug_uart_putc(int ch
)
209 struct uart_zynq
*regs
= (struct uart_zynq
*)CONFIG_DEBUG_UART_BASE
;
211 while (_uart_zynq_serial_putc(regs
, ch
) == -EAGAIN
)