2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <debug_uart.h>
16 #include <linux/compiler.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/hardware.h>
21 DECLARE_GLOBAL_DATA_PTR
;
23 #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
24 #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
25 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
27 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
28 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
29 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
30 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
32 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
35 u32 control
; /* 0x0 - Control Register [8:0] */
36 u32 mode
; /* 0x4 - Mode Register [10:0] */
38 u32 baud_rate_gen
; /* 0x18 - Baud Rate Generator [15:0] */
40 u32 channel_sts
; /* 0x2c - Channel Status [11:0] */
41 u32 tx_rx_fifo
; /* 0x30 - FIFO [15:0] or [7:0] */
42 u32 baud_rate_divider
; /* 0x34 - Baud Rate Divider [7:0] */
45 struct zynq_uart_priv
{
46 struct uart_zynq
*regs
;
49 /* Set up the baud rate in gd struct */
50 static void _uart_zynq_serial_setbrg(struct uart_zynq
*regs
,
51 unsigned long clock
, unsigned long baud
)
53 /* Calculation results. */
54 unsigned int calc_bauderror
, bdiv
, bgen
;
55 unsigned long calc_baud
= 0;
57 /* Covering case where input clock is so slow */
58 if (clock
< 1000000 && baud
> 4800)
62 * Baud rate = ------------------
65 * Find acceptable values for baud generation.
67 for (bdiv
= 4; bdiv
< 255; bdiv
++) {
68 bgen
= clock
/ (baud
* (bdiv
+ 1));
69 if (bgen
< 2 || bgen
> 65535)
72 calc_baud
= clock
/ (bgen
* (bdiv
+ 1));
75 * Use first calculated baudrate with
76 * an acceptable (<3%) error
79 calc_bauderror
= baud
- calc_baud
;
81 calc_bauderror
= calc_baud
- baud
;
82 if (((calc_bauderror
* 100) / baud
) < 3)
86 writel(bdiv
, ®s
->baud_rate_divider
);
87 writel(bgen
, ®s
->baud_rate_gen
);
90 /* Initialize the UART, with...some settings. */
91 static void _uart_zynq_serial_init(struct uart_zynq
*regs
)
93 /* RX/TX enabled & reset */
94 writel(ZYNQ_UART_CR_TX_EN
| ZYNQ_UART_CR_RX_EN
| ZYNQ_UART_CR_TXRST
| \
95 ZYNQ_UART_CR_RXRST
, ®s
->control
);
96 writel(ZYNQ_UART_MR_PARITY_NONE
, ®s
->mode
); /* 8 bit, no parity */
99 static int _uart_zynq_serial_putc(struct uart_zynq
*regs
, const char c
)
101 if (!(readl(®s
->channel_sts
) & ZYNQ_UART_SR_TXEMPTY
))
104 writel(c
, ®s
->tx_rx_fifo
);
109 int zynq_serial_setbrg(struct udevice
*dev
, int baudrate
)
111 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
114 #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
118 ret
= clk_get_by_index(dev
, 0, &clk
);
120 dev_err(dev
, "failed to get clock\n");
124 clock
= clk_get_rate(&clk
);
125 if (IS_ERR_VALUE(clock
)) {
126 dev_err(dev
, "failed to get rate\n");
129 debug("%s: CLK %ld\n", __func__
, clock
);
131 ret
= clk_enable(&clk
);
132 if (ret
&& ret
!= -ENOSYS
) {
133 dev_err(dev
, "failed to enable clock\n");
137 clock
= get_uart_clk(0);
139 _uart_zynq_serial_setbrg(priv
->regs
, clock
, baudrate
);
144 static int zynq_serial_probe(struct udevice
*dev
)
146 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
148 _uart_zynq_serial_init(priv
->regs
);
153 static int zynq_serial_getc(struct udevice
*dev
)
155 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
156 struct uart_zynq
*regs
= priv
->regs
;
158 if (readl(®s
->channel_sts
) & ZYNQ_UART_SR_RXEMPTY
)
161 return readl(®s
->tx_rx_fifo
);
164 static int zynq_serial_putc(struct udevice
*dev
, const char ch
)
166 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
168 return _uart_zynq_serial_putc(priv
->regs
, ch
);
171 static int zynq_serial_pending(struct udevice
*dev
, bool input
)
173 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
174 struct uart_zynq
*regs
= priv
->regs
;
177 return !(readl(®s
->channel_sts
) & ZYNQ_UART_SR_RXEMPTY
);
179 return !!(readl(®s
->channel_sts
) & ZYNQ_UART_SR_TXACTIVE
);
182 static int zynq_serial_ofdata_to_platdata(struct udevice
*dev
)
184 struct zynq_uart_priv
*priv
= dev_get_priv(dev
);
186 priv
->regs
= (struct uart_zynq
*)dev_get_addr(dev
);
191 static const struct dm_serial_ops zynq_serial_ops
= {
192 .putc
= zynq_serial_putc
,
193 .pending
= zynq_serial_pending
,
194 .getc
= zynq_serial_getc
,
195 .setbrg
= zynq_serial_setbrg
,
198 static const struct udevice_id zynq_serial_ids
[] = {
199 { .compatible
= "xlnx,xuartps" },
200 { .compatible
= "cdns,uart-r1p8" },
201 { .compatible
= "cdns,uart-r1p12" },
205 U_BOOT_DRIVER(serial_zynq
) = {
206 .name
= "serial_zynq",
208 .of_match
= zynq_serial_ids
,
209 .ofdata_to_platdata
= zynq_serial_ofdata_to_platdata
,
210 .priv_auto_alloc_size
= sizeof(struct zynq_uart_priv
),
211 .probe
= zynq_serial_probe
,
212 .ops
= &zynq_serial_ops
,
213 .flags
= DM_FLAG_PRE_RELOC
,
216 #ifdef CONFIG_DEBUG_UART_ZYNQ
217 static inline void _debug_uart_init(void)
219 struct uart_zynq
*regs
= (struct uart_zynq
*)CONFIG_DEBUG_UART_BASE
;
221 _uart_zynq_serial_init(regs
);
222 _uart_zynq_serial_setbrg(regs
, CONFIG_DEBUG_UART_CLOCK
,
226 static inline void _debug_uart_putc(int ch
)
228 struct uart_zynq
*regs
= (struct uart_zynq
*)CONFIG_DEBUG_UART_BASE
;
230 while (_uart_zynq_serial_putc(regs
, ch
) == -EAGAIN
)