1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
68 #ifdef CONFIG_DRIVER_SMC91111
70 /* Use power-down feature of the chip */
78 static const char version
[] =
79 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
82 /* Autonegotiation timeout in seconds */
83 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
84 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
87 /*------------------------------------------------------------------------
89 . Configuration options, for the experienced user to change.
91 -------------------------------------------------------------------------*/
94 . Wait time for memory to be free. This probably shouldn't be
95 . tuned that much, as waiting for this means nothing else happens
98 #define MEMORY_WAIT_TIME 16
102 #define PRINTK3(args...) printf(args)
104 #define PRINTK3(args...)
108 #define PRINTK2(args...) printf(args)
110 #define PRINTK2(args...)
114 #define PRINTK(args...) printf(args)
116 #define PRINTK(args...)
120 /*------------------------------------------------------------------------
122 . The internal workings of the driver. If you are changing anything
123 . here with the SMC stuff, you should have the datasheet and know
124 . what you are doing.
126 -------------------------------------------------------------------------*/
127 #define CARDNAME "LAN91C111"
129 /* Memory sizing constant */
130 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
132 #ifndef CONFIG_SMC91111_BASE
133 #define CONFIG_SMC91111_BASE 0x20000300
136 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
138 #define SMC_DEV_NAME "SMC91111"
139 #define SMC_PHY_ADDR 0x0000
140 #define SMC_ALLOC_MAX_TRY 5
141 #define SMC_TX_TIMEOUT 30
143 #define SMC_PHY_CLOCK_DELAY 1000
147 #ifdef CONFIG_SMC_USE_32_BIT
152 /*-----------------------------------------------------------------
154 . The driver can be entered at any of the following entry points.
156 .------------------------------------------------------------------ */
158 extern int eth_init(bd_t
*bd
);
159 extern void eth_halt(void);
160 extern int eth_rx(void);
161 extern int eth_send(volatile void *packet
, int length
);
163 #ifdef SHARED_RESOURCES
164 extern void swap_to(int device_id
);
168 . This is called by register_netdev(). It is responsible for
169 . checking the portlist for the SMC9000 series chipset. If it finds
170 . one, then it will initialize the device, find the hardware information,
171 . and sets up the appropriate device parameters.
172 . NOTE: Interrupts are *OFF* when this procedure is called.
174 . NB:This shouldn't be static since it is referred to externally.
179 . This is called by unregister_netdev(). It is responsible for
180 . cleaning up before the driver is finally unregistered and discarded.
182 void smc_destructor(void);
185 . The kernel calls this function when someone wants to use the device,
186 . typically 'ifconfig ethX up'.
188 static int smc_open(bd_t
*bd
);
192 . This is called by the kernel in response to 'ifconfig ethX down'. It
193 . is responsible for cleaning up everything that the open routine
194 . does, and maybe putting the card into a powerdown state.
196 static int smc_close(void);
199 . Configures the PHY through the MII Management interface
201 #ifndef CONFIG_SMC91111_EXT_PHY
202 static void smc_phy_configure(void);
203 #endif /* !CONFIG_SMC91111_EXT_PHY */
206 . This is a separate procedure to handle the receipt of a packet, to
207 . leave the interrupt code looking slightly cleaner
209 static int smc_rcv(void);
211 /* See if a MAC address is defined in the current environment. If so use it. If not
212 . print a warning and set the environment and other globals with the default.
213 . If an EEPROM is present it really should be consulted.
215 int smc_get_ethaddr(bd_t
*bd
);
216 int get_rom_mac(uchar
*v_rom_mac
);
219 ------------------------------------------------------------
223 ------------------------------------------------------------
226 #ifdef CONFIG_SMC_USE_IOFUNCS
228 * input and output functions
230 * Implemented due to inx,outx macros accessing the device improperly
231 * and putting the device into an unkown state.
233 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
234 * could not be free'd (hence the alloc failures), duplicate packets,
235 * packets being corrupt (shifted) on the wire, etc. Switching to the
236 * inx,outx functions fixed this problem.
238 static inline word
SMC_inw(dword offset
);
239 static inline void SMC_outw(word value
, dword offset
);
240 static inline byte
SMC_inb(dword offset
);
241 static inline void SMC_outb(byte value
, dword offset
);
242 static inline void SMC_insw(dword offset
, volatile uchar
* buf
, dword len
);
243 static inline void SMC_outsw(dword offset
, uchar
* buf
, dword len
);
245 #define barrier() __asm__ __volatile__("": : :"memory")
247 static inline word
SMC_inw(dword offset
)
250 v
= *((volatile word
*)(SMC_BASE_ADDRESS
+offset
));
251 barrier(); *(volatile u32
*)(0xc0000000);
255 static inline void SMC_outw(word value
, dword offset
)
257 *((volatile word
*)(SMC_BASE_ADDRESS
+offset
)) = value
;
258 barrier(); *(volatile u32
*)(0xc0000000);
261 static inline byte
SMC_inb(dword offset
)
265 _w
= SMC_inw(offset
& ~((dword
)1));
266 return (offset
& 1) ? (byte
)(_w
>> 8) : (byte
)(_w
);
269 static inline void SMC_outb(byte value
, dword offset
)
273 _w
= SMC_inw(offset
& ~((dword
)1));
275 *((volatile word
*)(SMC_BASE_ADDRESS
+(offset
& ~((dword
)1)))) = (value
<<8) | (_w
& 0x00ff);
277 *((volatile word
*)(SMC_BASE_ADDRESS
+offset
)) = value
| (_w
& 0xff00);
280 static inline void SMC_insw(dword offset
, volatile uchar
* buf
, dword len
)
282 volatile word
*p
= (volatile word
*)buf
;
285 *p
++ = SMC_inw(offset
);
287 *((volatile u32
*)(0xc0000000));
291 static inline void SMC_outsw(dword offset
, uchar
* buf
, dword len
)
293 volatile word
*p
= (volatile word
*)buf
;
296 SMC_outw(*p
++, offset
);
298 *(volatile u32
*)(0xc0000000);
301 #endif /* CONFIG_SMC_USE_IOFUNCS */
303 static char unsigned smc_mac_addr
[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
306 * This function must be called before smc_open() if you want to override
307 * the default mac address.
310 void smc_set_mac_addr(const unsigned char *addr
) {
313 for (i
=0; i
< sizeof(smc_mac_addr
); i
++){
314 smc_mac_addr
[i
] = addr
[i
];
319 * smc_get_macaddr is no longer used. If you want to override the default
320 * mac address, call smc_get_mac_addr as a part of the board initialization.
324 void smc_get_macaddr( byte
*addr
) {
325 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
326 unsigned char *dnp1110_mac
= (unsigned char *) (0xE8000000 + 0x20010);
330 for (i
=0; i
<6; i
++) {
331 addr
[0] = *(dnp1110_mac
+0);
332 addr
[1] = *(dnp1110_mac
+1);
333 addr
[2] = *(dnp1110_mac
+2);
334 addr
[3] = *(dnp1110_mac
+3);
335 addr
[4] = *(dnp1110_mac
+4);
336 addr
[5] = *(dnp1110_mac
+5);
341 /***********************************************
342 * Show available memory *
343 ***********************************************/
344 void dump_memory_info(void)
349 old_bank
= SMC_inw(BANK_SELECT
)&0xF;
352 mem_info
= SMC_inw( MIR_REG
);
353 PRINTK2("Memory: %4d available\n", (mem_info
>> 8)*2048);
355 SMC_SELECT_BANK(old_bank
);
358 . A rather simple routine to print out a packet for debugging purposes.
361 static void print_packet( byte
*, int );
364 #define tx_done(dev) 1
367 /* this does a soft reset on the device */
368 static void smc_reset( void );
370 /* Enable Interrupts, Receive, and Transmit */
371 static void smc_enable( void );
373 /* this puts the device in an inactive state */
374 static void smc_shutdown( void );
376 /* Routines to Read and Write the PHY Registers across the
377 MII Management Interface
380 #ifndef CONFIG_SMC91111_EXT_PHY
381 static word
smc_read_phy_register(byte phyreg
);
382 static void smc_write_phy_register(byte phyreg
, word phydata
);
383 #endif /* !CONFIG_SMC91111_EXT_PHY */
386 static int poll4int (byte mask
, int timeout
)
388 int tmo
= get_timer (0) + timeout
* CFG_HZ
;
390 word old_bank
= SMC_inw (BSR_REG
);
392 PRINTK2 ("Polling...\n");
394 while ((SMC_inw (SMC91111_INT_REG
) & mask
) == 0) {
395 if (get_timer (0) >= tmo
) {
401 /* restore old bank selection */
402 SMC_SELECT_BANK (old_bank
);
410 /* Only one release command at a time, please */
411 static inline void smc_wait_mmu_release_complete (void)
415 /* assume bank 2 selected */
416 while (SMC_inw (MMU_CMD_REG
) & MC_BUSY
) {
417 udelay (1); /* Wait until not busy */
424 . Function: smc_reset( void )
426 . This sets the SMC91111 chip to its normal state, hopefully from whatever
427 . mess that any other DOS driver has put it in.
429 . Maybe I should reset more registers to defaults in here? SOFTRST should
433 . 1. send a SOFT RESET
434 . 2. wait for it to finish
435 . 3. enable autorelease mode
436 . 4. reset the memory management unit
437 . 5. clear all interrupts
440 static void smc_reset (void)
442 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME
);
444 /* This resets the registers mostly to defaults, but doesn't
445 affect EEPROM. That seems unnecessary */
447 SMC_outw (RCR_SOFTRST
, RCR_REG
);
449 /* Setup the Configuration Register */
450 /* This is necessary because the CONFIG_REG is not affected */
451 /* by a soft reset */
454 #if defined(CONFIG_SMC91111_EXT_PHY)
455 SMC_outw (CONFIG_DEFAULT
| CONFIG_EXT_PHY
, CONFIG_REG
);
457 SMC_outw (CONFIG_DEFAULT
, CONFIG_REG
);
461 /* Release from possible power-down state */
462 /* Configuration register is not affected by Soft Reset */
463 SMC_outw (SMC_inw (CONFIG_REG
) | CONFIG_EPH_POWER_EN
, CONFIG_REG
);
467 /* this should pause enough for the chip to be happy */
470 /* Disable transmit and receive functionality */
471 SMC_outw (RCR_CLEAR
, RCR_REG
);
472 SMC_outw (TCR_CLEAR
, TCR_REG
);
474 /* set the control register */
476 SMC_outw (CTL_DEFAULT
, CTL_REG
);
480 smc_wait_mmu_release_complete ();
481 SMC_outw (MC_RESET
, MMU_CMD_REG
);
482 while (SMC_inw (MMU_CMD_REG
) & MC_BUSY
)
483 udelay (1); /* Wait until not busy */
485 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
486 but this is a place where future chipsets _COULD_ break. Be wary
487 of issuing another MMU command right after this */
489 /* Disable all interrupts */
490 SMC_outb (0, IM_REG
);
494 . Function: smc_enable
495 . Purpose: let the chip talk to the outside work
497 . 1. Enable the transmitter
498 . 2. Enable the receiver
499 . 3. Enable interrupts
501 static void smc_enable()
503 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME
);
504 SMC_SELECT_BANK( 0 );
505 /* see the header file for options in TCR/RCR DEFAULT*/
506 SMC_outw( TCR_DEFAULT
, TCR_REG
);
507 SMC_outw( RCR_DEFAULT
, RCR_REG
);
510 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
514 . Function: smc_shutdown
515 . Purpose: closes down the SMC91xxx chip.
517 . 1. zero the interrupt mask
518 . 2. clear the enable receive flag
519 . 3. clear the enable xmit flags
522 . (1) maybe utilize power down mode.
523 . Why not yet? Because while the chip will go into power down mode,
524 . the manual says that it will wake up in response to any I/O requests
525 . in the register space. Empirical results do not show this working.
527 static void smc_shutdown()
529 PRINTK2(CARDNAME
": smc_shutdown\n");
531 /* no more interrupts for me */
532 SMC_SELECT_BANK( 2 );
533 SMC_outb( 0, IM_REG
);
535 /* and tell the card to stay away from that nasty outside world */
536 SMC_SELECT_BANK( 0 );
537 SMC_outb( RCR_CLEAR
, RCR_REG
);
538 SMC_outb( TCR_CLEAR
, TCR_REG
);
539 #ifdef SHARED_RESOURCES
546 . Function: smc_hardware_send_packet(struct net_device * )
548 . This sends the actual packet to the SMC9xxx chip.
551 . First, see if a saved_skb is available.
552 . ( this should NOT be called if there is no 'saved_skb'
553 . Now, find the packet number that the chip allocated
554 . Point the data pointers at it in memory
555 . Set the length word in the chip's memory
556 . Dump the packet to chip memory
557 . Check if a last byte is needed ( odd length packet )
558 . if so, set the control flag right
559 . Tell the card to send it
560 . Enable the transmit interrupt, so I know if it failed
561 . Free the kernel data if I actually sent it.
563 static int smc_send_packet (volatile void *packet
, int packet_length
)
566 unsigned long ioaddr
;
576 /* save PTR and PNR registers before manipulation */
578 saved_pnr
= SMC_inb( PN_REG
);
579 saved_ptr
= SMC_inw( PTR_REG
);
581 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME
);
583 length
= ETH_ZLEN
< packet_length
? packet_length
: ETH_ZLEN
;
586 ** The MMU wants the number of pages to be the number of 256 bytes
587 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
589 ** The 91C111 ignores the size bits, but the code is left intact
590 ** for backwards and future compatibility.
592 ** Pkt size for allocating is data length +6 (for additional status
593 ** words, length and ctl!)
595 ** If odd size then last byte is included in this header.
597 numPages
= ((length
& 0xfffe) + 6);
598 numPages
>>= 8; /* Divide by 256 */
601 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME
);
605 /* now, try to allocate the memory */
607 SMC_outw (MC_ALLOC
| numPages
, MMU_CMD_REG
);
609 /* FIXME: the ALLOC_INT bit never gets set *
610 * so the following will always give a *
611 * memory allocation error. *
612 * same code works in armboot though *
618 time_out
= MEMORY_WAIT_TIME
;
620 status
= SMC_inb (SMC91111_INT_REG
);
621 if (status
& IM_ALLOC_INT
) {
622 /* acknowledge the interrupt */
623 SMC_outb (IM_ALLOC_INT
, SMC91111_INT_REG
);
626 } while (--time_out
);
629 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
631 if (try < SMC_ALLOC_MAX_TRY
)
637 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
640 /* I can send the packet now.. */
642 ioaddr
= SMC_BASE_ADDRESS
;
644 buf
= (byte
*) packet
;
646 /* If I get here, I _know_ there is a packet slot waiting for me */
647 packet_no
= SMC_inb (AR_REG
);
648 if (packet_no
& AR_FAILED
) {
649 /* or isn't there? BAD CHIP! */
650 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME
);
654 /* we have a packet address, so tell the card to use it */
655 #ifndef CONFIG_XAENIAX
656 SMC_outb (packet_no
, PN_REG
);
658 /* On Xaeniax board, we can't use SMC_outb here because that way
659 * the Allocate MMU command will end up written to the command register
660 * as well, which will lead to a problem.
662 SMC_outl (packet_no
<< 16, 0);
664 /* do not write new ptr value if Write data fifo not empty */
665 while ( saved_ptr
& PTR_NOTEMPTY
)
666 printf ("Write data fifo not empty!\n");
668 /* point to the beginning of the packet */
669 SMC_outw (PTR_AUTOINC
, PTR_REG
);
671 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
672 SMC_DEV_NAME
, length
);
675 printf ("Transmitting Packet\n");
676 print_packet (buf
, length
);
679 /* send the packet length ( +6 for status, length and ctl byte )
680 and the status word ( set to zeros ) */
682 SMC_outl ((length
+ 6) << 16, SMC91111_DATA_REG
);
684 SMC_outw (0, SMC91111_DATA_REG
);
685 /* send the packet length ( +6 for status words, length, and ctl */
686 SMC_outw ((length
+ 6), SMC91111_DATA_REG
);
689 /* send the actual data
690 . I _think_ it's faster to send the longs first, and then
691 . mop up by sending the last word. It depends heavily
692 . on alignment, at least on the 486. Maybe it would be
693 . a good idea to check which is optimal? But that could take
694 . almost as much time as is saved?
697 SMC_outsl (SMC91111_DATA_REG
, buf
, length
>> 2);
698 #ifndef CONFIG_XAENIAX
700 SMC_outw (*((word
*) (buf
+ (length
& 0xFFFFFFFC))),
703 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
704 * unaligned tail part specially. The standard code doesn't work.
706 if ((length
& 3) == 3) {
707 u16
* ptr
= (u16
*) &buf
[length
-3];
708 SMC_outl((*ptr
) | ((0x2000 | buf
[length
-1]) << 16),
710 } else if ((length
& 2) == 2) {
711 u16
* ptr
= (u16
*) &buf
[length
-2];
712 SMC_outl(*ptr
, SMC91111_DATA_REG
);
713 } else if (length
& 1) {
714 SMC_outl((0x2000 | buf
[length
-1]), SMC91111_DATA_REG
);
716 SMC_outl(0, SMC91111_DATA_REG
);
720 SMC_outsw (SMC91111_DATA_REG
, buf
, (length
) >> 1);
721 #endif /* USE_32_BIT */
723 #ifndef CONFIG_XAENIAX
724 /* Send the last byte, if there is one. */
725 if ((length
& 1) == 0) {
726 SMC_outw (0, SMC91111_DATA_REG
);
728 SMC_outw (buf
[length
- 1] | 0x2000, SMC91111_DATA_REG
);
732 /* and let the chipset deal with it */
733 SMC_outw (MC_ENQUEUE
, MMU_CMD_REG
);
735 /* poll for TX INT */
736 /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
737 /* poll for TX_EMPTY INT - autorelease enabled */
738 if (poll4int(IM_TX_EMPTY_INT
, SMC_TX_TIMEOUT
)) {
740 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME
);
743 /* no need to release, MMU does that now */
744 #ifdef CONFIG_XAENIAX
745 SMC_outw (MC_FREEPKT
, MMU_CMD_REG
);
748 /* wait for MMU getting ready (low) */
749 while (SMC_inw (MMU_CMD_REG
) & MC_BUSY
) {
753 PRINTK2 ("MMU ready\n");
759 SMC_outb (IM_TX_EMPTY_INT
, SMC91111_INT_REG
);
760 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
761 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME
,
765 /* no need to release, MMU does that now */
766 #ifdef CONFIG_XAENIAX
767 SMC_outw (MC_FREEPKT
, MMU_CMD_REG
);
770 /* wait for MMU getting ready (low) */
771 while (SMC_inw (MMU_CMD_REG
) & MC_BUSY
) {
775 PRINTK2 ("MMU ready\n");
780 /* restore previously saved registers */
781 #ifndef CONFIG_XAENIAX
782 SMC_outb( saved_pnr
, PN_REG
);
784 /* On Xaeniax board, we can't use SMC_outb here because that way
785 * the Allocate MMU command will end up written to the command register
786 * as well, which will lead to a problem.
788 SMC_outl(saved_pnr
<< 16, 0);
790 SMC_outw( saved_ptr
, PTR_REG
);
795 /*-------------------------------------------------------------------------
797 | smc_destructor( struct net_device * dev )
799 | dev, pointer to the device structure
804 ---------------------------------------------------------------------------
806 void smc_destructor()
808 PRINTK2(CARDNAME
": smc_destructor\n");
813 * Open and Initialize the board
815 * Set up everything, reset the card, etc ..
818 static int smc_open (bd_t
* bd
)
822 PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME
);
824 /* reset the hardware */
828 /* Configure the PHY */
829 #ifndef CONFIG_SMC91111_EXT_PHY
830 smc_phy_configure ();
833 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
834 /* SMC_SELECT_BANK(0); */
835 /* SMC_outw(0, RPC_REG); */
838 err
= smc_get_ethaddr (bd
); /* set smc_mac_addr, and sync it with u-boot globals */
840 memset (bd
->bi_enetaddr
, 0, 6); /* hack to make error stick! upper code will abort if not set */
841 return (-1); /* upper code ignores this, but NOT bi_enetaddr */
844 for (i
= 0; i
< 6; i
+= 2) {
847 address
= smc_mac_addr
[i
+ 1] << 8;
848 address
|= smc_mac_addr
[i
];
849 SMC_outw (address
, (ADDR0_REG
+ i
));
852 for (i
= 0; i
< 6; i
++)
853 SMC_outb (smc_mac_addr
[i
], (ADDR0_REG
+ i
));
859 /*-------------------------------------------------------------
861 . smc_rcv - receive a packet from the card
863 . There is ( at least ) a packet waiting to be read from
867 . o If an error, record it
868 . o otherwise, read in the packet
869 --------------------------------------------------------------
884 /* save PTR and PTR registers */
885 saved_pnr
= SMC_inb( PN_REG
);
886 saved_ptr
= SMC_inw( PTR_REG
);
888 packet_number
= SMC_inw( RXFIFO_REG
);
890 if ( packet_number
& RXFIFO_REMPTY
) {
895 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME
);
896 /* start reading from the start of the packet */
897 SMC_outw( PTR_READ
| PTR_RCV
| PTR_AUTOINC
, PTR_REG
);
899 /* First two words are status and packet_length */
901 stat_len
= SMC_inl(SMC91111_DATA_REG
);
902 status
= stat_len
& 0xffff;
903 packet_length
= stat_len
>> 16;
905 status
= SMC_inw( SMC91111_DATA_REG
);
906 packet_length
= SMC_inw( SMC91111_DATA_REG
);
909 packet_length
&= 0x07ff; /* mask off top bits */
911 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status
, packet_length
);
913 if ( !(status
& RS_ERRORS
) ){
914 /* Adjust for having already read the first two words */
915 packet_length
-= 4; /*4; */
918 /* set odd length for bug in LAN91C111, */
919 /* which never sets RS_ODDFRAME */
924 PRINTK3(" Reading %d dwords (and %d bytes) \n",
925 packet_length
>> 2, packet_length
& 3 );
926 /* QUESTION: Like in the TX routine, do I want
927 to send the DWORDs or the bytes first, or some
928 mixture. A mixture might improve already slow PIO
930 SMC_insl( SMC91111_DATA_REG
, NetRxPackets
[0], packet_length
>> 2 );
931 /* read the left over bytes */
932 if (packet_length
& 3) {
935 byte
*tail
= (byte
*)(NetRxPackets
[0] + (packet_length
& ~3));
936 dword leftover
= SMC_inl(SMC91111_DATA_REG
);
937 for (i
=0; i
<(packet_length
& 3); i
++)
938 *tail
++ = (byte
) (leftover
>> (8*i
)) & 0xff;
941 PRINTK3(" Reading %d words and %d byte(s) \n",
942 (packet_length
>> 1 ), packet_length
& 1 );
943 SMC_insw(SMC91111_DATA_REG
, NetRxPackets
[0], packet_length
>> 1);
945 #endif /* USE_32_BIT */
948 printf("Receiving Packet\n");
949 print_packet( NetRxPackets
[0], packet_length
);
957 while ( SMC_inw( MMU_CMD_REG
) & MC_BUSY
)
958 udelay(1); /* Wait until not busy */
960 /* error or good, tell the card to get rid of this packet */
961 SMC_outw( MC_RELEASE
, MMU_CMD_REG
);
963 while ( SMC_inw( MMU_CMD_REG
) & MC_BUSY
)
964 udelay(1); /* Wait until not busy */
966 /* restore saved registers */
967 #ifndef CONFIG_XAENIAX
968 SMC_outb( saved_pnr
, PN_REG
);
970 /* On Xaeniax board, we can't use SMC_outb here because that way
971 * the Allocate MMU command will end up written to the command register
972 * as well, which will lead to a problem.
974 SMC_outl( saved_pnr
<< 16, 0);
976 SMC_outw( saved_ptr
, PTR_REG
);
979 /* Pass the packet up to the protocol layers. */
980 NetReceive(NetRxPackets
[0], packet_length
);
981 return packet_length
;
989 /*----------------------------------------------------
992 . this makes the board clean up everything that it can
993 . and not talk to the outside world. Caused by
994 . an 'ifconfig ethX down'
996 -----------------------------------------------------*/
997 static int smc_close()
999 PRINTK2("%s: smc_close\n", SMC_DEV_NAME
);
1001 /* clear everything */
1009 /*------------------------------------------------------------
1010 . Modify a bit in the LAN91C111 register set
1011 .-------------------------------------------------------------*/
1012 static word
smc_modify_regbit(int bank
, int ioaddr
, int reg
,
1013 unsigned int bit
, int val
)
1017 SMC_SELECT_BANK( bank
);
1019 regval
= SMC_inw( reg
);
1025 SMC_outw( regval
, 0 );
1030 /*------------------------------------------------------------
1031 . Retrieve a bit in the LAN91C111 register set
1032 .-------------------------------------------------------------*/
1033 static int smc_get_regbit(int bank
, int ioaddr
, int reg
, unsigned int bit
)
1035 SMC_SELECT_BANK( bank
);
1036 if ( SMC_inw( reg
) & bit
)
1043 /*------------------------------------------------------------
1044 . Modify a LAN91C111 register (word access only)
1045 .-------------------------------------------------------------*/
1046 static void smc_modify_reg(int bank
, int ioaddr
, int reg
, word val
)
1048 SMC_SELECT_BANK( bank
);
1049 SMC_outw( val
, reg
);
1053 /*------------------------------------------------------------
1054 . Retrieve a LAN91C111 register (word access only)
1055 .-------------------------------------------------------------*/
1056 static int smc_get_reg(int bank
, int ioaddr
, int reg
)
1058 SMC_SELECT_BANK( bank
);
1059 return(SMC_inw( reg
));
1064 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
1066 #if (SMC_DEBUG > 2 )
1068 /*------------------------------------------------------------
1069 . Debugging function for viewing MII Management serial bitstream
1070 .-------------------------------------------------------------*/
1071 static void smc_dump_mii_stream (byte
* bits
, int size
)
1076 for (i
= 0; i
< size
; ++i
) {
1077 printf ("%d", i
% 10);
1081 for (i
= 0; i
< size
; ++i
) {
1082 if (bits
[i
] & MII_MDOE
)
1089 for (i
= 0; i
< size
; ++i
) {
1090 if (bits
[i
] & MII_MDO
)
1097 for (i
= 0; i
< size
; ++i
) {
1098 if (bits
[i
] & MII_MDI
)
1108 /*------------------------------------------------------------
1109 . Reads a register from the MII Management serial interface
1110 .-------------------------------------------------------------*/
1111 #ifndef CONFIG_SMC91111_EXT_PHY
1112 static word
smc_read_phy_register (byte phyreg
)
1122 byte phyaddr
= SMC_PHY_ADDR
;
1124 /* 32 consecutive ones on MDO to establish sync */
1125 for (i
= 0; i
< 32; ++i
)
1126 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1128 /* Start code <01> */
1129 bits
[clk_idx
++] = MII_MDOE
;
1130 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1132 /* Read command <10> */
1133 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1134 bits
[clk_idx
++] = MII_MDOE
;
1136 /* Output the PHY address, msb first */
1138 for (i
= 0; i
< 5; ++i
) {
1140 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1142 bits
[clk_idx
++] = MII_MDOE
;
1144 /* Shift to next lowest bit */
1148 /* Output the phy register number, msb first */
1150 for (i
= 0; i
< 5; ++i
) {
1152 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1154 bits
[clk_idx
++] = MII_MDOE
;
1156 /* Shift to next lowest bit */
1160 /* Tristate and turnaround (2 bit times) */
1161 bits
[clk_idx
++] = 0;
1162 /*bits[clk_idx++] = 0; */
1164 /* Input starts at this bit time */
1165 input_idx
= clk_idx
;
1167 /* Will input 16 bits */
1168 for (i
= 0; i
< 16; ++i
)
1169 bits
[clk_idx
++] = 0;
1171 /* Final clock bit */
1172 bits
[clk_idx
++] = 0;
1174 /* Save the current bank */
1175 oldBank
= SMC_inw (BANK_SELECT
);
1178 SMC_SELECT_BANK (3);
1180 /* Get the current MII register value */
1181 mii_reg
= SMC_inw (MII_REG
);
1183 /* Turn off all MII Interface bits */
1184 mii_reg
&= ~(MII_MDOE
| MII_MCLK
| MII_MDI
| MII_MDO
);
1186 /* Clock all 64 cycles */
1187 for (i
= 0; i
< sizeof bits
; ++i
) {
1188 /* Clock Low - output data */
1189 SMC_outw (mii_reg
| bits
[i
], MII_REG
);
1190 udelay (SMC_PHY_CLOCK_DELAY
);
1193 /* Clock Hi - input data */
1194 SMC_outw (mii_reg
| bits
[i
] | MII_MCLK
, MII_REG
);
1195 udelay (SMC_PHY_CLOCK_DELAY
);
1196 bits
[i
] |= SMC_inw (MII_REG
) & MII_MDI
;
1199 /* Return to idle state */
1200 /* Set clock to low, data to low, and output tristated */
1201 SMC_outw (mii_reg
, MII_REG
);
1202 udelay (SMC_PHY_CLOCK_DELAY
);
1204 /* Restore original bank select */
1205 SMC_SELECT_BANK (oldBank
);
1207 /* Recover input data */
1209 for (i
= 0; i
< 16; ++i
) {
1212 if (bits
[input_idx
++] & MII_MDI
)
1216 #if (SMC_DEBUG > 2 )
1217 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1218 phyaddr
, phyreg
, phydata
);
1219 smc_dump_mii_stream (bits
, sizeof bits
);
1226 /*------------------------------------------------------------
1227 . Writes a register to the MII Management serial interface
1228 .-------------------------------------------------------------*/
1229 static void smc_write_phy_register (byte phyreg
, word phydata
)
1237 byte phyaddr
= SMC_PHY_ADDR
;
1239 /* 32 consecutive ones on MDO to establish sync */
1240 for (i
= 0; i
< 32; ++i
)
1241 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1243 /* Start code <01> */
1244 bits
[clk_idx
++] = MII_MDOE
;
1245 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1247 /* Write command <01> */
1248 bits
[clk_idx
++] = MII_MDOE
;
1249 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1251 /* Output the PHY address, msb first */
1253 for (i
= 0; i
< 5; ++i
) {
1255 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1257 bits
[clk_idx
++] = MII_MDOE
;
1259 /* Shift to next lowest bit */
1263 /* Output the phy register number, msb first */
1265 for (i
= 0; i
< 5; ++i
) {
1267 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1269 bits
[clk_idx
++] = MII_MDOE
;
1271 /* Shift to next lowest bit */
1275 /* Tristate and turnaround (2 bit times) */
1276 bits
[clk_idx
++] = 0;
1277 bits
[clk_idx
++] = 0;
1279 /* Write out 16 bits of data, msb first */
1281 for (i
= 0; i
< 16; ++i
) {
1283 bits
[clk_idx
++] = MII_MDOE
| MII_MDO
;
1285 bits
[clk_idx
++] = MII_MDOE
;
1287 /* Shift to next lowest bit */
1291 /* Final clock bit (tristate) */
1292 bits
[clk_idx
++] = 0;
1294 /* Save the current bank */
1295 oldBank
= SMC_inw (BANK_SELECT
);
1298 SMC_SELECT_BANK (3);
1300 /* Get the current MII register value */
1301 mii_reg
= SMC_inw (MII_REG
);
1303 /* Turn off all MII Interface bits */
1304 mii_reg
&= ~(MII_MDOE
| MII_MCLK
| MII_MDI
| MII_MDO
);
1306 /* Clock all cycles */
1307 for (i
= 0; i
< sizeof bits
; ++i
) {
1308 /* Clock Low - output data */
1309 SMC_outw (mii_reg
| bits
[i
], MII_REG
);
1310 udelay (SMC_PHY_CLOCK_DELAY
);
1313 /* Clock Hi - input data */
1314 SMC_outw (mii_reg
| bits
[i
] | MII_MCLK
, MII_REG
);
1315 udelay (SMC_PHY_CLOCK_DELAY
);
1316 bits
[i
] |= SMC_inw (MII_REG
) & MII_MDI
;
1319 /* Return to idle state */
1320 /* Set clock to low, data to low, and output tristated */
1321 SMC_outw (mii_reg
, MII_REG
);
1322 udelay (SMC_PHY_CLOCK_DELAY
);
1324 /* Restore original bank select */
1325 SMC_SELECT_BANK (oldBank
);
1327 #if (SMC_DEBUG > 2 )
1328 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1329 phyaddr
, phyreg
, phydata
);
1330 smc_dump_mii_stream (bits
, sizeof bits
);
1333 #endif /* !CONFIG_SMC91111_EXT_PHY */
1336 /*------------------------------------------------------------
1337 . Waits the specified number of milliseconds - kernel friendly
1338 .-------------------------------------------------------------*/
1339 #ifndef CONFIG_SMC91111_EXT_PHY
1340 static void smc_wait_ms(unsigned int ms
)
1344 #endif /* !CONFIG_SMC91111_EXT_PHY */
1347 /*------------------------------------------------------------
1348 . Configures the specified PHY using Autonegotiation. Calls
1349 . smc_phy_fixed() if the user has requested a certain config.
1350 .-------------------------------------------------------------*/
1351 #ifndef CONFIG_SMC91111_EXT_PHY
1352 static void smc_phy_configure ()
1356 word my_phy_caps
; /* My PHY capabilities */
1357 word my_ad_caps
; /* My Advertised capabilities */
1358 word status
= 0; /*;my status = 0 */
1361 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME
);
1364 /* Get the detected phy address */
1365 phyaddr
= SMC_PHY_ADDR
;
1367 /* Reset the PHY, setting all other bits to zero */
1368 smc_write_phy_register (PHY_CNTL_REG
, PHY_CNTL_RST
);
1370 /* Wait for the reset to complete, or time out */
1371 timeout
= 6; /* Wait up to 3 seconds */
1373 if (!(smc_read_phy_register (PHY_CNTL_REG
)
1375 /* reset complete */
1379 smc_wait_ms (500); /* wait 500 millisecs */
1383 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME
);
1384 goto smc_phy_configure_exit
;
1387 /* Read PHY Register 18, Status Output */
1388 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1390 /* Enable PHY Interrupts (for register 18) */
1391 /* Interrupts listed here are disabled */
1392 smc_write_phy_register (PHY_MASK_REG
, 0xffff);
1394 /* Configure the Receive/Phy Control register */
1395 SMC_SELECT_BANK (0);
1396 SMC_outw (RPC_DEFAULT
, RPC_REG
);
1398 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1399 my_phy_caps
= smc_read_phy_register (PHY_STAT_REG
);
1400 my_ad_caps
= PHY_AD_CSMA
; /* I am CSMA capable */
1402 if (my_phy_caps
& PHY_STAT_CAP_T4
)
1403 my_ad_caps
|= PHY_AD_T4
;
1405 if (my_phy_caps
& PHY_STAT_CAP_TXF
)
1406 my_ad_caps
|= PHY_AD_TX_FDX
;
1408 if (my_phy_caps
& PHY_STAT_CAP_TXH
)
1409 my_ad_caps
|= PHY_AD_TX_HDX
;
1411 if (my_phy_caps
& PHY_STAT_CAP_TF
)
1412 my_ad_caps
|= PHY_AD_10_FDX
;
1414 if (my_phy_caps
& PHY_STAT_CAP_TH
)
1415 my_ad_caps
|= PHY_AD_10_HDX
;
1417 /* Update our Auto-Neg Advertisement Register */
1418 smc_write_phy_register (PHY_AD_REG
, my_ad_caps
);
1420 /* Read the register back. Without this, it appears that when */
1421 /* auto-negotiation is restarted, sometimes it isn't ready and */
1422 /* the link does not come up. */
1423 smc_read_phy_register(PHY_AD_REG
);
1425 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME
, my_phy_caps
);
1426 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME
, my_ad_caps
);
1428 /* Restart auto-negotiation process in order to advertise my caps */
1429 smc_write_phy_register (PHY_CNTL_REG
,
1430 PHY_CNTL_ANEG_EN
| PHY_CNTL_ANEG_RST
);
1432 /* Wait for the auto-negotiation to complete. This may take from */
1433 /* 2 to 3 seconds. */
1434 /* Wait for the reset to complete, or time out */
1435 timeout
= CONFIG_SMC_AUTONEG_TIMEOUT
* 2;
1438 status
= smc_read_phy_register (PHY_STAT_REG
);
1439 if (status
& PHY_STAT_ANEG_ACK
) {
1440 /* auto-negotiate complete */
1444 smc_wait_ms (500); /* wait 500 millisecs */
1446 /* Restart auto-negotiation if remote fault */
1447 if (status
& PHY_STAT_REM_FLT
) {
1448 printf ("%s: PHY remote fault detected\n",
1451 /* Restart auto-negotiation */
1452 printf ("%s: PHY restarting auto-negotiation\n",
1454 smc_write_phy_register (PHY_CNTL_REG
,
1463 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME
);
1467 /* Fail if we detected an auto-negotiate remote fault */
1468 if (status
& PHY_STAT_REM_FLT
) {
1469 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME
);
1473 /* Re-Configure the Receive/Phy Control register */
1474 SMC_outw (RPC_DEFAULT
, RPC_REG
);
1476 smc_phy_configure_exit
: ;
1479 #endif /* !CONFIG_SMC91111_EXT_PHY */
1483 static void print_packet( byte
* buf
, int length
)
1489 printf("Packet of length %d \n", length
);
1492 lines
= length
/ 16;
1493 remainder
= length
% 16;
1495 for ( i
= 0; i
< lines
; i
++ ) {
1498 for ( cur
= 0; cur
< 8; cur
++ ) {
1503 printf("%02x%02x ", a
, b
);
1507 for ( i
= 0; i
< remainder
/2 ; i
++ ) {
1512 printf("%02x%02x ", a
, b
);
1519 int eth_init(bd_t
*bd
) {
1520 #ifdef SHARED_RESOURCES
1523 return (smc_open(bd
));
1534 int eth_send(volatile void *packet
, int length
) {
1535 return smc_send_packet(packet
, length
);
1538 int smc_get_ethaddr (bd_t
* bd
)
1540 int env_size
, rom_valid
, env_present
= 0, reg
;
1541 char *s
= NULL
, *e
, es
[] = "11:22:33:44:55:66";
1543 uchar v_env_mac
[6], v_rom_mac
[6], *v_mac
;
1545 env_size
= getenv_r ("ethaddr", s_env_mac
, sizeof (s_env_mac
));
1546 if ((env_size
> 0) && (env_size
< sizeof (es
))) { /* exit if env is bad */
1547 printf ("\n*** ERROR: ethaddr is not set properly!!\n");
1556 for (reg
= 0; reg
< 6; ++reg
) { /* turn string into mac value */
1557 v_env_mac
[reg
] = s
? simple_strtoul (s
, &e
, 16) : 0;
1559 s
= (*e
) ? e
+ 1 : e
;
1562 rom_valid
= get_rom_mac (v_rom_mac
); /* get ROM mac value if any */
1564 if (!env_present
) { /* if NO env */
1565 if (rom_valid
) { /* but ROM is valid */
1567 sprintf (s_env_mac
, "%02X:%02X:%02X:%02X:%02X:%02X",
1568 v_mac
[0], v_mac
[1], v_mac
[2], v_mac
[3],
1569 v_mac
[4], v_mac
[5]);
1570 setenv ("ethaddr", s_env_mac
);
1571 } else { /* no env, bad ROM */
1572 printf ("\n*** ERROR: ethaddr is NOT set !!\n");
1575 } else { /* good env, don't care ROM */
1576 v_mac
= v_env_mac
; /* always use a good env over a ROM */
1579 if (env_present
&& rom_valid
) { /* if both env and ROM are good */
1580 if (memcmp (v_env_mac
, v_rom_mac
, 6) != 0) {
1581 printf ("\nWarning: MAC addresses don't match:\n");
1582 printf ("\tHW MAC address: "
1583 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1584 v_rom_mac
[0], v_rom_mac
[1],
1585 v_rom_mac
[2], v_rom_mac
[3],
1586 v_rom_mac
[4], v_rom_mac
[5] );
1587 printf ("\t\"ethaddr\" value: "
1588 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1589 v_env_mac
[0], v_env_mac
[1],
1590 v_env_mac
[2], v_env_mac
[3],
1591 v_env_mac
[4], v_env_mac
[5]) ;
1592 debug ("### Set MAC addr from environment\n");
1595 memcpy (bd
->bi_enetaddr
, v_mac
, 6); /* update global address to match env (allows env changing) */
1596 smc_set_mac_addr ((uchar
*)v_mac
); /* use old function to update smc default */
1597 PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac
[0], v_mac
[1],
1598 v_mac
[2], v_mac
[3], v_mac
[4], v_mac
[5]);
1602 int get_rom_mac (uchar
*v_rom_mac
)
1604 #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1605 char hw_mac_addr
[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
1607 memcpy (v_rom_mac
, hw_mac_addr
, 6);
1613 SMC_SELECT_BANK (1);
1616 v_rom_mac
[i
] = SMC_inb ((ADDR0_REG
+ i
));
1617 valid_mac
|= v_rom_mac
[i
];
1620 return (valid_mac
? 1 : 0);
1623 #endif /* CONFIG_DRIVER_SMC91111 */