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soc/tegra: pmc: Drop locking from tegra_powergate_is_powered()
[people/arne_f/kernel.git] / drivers / soc / tegra / pmc.c
1 /*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
21
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
30 #include <linux/io.h>
31 #include <linux/iopoll.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
46
47 #define PMC_CNTRL 0x0
48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
54 #define PMC_CNTRL_MAIN_RST BIT(4)
55
56 #define DPD_SAMPLE 0x020
57 #define DPD_SAMPLE_ENABLE BIT(0)
58 #define DPD_SAMPLE_DISABLE (0 << 0)
59
60 #define PWRGATE_TOGGLE 0x30
61 #define PWRGATE_TOGGLE_START BIT(8)
62
63 #define REMOVE_CLAMPING 0x34
64
65 #define PWRGATE_STATUS 0x38
66
67 #define PMC_PWR_DET 0x48
68
69 #define PMC_SCRATCH0 0x50
70 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
71 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
72 #define PMC_SCRATCH0_MODE_RCM BIT(1)
73 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
74 PMC_SCRATCH0_MODE_BOOTLOADER | \
75 PMC_SCRATCH0_MODE_RCM)
76
77 #define PMC_CPUPWRGOOD_TIMER 0xc8
78 #define PMC_CPUPWROFF_TIMER 0xcc
79
80 #define PMC_PWR_DET_VALUE 0xe4
81
82 #define PMC_SCRATCH41 0x140
83
84 #define PMC_SENSOR_CTRL 0x1b0
85 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
86 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
87
88 #define PMC_RST_STATUS 0x1b4
89 #define PMC_RST_STATUS_POR 0
90 #define PMC_RST_STATUS_WATCHDOG 1
91 #define PMC_RST_STATUS_SENSOR 2
92 #define PMC_RST_STATUS_SW_MAIN 3
93 #define PMC_RST_STATUS_LP0 4
94 #define PMC_RST_STATUS_AOTAG 5
95
96 #define IO_DPD_REQ 0x1b8
97 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
98 #define IO_DPD_REQ_CODE_OFF (1U << 30)
99 #define IO_DPD_REQ_CODE_ON (2U << 30)
100 #define IO_DPD_REQ_CODE_MASK (3U << 30)
101
102 #define IO_DPD_STATUS 0x1bc
103 #define IO_DPD2_REQ 0x1c0
104 #define IO_DPD2_STATUS 0x1c4
105 #define SEL_DPD_TIM 0x1c8
106
107 #define PMC_SCRATCH54 0x258
108 #define PMC_SCRATCH54_DATA_SHIFT 8
109 #define PMC_SCRATCH54_ADDR_SHIFT 0
110
111 #define PMC_SCRATCH55 0x25c
112 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
113 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
114 #define PMC_SCRATCH55_PINMUX_SHIFT 24
115 #define PMC_SCRATCH55_16BITOP BIT(15)
116 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
117 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
118
119 #define GPU_RG_CNTRL 0x2d4
120
121 struct tegra_powergate {
122 struct generic_pm_domain genpd;
123 struct tegra_pmc *pmc;
124 unsigned int id;
125 struct clk **clks;
126 unsigned int num_clks;
127 struct reset_control **resets;
128 unsigned int num_resets;
129 };
130
131 struct tegra_io_pad_soc {
132 enum tegra_io_pad id;
133 unsigned int dpd;
134 unsigned int voltage;
135 };
136
137 struct tegra_pmc_soc {
138 unsigned int num_powergates;
139 const char *const *powergates;
140 unsigned int num_cpu_powergates;
141 const u8 *cpu_powergates;
142
143 bool has_tsense_reset;
144 bool has_gpu_clamps;
145
146 const struct tegra_io_pad_soc *io_pads;
147 unsigned int num_io_pads;
148 };
149
150 /**
151 * struct tegra_pmc - NVIDIA Tegra PMC
152 * @dev: pointer to PMC device structure
153 * @base: pointer to I/O remapped register region
154 * @clk: pointer to pclk clock
155 * @soc: pointer to SoC data structure
156 * @debugfs: pointer to debugfs entry
157 * @rate: currently configured rate of pclk
158 * @suspend_mode: lowest suspend mode available
159 * @cpu_good_time: CPU power good time (in microseconds)
160 * @cpu_off_time: CPU power off time (in microsecends)
161 * @core_osc_time: core power good OSC time (in microseconds)
162 * @core_pmu_time: core power good PMU time (in microseconds)
163 * @core_off_time: core power off time (in microseconds)
164 * @corereq_high: core power request is active-high
165 * @sysclkreq_high: system clock request is active-high
166 * @combined_req: combined power request for CPU & core
167 * @cpu_pwr_good_en: CPU power good signal is enabled
168 * @lp0_vec_phys: physical base address of the LP0 warm boot code
169 * @lp0_vec_size: size of the LP0 warm boot code
170 * @powergates_available: Bitmap of available power gates
171 * @powergates_lock: mutex for power gate register access
172 */
173 struct tegra_pmc {
174 struct device *dev;
175 void __iomem *base;
176 struct clk *clk;
177 struct dentry *debugfs;
178
179 const struct tegra_pmc_soc *soc;
180
181 unsigned long rate;
182
183 enum tegra_suspend_mode suspend_mode;
184 u32 cpu_good_time;
185 u32 cpu_off_time;
186 u32 core_osc_time;
187 u32 core_pmu_time;
188 u32 core_off_time;
189 bool corereq_high;
190 bool sysclkreq_high;
191 bool combined_req;
192 bool cpu_pwr_good_en;
193 u32 lp0_vec_phys;
194 u32 lp0_vec_size;
195 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
196
197 struct mutex powergates_lock;
198 };
199
200 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
201 .base = NULL,
202 .suspend_mode = TEGRA_SUSPEND_NONE,
203 };
204
205 static inline struct tegra_powergate *
206 to_powergate(struct generic_pm_domain *domain)
207 {
208 return container_of(domain, struct tegra_powergate, genpd);
209 }
210
211 static u32 tegra_pmc_readl(unsigned long offset)
212 {
213 return readl(pmc->base + offset);
214 }
215
216 static void tegra_pmc_writel(u32 value, unsigned long offset)
217 {
218 writel(value, pmc->base + offset);
219 }
220
221 static inline bool tegra_powergate_state(int id)
222 {
223 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
224 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
225 else
226 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
227 }
228
229 static inline bool tegra_powergate_is_valid(int id)
230 {
231 return (pmc->soc && pmc->soc->powergates[id]);
232 }
233
234 static inline bool tegra_powergate_is_available(int id)
235 {
236 return test_bit(id, pmc->powergates_available);
237 }
238
239 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
240 {
241 unsigned int i;
242
243 if (!pmc || !pmc->soc || !name)
244 return -EINVAL;
245
246 for (i = 0; i < pmc->soc->num_powergates; i++) {
247 if (!tegra_powergate_is_valid(i))
248 continue;
249
250 if (!strcmp(name, pmc->soc->powergates[i]))
251 return i;
252 }
253
254 return -ENODEV;
255 }
256
257 /**
258 * tegra_powergate_set() - set the state of a partition
259 * @id: partition ID
260 * @new_state: new state of the partition
261 */
262 static int tegra_powergate_set(unsigned int id, bool new_state)
263 {
264 bool status;
265 int err;
266
267 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
268 return -EINVAL;
269
270 mutex_lock(&pmc->powergates_lock);
271
272 if (tegra_powergate_state(id) == new_state) {
273 mutex_unlock(&pmc->powergates_lock);
274 return 0;
275 }
276
277 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
278
279 err = readx_poll_timeout(tegra_powergate_state, id, status,
280 status == new_state, 10, 100000);
281
282 mutex_unlock(&pmc->powergates_lock);
283
284 return err;
285 }
286
287 static int __tegra_powergate_remove_clamping(unsigned int id)
288 {
289 u32 mask;
290
291 mutex_lock(&pmc->powergates_lock);
292
293 /*
294 * On Tegra124 and later, the clamps for the GPU are controlled by a
295 * separate register (with different semantics).
296 */
297 if (id == TEGRA_POWERGATE_3D) {
298 if (pmc->soc->has_gpu_clamps) {
299 tegra_pmc_writel(0, GPU_RG_CNTRL);
300 goto out;
301 }
302 }
303
304 /*
305 * Tegra 2 has a bug where PCIE and VDE clamping masks are
306 * swapped relatively to the partition ids
307 */
308 if (id == TEGRA_POWERGATE_VDEC)
309 mask = (1 << TEGRA_POWERGATE_PCIE);
310 else if (id == TEGRA_POWERGATE_PCIE)
311 mask = (1 << TEGRA_POWERGATE_VDEC);
312 else
313 mask = (1 << id);
314
315 tegra_pmc_writel(mask, REMOVE_CLAMPING);
316
317 out:
318 mutex_unlock(&pmc->powergates_lock);
319
320 return 0;
321 }
322
323 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
324 {
325 unsigned int i;
326
327 for (i = 0; i < pg->num_clks; i++)
328 clk_disable_unprepare(pg->clks[i]);
329 }
330
331 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
332 {
333 unsigned int i;
334 int err;
335
336 for (i = 0; i < pg->num_clks; i++) {
337 err = clk_prepare_enable(pg->clks[i]);
338 if (err)
339 goto out;
340 }
341
342 return 0;
343
344 out:
345 while (i--)
346 clk_disable_unprepare(pg->clks[i]);
347
348 return err;
349 }
350
351 static int tegra_powergate_reset_assert(struct tegra_powergate *pg)
352 {
353 unsigned int i;
354 int err;
355
356 for (i = 0; i < pg->num_resets; i++) {
357 err = reset_control_assert(pg->resets[i]);
358 if (err)
359 return err;
360 }
361
362 return 0;
363 }
364
365 static int tegra_powergate_reset_deassert(struct tegra_powergate *pg)
366 {
367 unsigned int i;
368 int err;
369
370 for (i = 0; i < pg->num_resets; i++) {
371 err = reset_control_deassert(pg->resets[i]);
372 if (err)
373 return err;
374 }
375
376 return 0;
377 }
378
379 static int tegra_powergate_power_up(struct tegra_powergate *pg,
380 bool disable_clocks)
381 {
382 int err;
383
384 err = tegra_powergate_reset_assert(pg);
385 if (err)
386 return err;
387
388 usleep_range(10, 20);
389
390 err = tegra_powergate_set(pg->id, true);
391 if (err < 0)
392 return err;
393
394 usleep_range(10, 20);
395
396 err = tegra_powergate_enable_clocks(pg);
397 if (err)
398 goto disable_clks;
399
400 usleep_range(10, 20);
401
402 err = __tegra_powergate_remove_clamping(pg->id);
403 if (err)
404 goto disable_clks;
405
406 usleep_range(10, 20);
407
408 err = tegra_powergate_reset_deassert(pg);
409 if (err)
410 goto powergate_off;
411
412 usleep_range(10, 20);
413
414 if (disable_clocks)
415 tegra_powergate_disable_clocks(pg);
416
417 return 0;
418
419 disable_clks:
420 tegra_powergate_disable_clocks(pg);
421 usleep_range(10, 20);
422
423 powergate_off:
424 tegra_powergate_set(pg->id, false);
425
426 return err;
427 }
428
429 static int tegra_powergate_power_down(struct tegra_powergate *pg)
430 {
431 int err;
432
433 err = tegra_powergate_enable_clocks(pg);
434 if (err)
435 return err;
436
437 usleep_range(10, 20);
438
439 err = tegra_powergate_reset_assert(pg);
440 if (err)
441 goto disable_clks;
442
443 usleep_range(10, 20);
444
445 tegra_powergate_disable_clocks(pg);
446
447 usleep_range(10, 20);
448
449 err = tegra_powergate_set(pg->id, false);
450 if (err)
451 goto assert_resets;
452
453 return 0;
454
455 assert_resets:
456 tegra_powergate_enable_clocks(pg);
457 usleep_range(10, 20);
458 tegra_powergate_reset_deassert(pg);
459 usleep_range(10, 20);
460
461 disable_clks:
462 tegra_powergate_disable_clocks(pg);
463
464 return err;
465 }
466
467 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
468 {
469 struct tegra_powergate *pg = to_powergate(domain);
470 int err;
471
472 err = tegra_powergate_power_up(pg, true);
473 if (err)
474 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
475 err);
476
477 return err;
478 }
479
480 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
481 {
482 struct tegra_powergate *pg = to_powergate(domain);
483 int err;
484
485 err = tegra_powergate_power_down(pg);
486 if (err)
487 pr_err("failed to turn off PM domain %s: %d\n",
488 pg->genpd.name, err);
489
490 return err;
491 }
492
493 /**
494 * tegra_powergate_power_on() - power on partition
495 * @id: partition ID
496 */
497 int tegra_powergate_power_on(unsigned int id)
498 {
499 if (!tegra_powergate_is_available(id))
500 return -EINVAL;
501
502 return tegra_powergate_set(id, true);
503 }
504
505 /**
506 * tegra_powergate_power_off() - power off partition
507 * @id: partition ID
508 */
509 int tegra_powergate_power_off(unsigned int id)
510 {
511 if (!tegra_powergate_is_available(id))
512 return -EINVAL;
513
514 return tegra_powergate_set(id, false);
515 }
516 EXPORT_SYMBOL(tegra_powergate_power_off);
517
518 /**
519 * tegra_powergate_is_powered() - check if partition is powered
520 * @id: partition ID
521 */
522 int tegra_powergate_is_powered(unsigned int id)
523 {
524 if (!tegra_powergate_is_valid(id))
525 return -EINVAL;
526
527 return tegra_powergate_state(id);
528 }
529
530 /**
531 * tegra_powergate_remove_clamping() - remove power clamps for partition
532 * @id: partition ID
533 */
534 int tegra_powergate_remove_clamping(unsigned int id)
535 {
536 if (!tegra_powergate_is_available(id))
537 return -EINVAL;
538
539 return __tegra_powergate_remove_clamping(id);
540 }
541 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
542
543 /**
544 * tegra_powergate_sequence_power_up() - power up partition
545 * @id: partition ID
546 * @clk: clock for partition
547 * @rst: reset for partition
548 *
549 * Must be called with clk disabled, and returns with clk enabled.
550 */
551 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
552 struct reset_control *rst)
553 {
554 struct tegra_powergate pg;
555 int err;
556
557 if (!tegra_powergate_is_available(id))
558 return -EINVAL;
559
560 pg.id = id;
561 pg.clks = &clk;
562 pg.num_clks = 1;
563 pg.resets = &rst;
564 pg.num_resets = 1;
565
566 err = tegra_powergate_power_up(&pg, false);
567 if (err)
568 pr_err("failed to turn on partition %d: %d\n", id, err);
569
570 return err;
571 }
572 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
573
574 #ifdef CONFIG_SMP
575 /**
576 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
577 * @cpuid: CPU partition ID
578 *
579 * Returns the partition ID corresponding to the CPU partition ID or a
580 * negative error code on failure.
581 */
582 static int tegra_get_cpu_powergate_id(unsigned int cpuid)
583 {
584 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
585 return pmc->soc->cpu_powergates[cpuid];
586
587 return -EINVAL;
588 }
589
590 /**
591 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
592 * @cpuid: CPU partition ID
593 */
594 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
595 {
596 int id;
597
598 id = tegra_get_cpu_powergate_id(cpuid);
599 if (id < 0)
600 return false;
601
602 return tegra_powergate_is_powered(id);
603 }
604
605 /**
606 * tegra_pmc_cpu_power_on() - power on CPU partition
607 * @cpuid: CPU partition ID
608 */
609 int tegra_pmc_cpu_power_on(unsigned int cpuid)
610 {
611 int id;
612
613 id = tegra_get_cpu_powergate_id(cpuid);
614 if (id < 0)
615 return id;
616
617 return tegra_powergate_set(id, true);
618 }
619
620 /**
621 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
622 * @cpuid: CPU partition ID
623 */
624 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
625 {
626 int id;
627
628 id = tegra_get_cpu_powergate_id(cpuid);
629 if (id < 0)
630 return id;
631
632 return tegra_powergate_remove_clamping(id);
633 }
634 #endif /* CONFIG_SMP */
635
636 static int tegra_pmc_restart_notify(struct notifier_block *this,
637 unsigned long action, void *data)
638 {
639 const char *cmd = data;
640 u32 value;
641
642 value = tegra_pmc_readl(PMC_SCRATCH0);
643 value &= ~PMC_SCRATCH0_MODE_MASK;
644
645 if (cmd) {
646 if (strcmp(cmd, "recovery") == 0)
647 value |= PMC_SCRATCH0_MODE_RECOVERY;
648
649 if (strcmp(cmd, "bootloader") == 0)
650 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
651
652 if (strcmp(cmd, "forced-recovery") == 0)
653 value |= PMC_SCRATCH0_MODE_RCM;
654 }
655
656 tegra_pmc_writel(value, PMC_SCRATCH0);
657
658 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
659 value = tegra_pmc_readl(PMC_CNTRL);
660 value |= PMC_CNTRL_MAIN_RST;
661 tegra_pmc_writel(value, PMC_CNTRL);
662
663 return NOTIFY_DONE;
664 }
665
666 static struct notifier_block tegra_pmc_restart_handler = {
667 .notifier_call = tegra_pmc_restart_notify,
668 .priority = 128,
669 };
670
671 static int powergate_show(struct seq_file *s, void *data)
672 {
673 unsigned int i;
674 int status;
675
676 seq_printf(s, " powergate powered\n");
677 seq_printf(s, "------------------\n");
678
679 for (i = 0; i < pmc->soc->num_powergates; i++) {
680 status = tegra_powergate_is_powered(i);
681 if (status < 0)
682 continue;
683
684 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
685 status ? "yes" : "no");
686 }
687
688 return 0;
689 }
690
691 static int powergate_open(struct inode *inode, struct file *file)
692 {
693 return single_open(file, powergate_show, inode->i_private);
694 }
695
696 static const struct file_operations powergate_fops = {
697 .open = powergate_open,
698 .read = seq_read,
699 .llseek = seq_lseek,
700 .release = single_release,
701 };
702
703 static int tegra_powergate_debugfs_init(void)
704 {
705 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
706 &powergate_fops);
707 if (!pmc->debugfs)
708 return -ENOMEM;
709
710 return 0;
711 }
712
713 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
714 struct device_node *np)
715 {
716 struct clk *clk;
717 unsigned int i, count;
718 int err;
719
720 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
721 if (count == 0)
722 return -ENODEV;
723
724 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
725 if (!pg->clks)
726 return -ENOMEM;
727
728 for (i = 0; i < count; i++) {
729 pg->clks[i] = of_clk_get(np, i);
730 if (IS_ERR(pg->clks[i])) {
731 err = PTR_ERR(pg->clks[i]);
732 goto err;
733 }
734 }
735
736 pg->num_clks = count;
737
738 return 0;
739
740 err:
741 while (i--)
742 clk_put(pg->clks[i]);
743
744 kfree(pg->clks);
745
746 return err;
747 }
748
749 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
750 struct device_node *np, bool off)
751 {
752 struct reset_control *rst;
753 unsigned int i, count;
754 int err;
755
756 count = of_count_phandle_with_args(np, "resets", "#reset-cells");
757 if (count == 0)
758 return -ENODEV;
759
760 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL);
761 if (!pg->resets)
762 return -ENOMEM;
763
764 for (i = 0; i < count; i++) {
765 pg->resets[i] = of_reset_control_get_by_index(np, i);
766 if (IS_ERR(pg->resets[i])) {
767 err = PTR_ERR(pg->resets[i]);
768 goto error;
769 }
770
771 if (off)
772 err = reset_control_assert(pg->resets[i]);
773 else
774 err = reset_control_deassert(pg->resets[i]);
775
776 if (err) {
777 reset_control_put(pg->resets[i]);
778 goto error;
779 }
780 }
781
782 pg->num_resets = count;
783
784 return 0;
785
786 error:
787 while (i--)
788 reset_control_put(pg->resets[i]);
789
790 kfree(pg->resets);
791
792 return err;
793 }
794
795 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
796 {
797 struct tegra_powergate *pg;
798 int id, err;
799 bool off;
800
801 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
802 if (!pg)
803 return;
804
805 id = tegra_powergate_lookup(pmc, np->name);
806 if (id < 0) {
807 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
808 goto free_mem;
809 }
810
811 /*
812 * Clear the bit for this powergate so it cannot be managed
813 * directly via the legacy APIs for controlling powergates.
814 */
815 clear_bit(id, pmc->powergates_available);
816
817 pg->id = id;
818 pg->genpd.name = np->name;
819 pg->genpd.power_off = tegra_genpd_power_off;
820 pg->genpd.power_on = tegra_genpd_power_on;
821 pg->pmc = pmc;
822
823 off = !tegra_powergate_is_powered(pg->id);
824
825 err = tegra_powergate_of_get_clks(pg, np);
826 if (err < 0) {
827 pr_err("failed to get clocks for %s: %d\n", np->name, err);
828 goto set_available;
829 }
830
831 err = tegra_powergate_of_get_resets(pg, np, off);
832 if (err < 0) {
833 pr_err("failed to get resets for %s: %d\n", np->name, err);
834 goto remove_clks;
835 }
836
837 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
838 if (off)
839 WARN_ON(tegra_powergate_power_up(pg, true));
840
841 goto remove_resets;
842 }
843
844 /*
845 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
846 * host and super-speed partitions. Once the XHCI driver
847 * manages the partitions itself this code can be removed. Note
848 * that we don't register these partitions with the genpd core
849 * to avoid it from powering down the partitions as they appear
850 * to be unused.
851 */
852 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
853 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
854 if (off)
855 WARN_ON(tegra_powergate_power_up(pg, true));
856
857 goto remove_resets;
858 }
859
860 err = pm_genpd_init(&pg->genpd, NULL, off);
861 if (err < 0) {
862 pr_err("failed to initialise PM domain %s: %d\n", np->name,
863 err);
864 goto remove_resets;
865 }
866
867 err = of_genpd_add_provider_simple(np, &pg->genpd);
868 if (err < 0) {
869 pr_err("failed to add PM domain provider for %s: %d\n",
870 np->name, err);
871 goto remove_genpd;
872 }
873
874 pr_debug("added PM domain %s\n", pg->genpd.name);
875
876 return;
877
878 remove_genpd:
879 pm_genpd_remove(&pg->genpd);
880
881 remove_resets:
882 while (pg->num_resets--)
883 reset_control_put(pg->resets[pg->num_resets]);
884
885 kfree(pg->resets);
886
887 remove_clks:
888 while (pg->num_clks--)
889 clk_put(pg->clks[pg->num_clks]);
890
891 kfree(pg->clks);
892
893 set_available:
894 set_bit(id, pmc->powergates_available);
895
896 free_mem:
897 kfree(pg);
898 }
899
900 static void tegra_powergate_init(struct tegra_pmc *pmc,
901 struct device_node *parent)
902 {
903 struct device_node *np, *child;
904 unsigned int i;
905
906 /* Create a bitmap of the available and valid partitions */
907 for (i = 0; i < pmc->soc->num_powergates; i++)
908 if (pmc->soc->powergates[i])
909 set_bit(i, pmc->powergates_available);
910
911 np = of_get_child_by_name(parent, "powergates");
912 if (!np)
913 return;
914
915 for_each_child_of_node(np, child)
916 tegra_powergate_add(pmc, child);
917
918 of_node_put(np);
919 }
920
921 static const struct tegra_io_pad_soc *
922 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
923 {
924 unsigned int i;
925
926 for (i = 0; i < pmc->soc->num_io_pads; i++)
927 if (pmc->soc->io_pads[i].id == id)
928 return &pmc->soc->io_pads[i];
929
930 return NULL;
931 }
932
933 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
934 unsigned long *status, u32 *mask)
935 {
936 const struct tegra_io_pad_soc *pad;
937 unsigned long rate, value;
938
939 pad = tegra_io_pad_find(pmc, id);
940 if (!pad) {
941 pr_err("invalid I/O pad ID %u\n", id);
942 return -ENOENT;
943 }
944
945 if (pad->dpd == UINT_MAX)
946 return -ENOTSUPP;
947
948 *mask = BIT(pad->dpd % 32);
949
950 if (pad->dpd < 32) {
951 *status = IO_DPD_STATUS;
952 *request = IO_DPD_REQ;
953 } else {
954 *status = IO_DPD2_STATUS;
955 *request = IO_DPD2_REQ;
956 }
957
958 rate = clk_get_rate(pmc->clk);
959 if (!rate) {
960 pr_err("failed to get clock rate\n");
961 return -ENODEV;
962 }
963
964 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
965
966 /* must be at least 200 ns, in APB (PCLK) clock cycles */
967 value = DIV_ROUND_UP(1000000000, rate);
968 value = DIV_ROUND_UP(200, value);
969 tegra_pmc_writel(value, SEL_DPD_TIM);
970
971 return 0;
972 }
973
974 static int tegra_io_pad_poll(unsigned long offset, u32 mask,
975 u32 val, unsigned long timeout)
976 {
977 u32 value;
978
979 timeout = jiffies + msecs_to_jiffies(timeout);
980
981 while (time_after(timeout, jiffies)) {
982 value = tegra_pmc_readl(offset);
983 if ((value & mask) == val)
984 return 0;
985
986 usleep_range(250, 1000);
987 }
988
989 return -ETIMEDOUT;
990 }
991
992 static void tegra_io_pad_unprepare(void)
993 {
994 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
995 }
996
997 /**
998 * tegra_io_pad_power_enable() - enable power to I/O pad
999 * @id: Tegra I/O pad ID for which to enable power
1000 *
1001 * Returns: 0 on success or a negative error code on failure.
1002 */
1003 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1004 {
1005 unsigned long request, status;
1006 u32 mask;
1007 int err;
1008
1009 mutex_lock(&pmc->powergates_lock);
1010
1011 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1012 if (err < 0) {
1013 pr_err("failed to prepare I/O pad: %d\n", err);
1014 goto unlock;
1015 }
1016
1017 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1018
1019 err = tegra_io_pad_poll(status, mask, 0, 250);
1020 if (err < 0) {
1021 pr_err("failed to enable I/O pad: %d\n", err);
1022 goto unlock;
1023 }
1024
1025 tegra_io_pad_unprepare();
1026
1027 unlock:
1028 mutex_unlock(&pmc->powergates_lock);
1029 return err;
1030 }
1031 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1032
1033 /**
1034 * tegra_io_pad_power_disable() - disable power to I/O pad
1035 * @id: Tegra I/O pad ID for which to disable power
1036 *
1037 * Returns: 0 on success or a negative error code on failure.
1038 */
1039 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1040 {
1041 unsigned long request, status;
1042 u32 mask;
1043 int err;
1044
1045 mutex_lock(&pmc->powergates_lock);
1046
1047 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1048 if (err < 0) {
1049 pr_err("failed to prepare I/O pad: %d\n", err);
1050 goto unlock;
1051 }
1052
1053 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1054
1055 err = tegra_io_pad_poll(status, mask, mask, 250);
1056 if (err < 0) {
1057 pr_err("failed to disable I/O pad: %d\n", err);
1058 goto unlock;
1059 }
1060
1061 tegra_io_pad_unprepare();
1062
1063 unlock:
1064 mutex_unlock(&pmc->powergates_lock);
1065 return err;
1066 }
1067 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1068
1069 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1070 enum tegra_io_pad_voltage voltage)
1071 {
1072 const struct tegra_io_pad_soc *pad;
1073 u32 value;
1074
1075 pad = tegra_io_pad_find(pmc, id);
1076 if (!pad)
1077 return -ENOENT;
1078
1079 if (pad->voltage == UINT_MAX)
1080 return -ENOTSUPP;
1081
1082 mutex_lock(&pmc->powergates_lock);
1083
1084 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1085 value = tegra_pmc_readl(PMC_PWR_DET);
1086 value |= BIT(pad->voltage);
1087 tegra_pmc_writel(value, PMC_PWR_DET);
1088
1089 /* update I/O voltage */
1090 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1091
1092 if (voltage == TEGRA_IO_PAD_1800000UV)
1093 value &= ~BIT(pad->voltage);
1094 else
1095 value |= BIT(pad->voltage);
1096
1097 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1098
1099 mutex_unlock(&pmc->powergates_lock);
1100
1101 usleep_range(100, 250);
1102
1103 return 0;
1104 }
1105 EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1106
1107 int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1108 {
1109 const struct tegra_io_pad_soc *pad;
1110 u32 value;
1111
1112 pad = tegra_io_pad_find(pmc, id);
1113 if (!pad)
1114 return -ENOENT;
1115
1116 if (pad->voltage == UINT_MAX)
1117 return -ENOTSUPP;
1118
1119 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1120
1121 if ((value & BIT(pad->voltage)) == 0)
1122 return TEGRA_IO_PAD_1800000UV;
1123
1124 return TEGRA_IO_PAD_3300000UV;
1125 }
1126 EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1127
1128 /**
1129 * tegra_io_rail_power_on() - enable power to I/O rail
1130 * @id: Tegra I/O pad ID for which to enable power
1131 *
1132 * See also: tegra_io_pad_power_enable()
1133 */
1134 int tegra_io_rail_power_on(unsigned int id)
1135 {
1136 return tegra_io_pad_power_enable(id);
1137 }
1138 EXPORT_SYMBOL(tegra_io_rail_power_on);
1139
1140 /**
1141 * tegra_io_rail_power_off() - disable power to I/O rail
1142 * @id: Tegra I/O pad ID for which to disable power
1143 *
1144 * See also: tegra_io_pad_power_disable()
1145 */
1146 int tegra_io_rail_power_off(unsigned int id)
1147 {
1148 return tegra_io_pad_power_disable(id);
1149 }
1150 EXPORT_SYMBOL(tegra_io_rail_power_off);
1151
1152 #ifdef CONFIG_PM_SLEEP
1153 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1154 {
1155 return pmc->suspend_mode;
1156 }
1157
1158 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1159 {
1160 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1161 return;
1162
1163 pmc->suspend_mode = mode;
1164 }
1165
1166 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1167 {
1168 unsigned long long rate = 0;
1169 u32 value;
1170
1171 switch (mode) {
1172 case TEGRA_SUSPEND_LP1:
1173 rate = 32768;
1174 break;
1175
1176 case TEGRA_SUSPEND_LP2:
1177 rate = clk_get_rate(pmc->clk);
1178 break;
1179
1180 default:
1181 break;
1182 }
1183
1184 if (WARN_ON_ONCE(rate == 0))
1185 rate = 100000000;
1186
1187 if (rate != pmc->rate) {
1188 u64 ticks;
1189
1190 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1191 do_div(ticks, USEC_PER_SEC);
1192 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1193
1194 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1195 do_div(ticks, USEC_PER_SEC);
1196 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1197
1198 wmb();
1199
1200 pmc->rate = rate;
1201 }
1202
1203 value = tegra_pmc_readl(PMC_CNTRL);
1204 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1205 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1206 tegra_pmc_writel(value, PMC_CNTRL);
1207 }
1208 #endif
1209
1210 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1211 {
1212 u32 value, values[2];
1213
1214 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1215 } else {
1216 switch (value) {
1217 case 0:
1218 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1219 break;
1220
1221 case 1:
1222 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1223 break;
1224
1225 case 2:
1226 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1227 break;
1228
1229 default:
1230 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1231 break;
1232 }
1233 }
1234
1235 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1236
1237 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1238 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1239
1240 pmc->cpu_good_time = value;
1241
1242 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1243 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1244
1245 pmc->cpu_off_time = value;
1246
1247 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1248 values, ARRAY_SIZE(values)))
1249 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1250
1251 pmc->core_osc_time = values[0];
1252 pmc->core_pmu_time = values[1];
1253
1254 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1255 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1256
1257 pmc->core_off_time = value;
1258
1259 pmc->corereq_high = of_property_read_bool(np,
1260 "nvidia,core-power-req-active-high");
1261
1262 pmc->sysclkreq_high = of_property_read_bool(np,
1263 "nvidia,sys-clock-req-active-high");
1264
1265 pmc->combined_req = of_property_read_bool(np,
1266 "nvidia,combined-power-req");
1267
1268 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1269 "nvidia,cpu-pwr-good-en");
1270
1271 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1272 ARRAY_SIZE(values)))
1273 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1274 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1275
1276 pmc->lp0_vec_phys = values[0];
1277 pmc->lp0_vec_size = values[1];
1278
1279 return 0;
1280 }
1281
1282 static void tegra_pmc_init(struct tegra_pmc *pmc)
1283 {
1284 u32 value;
1285
1286 /* Always enable CPU power request */
1287 value = tegra_pmc_readl(PMC_CNTRL);
1288 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1289 tegra_pmc_writel(value, PMC_CNTRL);
1290
1291 value = tegra_pmc_readl(PMC_CNTRL);
1292
1293 if (pmc->sysclkreq_high)
1294 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1295 else
1296 value |= PMC_CNTRL_SYSCLK_POLARITY;
1297
1298 /* configure the output polarity while the request is tristated */
1299 tegra_pmc_writel(value, PMC_CNTRL);
1300
1301 /* now enable the request */
1302 value = tegra_pmc_readl(PMC_CNTRL);
1303 value |= PMC_CNTRL_SYSCLK_OE;
1304 tegra_pmc_writel(value, PMC_CNTRL);
1305 }
1306
1307 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1308 {
1309 static const char disabled[] = "emergency thermal reset disabled";
1310 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1311 struct device *dev = pmc->dev;
1312 struct device_node *np;
1313 u32 value, checksum;
1314
1315 if (!pmc->soc->has_tsense_reset)
1316 return;
1317
1318 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1319 if (!np) {
1320 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1321 return;
1322 }
1323
1324 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1325 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1326 goto out;
1327 }
1328
1329 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1330 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1331 goto out;
1332 }
1333
1334 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1335 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1336 goto out;
1337 }
1338
1339 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1340 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1341 goto out;
1342 }
1343
1344 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1345 pinmux = 0;
1346
1347 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1348 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1349 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1350
1351 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1352 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1353 tegra_pmc_writel(value, PMC_SCRATCH54);
1354
1355 value = PMC_SCRATCH55_RESET_TEGRA;
1356 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1357 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1358 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1359
1360 /*
1361 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1362 * contain the checksum and are currently zero, so they are not added.
1363 */
1364 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1365 + ((value >> 24) & 0xff);
1366 checksum &= 0xff;
1367 checksum = 0x100 - checksum;
1368
1369 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1370
1371 tegra_pmc_writel(value, PMC_SCRATCH55);
1372
1373 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1374 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1375 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1376
1377 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1378
1379 out:
1380 of_node_put(np);
1381 }
1382
1383 static int tegra_pmc_probe(struct platform_device *pdev)
1384 {
1385 void __iomem *base;
1386 struct resource *res;
1387 int err;
1388
1389 /*
1390 * Early initialisation should have configured an initial
1391 * register mapping and setup the soc data pointer. If these
1392 * are not valid then something went badly wrong!
1393 */
1394 if (WARN_ON(!pmc->base || !pmc->soc))
1395 return -ENODEV;
1396
1397 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1398 if (err < 0)
1399 return err;
1400
1401 /* take over the memory region from the early initialization */
1402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1403 base = devm_ioremap_resource(&pdev->dev, res);
1404 if (IS_ERR(base))
1405 return PTR_ERR(base);
1406
1407 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1408 if (IS_ERR(pmc->clk)) {
1409 err = PTR_ERR(pmc->clk);
1410 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1411 return err;
1412 }
1413
1414 pmc->dev = &pdev->dev;
1415
1416 tegra_pmc_init(pmc);
1417
1418 tegra_pmc_init_tsense_reset(pmc);
1419
1420 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1421 err = tegra_powergate_debugfs_init();
1422 if (err < 0)
1423 return err;
1424 }
1425
1426 err = register_restart_handler(&tegra_pmc_restart_handler);
1427 if (err) {
1428 debugfs_remove(pmc->debugfs);
1429 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1430 err);
1431 return err;
1432 }
1433
1434 mutex_lock(&pmc->powergates_lock);
1435 iounmap(pmc->base);
1436 pmc->base = base;
1437 mutex_unlock(&pmc->powergates_lock);
1438
1439 return 0;
1440 }
1441
1442 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1443 static int tegra_pmc_suspend(struct device *dev)
1444 {
1445 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1446
1447 return 0;
1448 }
1449
1450 static int tegra_pmc_resume(struct device *dev)
1451 {
1452 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1453
1454 return 0;
1455 }
1456
1457 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1458
1459 #endif
1460
1461 static const char * const tegra20_powergates[] = {
1462 [TEGRA_POWERGATE_CPU] = "cpu",
1463 [TEGRA_POWERGATE_3D] = "3d",
1464 [TEGRA_POWERGATE_VENC] = "venc",
1465 [TEGRA_POWERGATE_VDEC] = "vdec",
1466 [TEGRA_POWERGATE_PCIE] = "pcie",
1467 [TEGRA_POWERGATE_L2] = "l2",
1468 [TEGRA_POWERGATE_MPE] = "mpe",
1469 };
1470
1471 static const struct tegra_pmc_soc tegra20_pmc_soc = {
1472 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1473 .powergates = tegra20_powergates,
1474 .num_cpu_powergates = 0,
1475 .cpu_powergates = NULL,
1476 .has_tsense_reset = false,
1477 .has_gpu_clamps = false,
1478 };
1479
1480 static const char * const tegra30_powergates[] = {
1481 [TEGRA_POWERGATE_CPU] = "cpu0",
1482 [TEGRA_POWERGATE_3D] = "3d0",
1483 [TEGRA_POWERGATE_VENC] = "venc",
1484 [TEGRA_POWERGATE_VDEC] = "vdec",
1485 [TEGRA_POWERGATE_PCIE] = "pcie",
1486 [TEGRA_POWERGATE_L2] = "l2",
1487 [TEGRA_POWERGATE_MPE] = "mpe",
1488 [TEGRA_POWERGATE_HEG] = "heg",
1489 [TEGRA_POWERGATE_SATA] = "sata",
1490 [TEGRA_POWERGATE_CPU1] = "cpu1",
1491 [TEGRA_POWERGATE_CPU2] = "cpu2",
1492 [TEGRA_POWERGATE_CPU3] = "cpu3",
1493 [TEGRA_POWERGATE_CELP] = "celp",
1494 [TEGRA_POWERGATE_3D1] = "3d1",
1495 };
1496
1497 static const u8 tegra30_cpu_powergates[] = {
1498 TEGRA_POWERGATE_CPU,
1499 TEGRA_POWERGATE_CPU1,
1500 TEGRA_POWERGATE_CPU2,
1501 TEGRA_POWERGATE_CPU3,
1502 };
1503
1504 static const struct tegra_pmc_soc tegra30_pmc_soc = {
1505 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1506 .powergates = tegra30_powergates,
1507 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1508 .cpu_powergates = tegra30_cpu_powergates,
1509 .has_tsense_reset = true,
1510 .has_gpu_clamps = false,
1511 };
1512
1513 static const char * const tegra114_powergates[] = {
1514 [TEGRA_POWERGATE_CPU] = "crail",
1515 [TEGRA_POWERGATE_3D] = "3d",
1516 [TEGRA_POWERGATE_VENC] = "venc",
1517 [TEGRA_POWERGATE_VDEC] = "vdec",
1518 [TEGRA_POWERGATE_MPE] = "mpe",
1519 [TEGRA_POWERGATE_HEG] = "heg",
1520 [TEGRA_POWERGATE_CPU1] = "cpu1",
1521 [TEGRA_POWERGATE_CPU2] = "cpu2",
1522 [TEGRA_POWERGATE_CPU3] = "cpu3",
1523 [TEGRA_POWERGATE_CELP] = "celp",
1524 [TEGRA_POWERGATE_CPU0] = "cpu0",
1525 [TEGRA_POWERGATE_C0NC] = "c0nc",
1526 [TEGRA_POWERGATE_C1NC] = "c1nc",
1527 [TEGRA_POWERGATE_DIS] = "dis",
1528 [TEGRA_POWERGATE_DISB] = "disb",
1529 [TEGRA_POWERGATE_XUSBA] = "xusba",
1530 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1531 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1532 };
1533
1534 static const u8 tegra114_cpu_powergates[] = {
1535 TEGRA_POWERGATE_CPU0,
1536 TEGRA_POWERGATE_CPU1,
1537 TEGRA_POWERGATE_CPU2,
1538 TEGRA_POWERGATE_CPU3,
1539 };
1540
1541 static const struct tegra_pmc_soc tegra114_pmc_soc = {
1542 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1543 .powergates = tegra114_powergates,
1544 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1545 .cpu_powergates = tegra114_cpu_powergates,
1546 .has_tsense_reset = true,
1547 .has_gpu_clamps = false,
1548 };
1549
1550 static const char * const tegra124_powergates[] = {
1551 [TEGRA_POWERGATE_CPU] = "crail",
1552 [TEGRA_POWERGATE_3D] = "3d",
1553 [TEGRA_POWERGATE_VENC] = "venc",
1554 [TEGRA_POWERGATE_PCIE] = "pcie",
1555 [TEGRA_POWERGATE_VDEC] = "vdec",
1556 [TEGRA_POWERGATE_MPE] = "mpe",
1557 [TEGRA_POWERGATE_HEG] = "heg",
1558 [TEGRA_POWERGATE_SATA] = "sata",
1559 [TEGRA_POWERGATE_CPU1] = "cpu1",
1560 [TEGRA_POWERGATE_CPU2] = "cpu2",
1561 [TEGRA_POWERGATE_CPU3] = "cpu3",
1562 [TEGRA_POWERGATE_CELP] = "celp",
1563 [TEGRA_POWERGATE_CPU0] = "cpu0",
1564 [TEGRA_POWERGATE_C0NC] = "c0nc",
1565 [TEGRA_POWERGATE_C1NC] = "c1nc",
1566 [TEGRA_POWERGATE_SOR] = "sor",
1567 [TEGRA_POWERGATE_DIS] = "dis",
1568 [TEGRA_POWERGATE_DISB] = "disb",
1569 [TEGRA_POWERGATE_XUSBA] = "xusba",
1570 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1571 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1572 [TEGRA_POWERGATE_VIC] = "vic",
1573 [TEGRA_POWERGATE_IRAM] = "iram",
1574 };
1575
1576 static const u8 tegra124_cpu_powergates[] = {
1577 TEGRA_POWERGATE_CPU0,
1578 TEGRA_POWERGATE_CPU1,
1579 TEGRA_POWERGATE_CPU2,
1580 TEGRA_POWERGATE_CPU3,
1581 };
1582
1583 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1584 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1585 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1586 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1587 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1588 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1589 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1590 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1591 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1592 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1593 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1594 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1595 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1596 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1597 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1598 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1599 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1600 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1601 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1602 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1603 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1604 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1605 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1606 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1607 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1608 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1609 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1610 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1611 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1612 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1613 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1614 };
1615
1616 static const struct tegra_pmc_soc tegra124_pmc_soc = {
1617 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1618 .powergates = tegra124_powergates,
1619 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1620 .cpu_powergates = tegra124_cpu_powergates,
1621 .has_tsense_reset = true,
1622 .has_gpu_clamps = true,
1623 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1624 .io_pads = tegra124_io_pads,
1625 };
1626
1627 static const char * const tegra210_powergates[] = {
1628 [TEGRA_POWERGATE_CPU] = "crail",
1629 [TEGRA_POWERGATE_3D] = "3d",
1630 [TEGRA_POWERGATE_VENC] = "venc",
1631 [TEGRA_POWERGATE_PCIE] = "pcie",
1632 [TEGRA_POWERGATE_MPE] = "mpe",
1633 [TEGRA_POWERGATE_SATA] = "sata",
1634 [TEGRA_POWERGATE_CPU1] = "cpu1",
1635 [TEGRA_POWERGATE_CPU2] = "cpu2",
1636 [TEGRA_POWERGATE_CPU3] = "cpu3",
1637 [TEGRA_POWERGATE_CPU0] = "cpu0",
1638 [TEGRA_POWERGATE_C0NC] = "c0nc",
1639 [TEGRA_POWERGATE_SOR] = "sor",
1640 [TEGRA_POWERGATE_DIS] = "dis",
1641 [TEGRA_POWERGATE_DISB] = "disb",
1642 [TEGRA_POWERGATE_XUSBA] = "xusba",
1643 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1644 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1645 [TEGRA_POWERGATE_VIC] = "vic",
1646 [TEGRA_POWERGATE_IRAM] = "iram",
1647 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1648 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1649 [TEGRA_POWERGATE_AUD] = "aud",
1650 [TEGRA_POWERGATE_DFD] = "dfd",
1651 [TEGRA_POWERGATE_VE2] = "ve2",
1652 };
1653
1654 static const u8 tegra210_cpu_powergates[] = {
1655 TEGRA_POWERGATE_CPU0,
1656 TEGRA_POWERGATE_CPU1,
1657 TEGRA_POWERGATE_CPU2,
1658 TEGRA_POWERGATE_CPU3,
1659 };
1660
1661 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1662 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1663 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1664 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1665 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1666 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1667 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1668 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1669 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1670 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1671 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1672 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1674 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1676 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1677 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1678 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1679 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1680 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1681 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1682 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1683 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1684 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1685 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1686 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1687 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1688 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1689 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1690 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1691 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1692 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1693 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1694 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1695 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1696 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1697 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1698 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1699 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1700 };
1701
1702 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1703 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1704 .powergates = tegra210_powergates,
1705 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1706 .cpu_powergates = tegra210_cpu_powergates,
1707 .has_tsense_reset = true,
1708 .has_gpu_clamps = true,
1709 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1710 .io_pads = tegra210_io_pads,
1711 };
1712
1713 static const struct of_device_id tegra_pmc_match[] = {
1714 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1715 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1716 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1717 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1718 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1719 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1720 { }
1721 };
1722
1723 static struct platform_driver tegra_pmc_driver = {
1724 .driver = {
1725 .name = "tegra-pmc",
1726 .suppress_bind_attrs = true,
1727 .of_match_table = tegra_pmc_match,
1728 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1729 .pm = &tegra_pmc_pm_ops,
1730 #endif
1731 },
1732 .probe = tegra_pmc_probe,
1733 };
1734 builtin_platform_driver(tegra_pmc_driver);
1735
1736 /*
1737 * Early initialization to allow access to registers in the very early boot
1738 * process.
1739 */
1740 static int __init tegra_pmc_early_init(void)
1741 {
1742 const struct of_device_id *match;
1743 struct device_node *np;
1744 struct resource regs;
1745 bool invert;
1746 u32 value;
1747
1748 mutex_init(&pmc->powergates_lock);
1749
1750 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1751 if (!np) {
1752 /*
1753 * Fall back to legacy initialization for 32-bit ARM only. All
1754 * 64-bit ARM device tree files for Tegra are required to have
1755 * a PMC node.
1756 *
1757 * This is for backwards-compatibility with old device trees
1758 * that didn't contain a PMC node. Note that in this case the
1759 * SoC data can't be matched and therefore powergating is
1760 * disabled.
1761 */
1762 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1763 pr_warn("DT node not found, powergating disabled\n");
1764
1765 regs.start = 0x7000e400;
1766 regs.end = 0x7000e7ff;
1767 regs.flags = IORESOURCE_MEM;
1768
1769 pr_warn("Using memory region %pR\n", &regs);
1770 } else {
1771 /*
1772 * At this point we're not running on Tegra, so play
1773 * nice with multi-platform kernels.
1774 */
1775 return 0;
1776 }
1777 } else {
1778 /*
1779 * Extract information from the device tree if we've found a
1780 * matching node.
1781 */
1782 if (of_address_to_resource(np, 0, &regs) < 0) {
1783 pr_err("failed to get PMC registers\n");
1784 of_node_put(np);
1785 return -ENXIO;
1786 }
1787 }
1788
1789 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
1790 if (!pmc->base) {
1791 pr_err("failed to map PMC registers\n");
1792 of_node_put(np);
1793 return -ENXIO;
1794 }
1795
1796 if (np) {
1797 pmc->soc = match->data;
1798
1799 tegra_powergate_init(pmc, np);
1800
1801 /*
1802 * Invert the interrupt polarity if a PMC device tree node
1803 * exists and contains the nvidia,invert-interrupt property.
1804 */
1805 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1806
1807 value = tegra_pmc_readl(PMC_CNTRL);
1808
1809 if (invert)
1810 value |= PMC_CNTRL_INTR_POLARITY;
1811 else
1812 value &= ~PMC_CNTRL_INTR_POLARITY;
1813
1814 tegra_pmc_writel(value, PMC_CNTRL);
1815
1816 of_node_put(np);
1817 }
1818
1819 return 0;
1820 }
1821 early_initcall(tegra_pmc_early_init);
Arne's tree of linux kernel.