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dm: sound: Add conversion to driver model
[thirdparty/u-boot.git] / drivers / sound / wm8994.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Samsung Electronics
4 * R. Chandrasekar <rcsekar@samsung.com>
5 */
6 #include <common.h>
7 #include <audio_codec.h>
8 #include <dm.h>
9 #include <div64.h>
10 #include <fdtdec.h>
11 #include <i2c.h>
12 #include <i2s.h>
13 #include <sound.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/sound.h>
19 #include "wm8994.h"
20 #include "wm8994_registers.h"
21
22 /* defines for wm8994 system clock selection */
23 #define SEL_MCLK1 0x00
24 #define SEL_MCLK2 0x08
25 #define SEL_FLL1 0x10
26 #define SEL_FLL2 0x18
27
28 /* fll config to configure fll */
29 struct wm8994_fll_config {
30 int src; /* Source */
31 int in; /* Input frequency in Hz */
32 int out; /* output frequency in Hz */
33 };
34
35 /* codec private data */
36 struct wm8994_priv {
37 enum wm8994_type type; /* codec type of wolfson */
38 int revision; /* Revision */
39 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
40 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
41 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
42 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
43 int i2c_addr;
44 struct udevice *dev;
45 };
46
47 /* wm 8994 supported sampling rate values */
48 static unsigned int src_rate[] = {
49 8000, 11025, 12000, 16000, 22050, 24000,
50 32000, 44100, 48000, 88200, 96000
51 };
52
53 /* op clock divisions */
54 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
55
56 /* lr clock frame size ratio */
57 static int fs_ratios[] = {
58 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
59 };
60
61 /* bit clock divisors */
62 static int bclk_divs[] = {
63 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
64 640, 880, 960, 1280, 1760, 1920
65 };
66
67 /*
68 * Writes value to a device register through i2c
69 *
70 * @param priv Private data for driver
71 * @param reg reg number to be write
72 * @param data data to be writen to the above registor
73 *
74 * @return int value 1 for change, 0 for no change or negative error code.
75 */
76 static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
77 unsigned short data)
78 {
79 unsigned char val[2];
80
81 val[0] = (unsigned char)((data >> 8) & 0xff);
82 val[1] = (unsigned char)(data & 0xff);
83 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
84
85 #ifdef CONFIG_DM_SOUND
86 debug("dev = %s\n", priv->dev->name);
87 return dm_i2c_write(priv->dev, reg, val, 2);
88 #else
89 return i2c_write(priv->i2c_addr, reg, 2, val, 2);
90 #endif
91 }
92
93 /*
94 * Read a value from a device register through i2c
95 *
96 * @param priv Private data for driver
97 * @param reg reg number to be read
98 * @param data address of read data to be stored
99 *
100 * @return int value 0 for success, -1 in case of error.
101 */
102 static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
103 unsigned short *data)
104 {
105 unsigned char val[2];
106 int ret;
107
108 #ifdef CONFIG_DM_SOUND
109 ret = dm_i2c_read(priv->dev, reg, val, 1);
110 #else
111 ret = i2c_read(priv->i2c_addr, reg, 2, val, 2);
112 #endif
113 if (ret != 0) {
114 debug("%s: Error while reading register %#04x\n",
115 __func__, reg);
116 return -1;
117 }
118
119 *data = val[0];
120 *data <<= 8;
121 *data |= val[1];
122
123 return 0;
124 }
125
126 /*
127 * update device register bits through i2c
128 *
129 * @param priv Private data for driver
130 * @param reg codec register
131 * @param mask register mask
132 * @param value new value
133 *
134 * @return int value 1 if change in the register value,
135 * 0 for no change or negative error code.
136 */
137 static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
138 unsigned short mask, unsigned short value)
139 {
140 int change , ret = 0;
141 unsigned short old, new;
142
143 if (wm8994_i2c_read(priv, reg, &old) != 0)
144 return -1;
145 new = (old & ~mask) | (value & mask);
146 change = (old != new) ? 1 : 0;
147 if (change)
148 ret = wm8994_i2c_write(priv, reg, new);
149 if (ret < 0)
150 return ret;
151
152 return change;
153 }
154
155 /*
156 * Sets i2s set format
157 *
158 * @param priv wm8994 information
159 * @param aif_id Interface ID
160 * @param fmt i2S format
161 *
162 * @return -1 for error and 0 Success.
163 */
164 static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
165 {
166 int ms_reg;
167 int aif_reg;
168 int ms = 0;
169 int aif = 0;
170 int aif_clk = 0;
171 int error = 0;
172
173 switch (aif_id) {
174 case 1:
175 ms_reg = WM8994_AIF1_MASTER_SLAVE;
176 aif_reg = WM8994_AIF1_CONTROL_1;
177 aif_clk = WM8994_AIF1_CLOCKING_1;
178 break;
179 case 2:
180 ms_reg = WM8994_AIF2_MASTER_SLAVE;
181 aif_reg = WM8994_AIF2_CONTROL_1;
182 aif_clk = WM8994_AIF2_CLOCKING_1;
183 break;
184 default:
185 debug("%s: Invalid audio interface selection\n", __func__);
186 return -1;
187 }
188
189 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
190 case SND_SOC_DAIFMT_CBS_CFS:
191 break;
192 case SND_SOC_DAIFMT_CBM_CFM:
193 ms = WM8994_AIF1_MSTR;
194 break;
195 default:
196 debug("%s: Invalid i2s master selection\n", __func__);
197 return -1;
198 }
199
200 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
201 case SND_SOC_DAIFMT_DSP_B:
202 aif |= WM8994_AIF1_LRCLK_INV;
203 case SND_SOC_DAIFMT_DSP_A:
204 aif |= 0x18;
205 break;
206 case SND_SOC_DAIFMT_I2S:
207 aif |= 0x10;
208 break;
209 case SND_SOC_DAIFMT_RIGHT_J:
210 break;
211 case SND_SOC_DAIFMT_LEFT_J:
212 aif |= 0x8;
213 break;
214 default:
215 debug("%s: Invalid i2s format selection\n", __func__);
216 return -1;
217 }
218
219 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
220 case SND_SOC_DAIFMT_DSP_A:
221 case SND_SOC_DAIFMT_DSP_B:
222 /* frame inversion not valid for DSP modes */
223 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
224 case SND_SOC_DAIFMT_NB_NF:
225 break;
226 case SND_SOC_DAIFMT_IB_NF:
227 aif |= WM8994_AIF1_BCLK_INV;
228 break;
229 default:
230 debug("%s: Invalid i2s frame inverse selection\n",
231 __func__);
232 return -1;
233 }
234 break;
235
236 case SND_SOC_DAIFMT_I2S:
237 case SND_SOC_DAIFMT_RIGHT_J:
238 case SND_SOC_DAIFMT_LEFT_J:
239 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
240 case SND_SOC_DAIFMT_NB_NF:
241 break;
242 case SND_SOC_DAIFMT_IB_IF:
243 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
244 break;
245 case SND_SOC_DAIFMT_IB_NF:
246 aif |= WM8994_AIF1_BCLK_INV;
247 break;
248 case SND_SOC_DAIFMT_NB_IF:
249 aif |= WM8994_AIF1_LRCLK_INV;
250 break;
251 default:
252 debug("%s: Invalid i2s clock polarity selection\n",
253 __func__);
254 return -1;
255 }
256 break;
257 default:
258 debug("%s: Invalid i2s format selection\n", __func__);
259 return -1;
260 }
261
262 error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
263 WM8994_AIF1_LRCLK_INV_MASK |
264 WM8994_AIF1_FMT_MASK, aif);
265
266 error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
267 error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
268 WM8994_AIF1CLK_ENA);
269 if (error < 0) {
270 debug("%s: codec register access error\n", __func__);
271 return -1;
272 }
273
274 return 0;
275 }
276
277 /*
278 * Sets hw params FOR WM8994
279 *
280 * @param priv wm8994 information pointer
281 * @param aif_id Audio interface ID
282 * @param sampling_rate Sampling rate
283 * @param bits_per_sample Bits per sample
284 * @param Channels Channels in the given audio input
285 *
286 * @return -1 for error and 0 Success.
287 */
288 static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
289 uint sampling_rate, uint bits_per_sample,
290 uint channels)
291 {
292 int aif1_reg;
293 int aif2_reg;
294 int bclk_reg;
295 int bclk = 0;
296 int rate_reg;
297 int aif1 = 0;
298 int aif2 = 0;
299 int rate_val = 0;
300 int id = aif_id - 1;
301 int i, cur_val, best_val, bclk_rate, best;
302 unsigned short reg_data;
303 int ret = 0;
304
305 switch (aif_id) {
306 case 1:
307 aif1_reg = WM8994_AIF1_CONTROL_1;
308 aif2_reg = WM8994_AIF1_CONTROL_2;
309 bclk_reg = WM8994_AIF1_BCLK;
310 rate_reg = WM8994_AIF1_RATE;
311 break;
312 case 2:
313 aif1_reg = WM8994_AIF2_CONTROL_1;
314 aif2_reg = WM8994_AIF2_CONTROL_2;
315 bclk_reg = WM8994_AIF2_BCLK;
316 rate_reg = WM8994_AIF2_RATE;
317 break;
318 default:
319 return -1;
320 }
321
322 bclk_rate = sampling_rate * 32;
323 switch (bits_per_sample) {
324 case 16:
325 bclk_rate *= 16;
326 break;
327 case 20:
328 bclk_rate *= 20;
329 aif1 |= 0x20;
330 break;
331 case 24:
332 bclk_rate *= 24;
333 aif1 |= 0x40;
334 break;
335 case 32:
336 bclk_rate *= 32;
337 aif1 |= 0x60;
338 break;
339 default:
340 return -1;
341 }
342
343 /* Try to find an appropriate sample rate; look for an exact match. */
344 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
345 if (src_rate[i] == sampling_rate)
346 break;
347
348 if (i == ARRAY_SIZE(src_rate)) {
349 debug("%s: Could not get the best matching samplingrate\n",
350 __func__);
351 return -1;
352 }
353
354 rate_val |= i << WM8994_AIF1_SR_SHIFT;
355
356 /* AIFCLK/fs ratio; look for a close match in either direction */
357 best = 0;
358 best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
359
360 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
361 cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
362 if (cur_val >= best_val)
363 continue;
364 best = i;
365 best_val = cur_val;
366 }
367
368 rate_val |= best;
369
370 /*
371 * We may not get quite the right frequency if using
372 * approximate clocks so look for the closest match that is
373 * higher than the target (we need to ensure that there enough
374 * BCLKs to clock out the samples).
375 */
376 best = 0;
377 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
378 cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
379 if (cur_val < 0) /* BCLK table is sorted */
380 break;
381 best = i;
382 }
383
384 if (i == ARRAY_SIZE(bclk_divs)) {
385 debug("%s: Could not get the best matching bclk division\n",
386 __func__);
387 return -1;
388 }
389
390 bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
391 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
392
393 if (wm8994_i2c_read(priv, aif1_reg, &reg_data) != 0) {
394 debug("%s: AIF1 register read Failed\n", __func__);
395 return -1;
396 }
397
398 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
399 aif2 |= WM8994_AIF1_MONO;
400
401 if (priv->aifclk[id] == 0) {
402 debug("%s:Audio interface clock not set\n", __func__);
403 return -1;
404 }
405
406 ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
407 ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
408 ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
409 bclk);
410 ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
411 WM8994_AIF1CLK_RATE_MASK, rate_val);
412
413 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
414
415 if (ret < 0) {
416 debug("%s: codec register access error\n", __func__);
417 return -1;
418 }
419
420 return 0;
421 }
422
423 /*
424 * Configures Audio interface Clock
425 *
426 * @param priv wm8994 information pointer
427 * @param aif Audio Interface ID
428 *
429 * @return -1 for error and 0 Success.
430 */
431 static int configure_aif_clock(struct wm8994_priv *priv, int aif)
432 {
433 int rate;
434 int reg1 = 0;
435 int offset;
436 int ret;
437
438 /* AIF(1/0) register adress offset calculated */
439 if (aif-1)
440 offset = 4;
441 else
442 offset = 0;
443
444 switch (priv->sysclk[aif - 1]) {
445 case WM8994_SYSCLK_MCLK1:
446 reg1 |= SEL_MCLK1;
447 rate = priv->mclk[0];
448 break;
449
450 case WM8994_SYSCLK_MCLK2:
451 reg1 |= SEL_MCLK2;
452 rate = priv->mclk[1];
453 break;
454
455 case WM8994_SYSCLK_FLL1:
456 reg1 |= SEL_FLL1;
457 rate = priv->fll[0].out;
458 break;
459
460 case WM8994_SYSCLK_FLL2:
461 reg1 |= SEL_FLL2;
462 rate = priv->fll[1].out;
463 break;
464
465 default:
466 debug("%s: Invalid input clock selection [%d]\n",
467 __func__, priv->sysclk[aif - 1]);
468 return -1;
469 }
470
471 /* if input clock frequenct is more than 135Mhz then divide */
472 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
473 rate /= 2;
474 reg1 |= WM8994_AIF1CLK_DIV;
475 }
476
477 priv->aifclk[aif - 1] = rate;
478
479 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
480 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
481 reg1);
482
483 if (aif == WM8994_AIF1)
484 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
485 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
486 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
487 else if (aif == WM8994_AIF2)
488 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
489 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
490 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
491 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
492
493 if (ret < 0) {
494 debug("%s: codec register access error\n", __func__);
495 return -1;
496 }
497
498 return 0;
499 }
500
501 /*
502 * Configures Audio interface for the given frequency
503 *
504 * @param priv wm8994 information
505 * @param aif_id Audio Interface
506 * @param clk_id Input Clock ID
507 * @param freq Sampling frequency in Hz
508 *
509 * @return -1 for error and 0 success.
510 */
511 static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
512 unsigned int freq)
513 {
514 int i;
515 int ret = 0;
516
517 priv->sysclk[aif_id - 1] = clk_id;
518
519 switch (clk_id) {
520 case WM8994_SYSCLK_MCLK1:
521 priv->mclk[0] = freq;
522 if (aif_id == 2) {
523 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
524 WM8994_AIF2DAC_DIV_MASK, 0);
525 }
526 break;
527
528 case WM8994_SYSCLK_MCLK2:
529 /* TODO: Set GPIO AF */
530 priv->mclk[1] = freq;
531 break;
532
533 case WM8994_SYSCLK_FLL1:
534 case WM8994_SYSCLK_FLL2:
535 break;
536
537 case WM8994_SYSCLK_OPCLK:
538 /*
539 * Special case - a division (times 10) is given and
540 * no effect on main clocking.
541 */
542 if (freq) {
543 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
544 if (opclk_divs[i] == freq)
545 break;
546 if (i == ARRAY_SIZE(opclk_divs)) {
547 debug("%s frequency divisor not found\n",
548 __func__);
549 return -1;
550 }
551 ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
552 WM8994_OPCLK_DIV_MASK, i);
553 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
554 WM8994_OPCLK_ENA,
555 WM8994_OPCLK_ENA);
556 } else {
557 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
558 WM8994_OPCLK_ENA, 0);
559 }
560
561 default:
562 debug("%s Invalid input clock selection [%d]\n",
563 __func__, clk_id);
564 return -1;
565 }
566
567 ret |= configure_aif_clock(priv, aif_id);
568
569 if (ret < 0) {
570 debug("%s: codec register access error\n", __func__);
571 return -1;
572 }
573
574 return 0;
575 }
576
577 /*
578 * Initializes Volume for AIF2 to HP path
579 *
580 * @param priv wm8994 information
581 * @returns -1 for error and 0 Success.
582 *
583 */
584 static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
585 {
586 int ret;
587
588 /* Unmute AIF2DAC */
589 ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
590 WM8994_AIF2DAC_MUTE_MASK, 0);
591
592
593 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
594 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
595 WM8994_AIF2DAC_VU | 0xff);
596
597 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
598 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
599 WM8994_AIF2DAC_VU | 0xff);
600
601
602 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
603 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
604 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
605
606 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
607 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
608 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
609 /* Head Phone Volume */
610 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
611 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
612
613 if (ret < 0) {
614 debug("%s: codec register access error\n", __func__);
615 return -1;
616 }
617
618 return 0;
619 }
620
621 /*
622 * Initializes Volume for AIF1 to HP path
623 *
624 * @param priv wm8994 information
625 * @returns -1 for error and 0 Success.
626 *
627 */
628 static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
629 {
630 int ret = 0;
631
632 /* Unmute AIF1DAC */
633 ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
634
635 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
636 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
637 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
638
639 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
640 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
641 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
642 /* Head Phone Volume */
643 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
644 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
645
646 if (ret < 0) {
647 debug("%s: codec register access error\n", __func__);
648 return -1;
649 }
650
651 return 0;
652 }
653
654 /*
655 * Intialise wm8994 codec device
656 *
657 * @param priv wm8994 information
658 *
659 * @returns -1 for error and 0 Success.
660 */
661 static int wm8994_device_init(struct wm8994_priv *priv)
662 {
663 const char *devname;
664 unsigned short reg_data;
665 int ret;
666
667 wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
668
669 ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, &reg_data);
670 if (ret < 0) {
671 debug("Failed to read ID register\n");
672 return ret;
673 }
674
675 if (reg_data == WM8994_ID) {
676 devname = "WM8994";
677 debug("Device registered as type %d\n", priv->type);
678 priv->type = WM8994;
679 } else {
680 debug("Device is not a WM8994, ID is %x\n", ret);
681 return -ENXIO;
682 }
683
684 ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, &reg_data);
685 if (ret < 0) {
686 debug("Failed to read revision register: %d\n", ret);
687 return ret;
688 }
689 priv->revision = reg_data;
690 debug("%s revision %c\n", devname, 'A' + priv->revision);
691
692 return 0;
693 }
694
695 static int wm8994_setup_interface(struct wm8994_priv *priv,
696 enum en_audio_interface aif_id)
697 {
698 int ret;
699
700 /* VMID Selection */
701 ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
702 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
703
704 /* Charge Pump Enable */
705 ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
706 WM8994_CP_ENA);
707
708 /* Head Phone Power Enable */
709 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
710 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
711
712 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
713 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
714
715 if (aif_id == WM8994_AIF1) {
716 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
717 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
718 WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
719 WM8994_IN2R_ENA);
720
721 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
722 WM8994_ADCL_ENA | WM8994_ADCR_ENA |
723 WM8994_AIF1ADC1R_ENA |
724 WM8994_AIF1ADC1L_ENA);
725
726 /* Power enable for AIF1 and DAC1 */
727 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
728 WM8994_AIF1DACL_ENA |
729 WM8994_AIF1DACR_ENA |
730 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
731 } else if (aif_id == WM8994_AIF2) {
732 /* Power enable for AIF2 and DAC1 */
733 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
734 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
735 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
736 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
737 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
738 }
739 /* Head Phone Initialisation */
740 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
741 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
742 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
743
744 ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
745 WM8994_DCS_ENA_CHAN_0_MASK |
746 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
747 WM8994_DCS_ENA_CHAN_1);
748
749 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
750 WM8994_HPOUT1L_DLY_MASK |
751 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
752 WM8994_HPOUT1R_OUTP_MASK |
753 WM8994_HPOUT1L_RMV_SHORT_MASK |
754 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
755 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
756 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
757 WM8994_HPOUT1R_RMV_SHORT);
758
759 /* MIXER Config DAC1 to HP */
760 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
761 WM8994_DAC1L_TO_HPOUT1L_MASK,
762 WM8994_DAC1L_TO_HPOUT1L);
763
764 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
765 WM8994_DAC1R_TO_HPOUT1R_MASK,
766 WM8994_DAC1R_TO_HPOUT1R);
767
768 if (aif_id == WM8994_AIF1) {
769 /* Routing AIF1 to DAC1 */
770 ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
771 WM8994_AIF1DAC1L_TO_DAC1L);
772
773 ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
774 WM8994_AIF1DAC1R_TO_DAC1R);
775
776 /* GPIO Settings for AIF1 */
777 ret |= wm8994_i2c_write(priv, WM8994_GPIO_1,
778 WM8994_GPIO_DIR_OUTPUT |
779 WM8994_GPIO_FUNCTION_I2S_CLK |
780 WM8994_GPIO_INPUT_DEBOUNCE);
781
782 ret |= wm8994_init_volume_aif1_dac1(priv);
783 } else if (aif_id == WM8994_AIF2) {
784 /* Routing AIF2 to DAC1 */
785 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
786 WM8994_AIF2DACL_TO_DAC1L_MASK,
787 WM8994_AIF2DACL_TO_DAC1L);
788
789 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
790 WM8994_AIF2DACR_TO_DAC1R_MASK,
791 WM8994_AIF2DACR_TO_DAC1R);
792
793 /* GPIO Settings for AIF2 */
794 /* B CLK */
795 ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
796 WM8994_GPIO_FUNCTION_MASK,
797 WM8994_GPIO_DIR_OUTPUT);
798
799 /* LR CLK */
800 ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
801 WM8994_GPIO_FUNCTION_MASK,
802 WM8994_GPIO_DIR_OUTPUT);
803
804 /* DATA */
805 ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
806 WM8994_GPIO_FUNCTION_MASK,
807 WM8994_GPIO_DIR_OUTPUT);
808
809 ret |= wm8994_init_volume_aif2_dac1(priv);
810 }
811
812 if (ret < 0)
813 goto err;
814
815 debug("%s: Codec chip setup ok\n", __func__);
816 return 0;
817 err:
818 debug("%s: Codec chip setup error\n", __func__);
819 return -1;
820 }
821
822 #ifndef CONFIG_DM_SOUND
823 /*
824 * Gets fdt values for wm8994 config parameters
825 *
826 * @param pcodec_info codec information structure
827 * @param blob FDT blob
828 * @return int value, 0 for success
829 */
830 static int get_codec_values(struct sound_codec_info *pcodec_info,
831 const void *blob)
832 {
833 int error = 0;
834 enum fdt_compat_id compat;
835 int node;
836 int parent;
837
838 /* Get the node from FDT for codec */
839 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
840 if (node <= 0) {
841 debug("EXYNOS_SOUND: No node for codec in device tree\n");
842 debug("node = %d\n", node);
843 return -1;
844 }
845
846 parent = fdt_parent_offset(blob, node);
847 if (parent < 0) {
848 debug("%s: Cannot find node parent\n", __func__);
849 return -1;
850 }
851
852 compat = fdtdec_lookup(blob, parent);
853 switch (compat) {
854 case COMPAT_SAMSUNG_S3C2440_I2C:
855 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
856 error |= pcodec_info->i2c_bus;
857 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
858 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
859 "reg", 0);
860 error |= pcodec_info->i2c_dev_addr;
861 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
862 break;
863 default:
864 debug("%s: Unknown compat id %d\n", __func__, compat);
865 return -1;
866 }
867
868 if (error == -1) {
869 debug("fail to get wm8994 codec node properties\n");
870 return -1;
871 }
872
873 return 0;
874 }
875 #endif
876
877 static int _wm8994_init(struct wm8994_priv *priv,
878 enum en_audio_interface aif_id, int sampling_rate,
879 int mclk_freq, int bits_per_sample,
880 unsigned int channels)
881 {
882 int ret;
883
884 ret = wm8994_setup_interface(priv, aif_id);
885 if (ret < 0) {
886 debug("%s: wm8994 codec chip init failed\n", __func__);
887 return ret;
888 }
889
890 ret = wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
891 if (ret < 0) {
892 debug("%s: wm8994 codec set sys clock failed\n", __func__);
893 return ret;
894 }
895
896 ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
897 channels);
898
899 if (ret == 0) {
900 ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
901 SND_SOC_DAIFMT_NB_NF |
902 SND_SOC_DAIFMT_CBS_CFS);
903 }
904
905 return ret;
906 }
907
908 #ifndef CONFIG_DM_SOUND
909 /* WM8994 Device Initialisation */
910 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
911 int sampling_rate, int mclk_freq, int bits_per_sample,
912 unsigned int channels)
913 {
914 struct sound_codec_info pcodec_info;
915 struct wm8994_priv wm8994_info;
916 int ret;
917
918 /* Get the codec Values */
919 if (get_codec_values(&pcodec_info, blob) < 0) {
920 debug("FDT Codec values failed\n");
921 return -1;
922 }
923
924 /* shift the device address by 1 for 7 bit addressing */
925 wm8994_info.i2c_addr = pcodec_info.i2c_dev_addr;
926 i2c_set_bus_num(pcodec_info.i2c_bus);
927 ret = wm8994_device_init(&wm8994_info);
928 if (ret < 0) {
929 debug("%s: wm8994 codec chip init failed\n", __func__);
930 return ret;
931 }
932
933 return _wm8994_init(&wm8994_info, aif_id, sampling_rate, mclk_freq,
934 bits_per_sample, channels);
935 }
936 #endif
937
938 static int wm8994_set_params(struct udevice *dev, int interface, int rate,
939 int mclk_freq, int bits_per_sample, uint channels)
940 {
941 struct wm8994_priv *priv = dev_get_priv(dev);
942
943 return _wm8994_init(priv, interface, rate, mclk_freq, bits_per_sample,
944 channels);
945 }
946
947 static int wm8994_probe(struct udevice *dev)
948 {
949 struct wm8994_priv *priv = dev_get_priv(dev);
950
951 priv->dev = dev;
952 return wm8994_device_init(priv);
953 }
954
955 static const struct audio_codec_ops wm8994_ops = {
956 .set_params = wm8994_set_params,
957 };
958
959 static const struct udevice_id wm8994_ids[] = {
960 { .compatible = "wolfson,wm8994" },
961 { }
962 };
963
964 U_BOOT_DRIVER(wm8994) = {
965 .name = "wm8994",
966 .id = UCLASS_AUDIO_CODEC,
967 .of_match = wm8994_ids,
968 .probe = wm8994_probe,
969 .ops = &wm8994_ops,
970 .priv_auto_alloc_size = sizeof(struct wm8994_priv),
971 };
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