drivers/spi/atmel-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Atmel QSPI Controller
   4  *
   5  * Copyright (C) 2015 Atmel Corporation
   6  * Copyright (C) 2018 Cryptera A/S
   7  *
   8  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
   9  * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
  10  *
  11  * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spi/spi-mem.h>
  25
  26 /* QSPI register offsets */
  27 #define QSPI_CR      0x0000  /* Control Register */
  28 #define QSPI_MR      0x0004  /* Mode Register */
  29 #define QSPI_RD      0x0008  /* Receive Data Register */
  30 #define QSPI_TD      0x000c  /* Transmit Data Register */
  31 #define QSPI_SR      0x0010  /* Status Register */
  32 #define QSPI_IER     0x0014  /* Interrupt Enable Register */
  33 #define QSPI_IDR     0x0018  /* Interrupt Disable Register */
  34 #define QSPI_IMR     0x001c  /* Interrupt Mask Register */
  35 #define QSPI_SCR     0x0020  /* Serial Clock Register */
  36
  37 #define QSPI_IAR     0x0030  /* Instruction Address Register */
  38 #define QSPI_ICR     0x0034  /* Instruction Code Register */
  39 #define QSPI_WICR    0x0034  /* Write Instruction Code Register */
  40 #define QSPI_IFR     0x0038  /* Instruction Frame Register */
  41 #define QSPI_RICR    0x003C  /* Read Instruction Code Register */
  42
  43 #define QSPI_SMR     0x0040  /* Scrambling Mode Register */
  44 #define QSPI_SKR     0x0044  /* Scrambling Key Register */
  45
  46 #define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
  47 #define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
  48
  49 #define QSPI_VERSION 0x00FC  /* Version Register */
  50
  51
  52 /* Bitfields in QSPI_CR (Control Register) */
  53 #define QSPI_CR_QSPIEN                  BIT(0)
  54 #define QSPI_CR_QSPIDIS                 BIT(1)
  55 #define QSPI_CR_SWRST                   BIT(7)
  56 #define QSPI_CR_LASTXFER                BIT(24)
  57
  58 /* Bitfields in QSPI_MR (Mode Register) */
  59 #define QSPI_MR_SMM                     BIT(0)
  60 #define QSPI_MR_LLB                     BIT(1)
  61 #define QSPI_MR_WDRBT                   BIT(2)
  62 #define QSPI_MR_SMRM                    BIT(3)
  63 #define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
  64 #define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
  65 #define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
  66 #define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
  67 #define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
  68 #define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  69 #define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
  70 #define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  71 #define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
  72 #define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
  73
  74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
  75 #define QSPI_SR_RDRF                    BIT(0)
  76 #define QSPI_SR_TDRE                    BIT(1)
  77 #define QSPI_SR_TXEMPTY                 BIT(2)
  78 #define QSPI_SR_OVRES                   BIT(3)
  79 #define QSPI_SR_CSR                     BIT(8)
  80 #define QSPI_SR_CSS                     BIT(9)
  81 #define QSPI_SR_INSTRE                  BIT(10)
  82 #define QSPI_SR_QSPIENS                 BIT(24)
  83
  84 #define QSPI_SR_CMD_COMPLETED   (QSPI_SR_INSTRE | QSPI_SR_CSR)
  85
  86 /* Bitfields in QSPI_SCR (Serial Clock Register) */
  87 #define QSPI_SCR_CPOL                   BIT(0)
  88 #define QSPI_SCR_CPHA                   BIT(1)
  89 #define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
  90 #define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
  91 #define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
  92 #define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
  93
  94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
  95 #define QSPI_ICR_INST_MASK              GENMASK(7, 0)
  96 #define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
  97 #define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
  98 #define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
  99
 100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
 101 #define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
 102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
 103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
 104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
 105 #define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
 106 #define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
 107 #define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
 108 #define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
 109 #define QSPI_IFR_INSTEN                 BIT(4)
 110 #define QSPI_IFR_ADDREN                 BIT(5)
 111 #define QSPI_IFR_OPTEN                  BIT(6)
 112 #define QSPI_IFR_DATAEN                 BIT(7)
 113 #define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
 114 #define QSPI_IFR_OPTL_1BIT              (0 << 8)
 115 #define QSPI_IFR_OPTL_2BIT              (1 << 8)
 116 #define QSPI_IFR_OPTL_4BIT              (2 << 8)
 117 #define QSPI_IFR_OPTL_8BIT              (3 << 8)
 118 #define QSPI_IFR_ADDRL                  BIT(10)
 119 #define QSPI_IFR_TFRTYP_MEM             BIT(12)
 120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR    BIT(13)
 121 #define QSPI_IFR_CRM                    BIT(14)
 122 #define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
 123 #define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
 124 #define QSPI_IFR_APBTFRTYP_READ         BIT(24) /* Defined in SAM9X60 */
 125
 126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
 127 #define QSPI_SMR_SCREN                  BIT(0)
 128 #define QSPI_SMR_RVDIS                  BIT(1)
 129
 130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
 131 #define QSPI_WPMR_WPEN                  BIT(0)
 132 #define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
 133 #define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
 134
 135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
 136 #define QSPI_WPSR_WPVS                  BIT(0)
 137 #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
 138 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
 139
 140 struct atmel_qspi_caps {
 141         bool has_qspick;
 142         bool has_ricr;
 143 };
 144
 145 struct atmel_qspi {
 146         void __iomem            *regs;
 147         void __iomem            *mem;
 148         struct clk              *pclk;
 149         struct clk              *qspick;
 150         struct platform_device  *pdev;
 151         const struct atmel_qspi_caps *caps;
 152         resource_size_t         mmap_size;
 153         u32                     pending;
 154         u32                     mr;
 155         u32                     scr;
 156         struct completion       cmd_completion;
 157 };
 158
 159 struct atmel_qspi_mode {
 160         u8 cmd_buswidth;
 161         u8 addr_buswidth;
 162         u8 data_buswidth;
 163         u32 config;
 164 };
 165
 166 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
 167         { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
 168         { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
 169         { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
 170         { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
 171         { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
 172         { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
 173         { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
 174 };
 175
 176 #ifdef VERBOSE_DEBUG
 177 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
 178 {
 179         switch (offset) {
 180         case QSPI_CR:
 181                 return "CR";
 182         case QSPI_MR:
 183                 return "MR";
 184         case QSPI_RD:
 185                 return "MR";
 186         case QSPI_TD:
 187                 return "TD";
 188         case QSPI_SR:
 189                 return "SR";
 190         case QSPI_IER:
 191                 return "IER";
 192         case QSPI_IDR:
 193                 return "IDR";
 194         case QSPI_IMR:
 195                 return "IMR";
 196         case QSPI_SCR:
 197                 return "SCR";
 198         case QSPI_IAR:
 199                 return "IAR";
 200         case QSPI_ICR:
 201                 return "ICR/WICR";
 202         case QSPI_IFR:
 203                 return "IFR";
 204         case QSPI_RICR:
 205                 return "RICR";
 206         case QSPI_SMR:
 207                 return "SMR";
 208         case QSPI_SKR:
 209                 return "SKR";
 210         case QSPI_WPMR:
 211                 return "WPMR";
 212         case QSPI_WPSR:
 213                 return "WPSR";
 214         case QSPI_VERSION:
 215                 return "VERSION";
 216         default:
 217                 snprintf(tmp, sz, "0x%02x", offset);
 218                 break;
 219         }
 220
 221         return tmp;
 222 }
 223 #endif /* VERBOSE_DEBUG */
 224
 225 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
 226 {
 227         u32 value = readl_relaxed(aq->regs + offset);
 228
 229 #ifdef VERBOSE_DEBUG
 230         char tmp[8];
 231
 232         dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
 233                  atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
 234 #endif /* VERBOSE_DEBUG */
 235
 236         return value;
 237 }
 238
 239 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
 240 {
 241 #ifdef VERBOSE_DEBUG
 242         char tmp[8];
 243
 244         dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
 245                  atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
 246 #endif /* VERBOSE_DEBUG */
 247
 248         writel_relaxed(value, aq->regs + offset);
 249 }
 250
 251 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
 252                                             const struct atmel_qspi_mode *mode)
 253 {
 254         if (op->cmd.buswidth != mode->cmd_buswidth)
 255                 return false;
 256
 257         if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
 258                 return false;
 259
 260         if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
 261                 return false;
 262
 263         return true;
 264 }
 265
 266 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
 267 {
 268         u32 i;
 269
 270         for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
 271                 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
 272                         return i;
 273
 274         return -ENOTSUPP;
 275 }
 276
 277 static bool atmel_qspi_supports_op(struct spi_mem *mem,
 278                                    const struct spi_mem_op *op)
 279 {
 280         if (atmel_qspi_find_mode(op) < 0)
 281                 return false;
 282
 283         /* special case not supported by hardware */
 284         if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
 285                 op->dummy.nbytes == 0)
 286                 return false;
 287
 288         return true;
 289 }
 290
 291 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 292                               const struct spi_mem_op *op, u32 *offset)
 293 {
 294         u32 iar, icr, ifr;
 295         u32 dummy_cycles = 0;
 296         int mode;
 297
 298         iar = 0;
 299         icr = QSPI_ICR_INST(op->cmd.opcode);
 300         ifr = QSPI_IFR_INSTEN;
 301
 302         mode = atmel_qspi_find_mode(op);
 303         if (mode < 0)
 304                 return mode;
 305         ifr |= atmel_qspi_modes[mode].config;
 306
 307         if (op->dummy.buswidth && op->dummy.nbytes)
 308                 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 309
 310         /*
 311          * The controller allows 24 and 32-bit addressing while NAND-flash
 312          * requires 16-bit long. Handling 8-bit long addresses is done using
 313          * the option field. For the 16-bit addresses, the workaround depends
 314          * of the number of requested dummy bits. If there are 8 or more dummy
 315          * cycles, the address is shifted and sent with the first dummy byte.
 316          * Otherwise opcode is disabled and the first byte of the address
 317          * contains the command opcode (works only if the opcode and address
 318          * use the same buswidth). The limitation is when the 16-bit address is
 319          * used without enough dummy cycles and the opcode is using a different
 320          * buswidth than the address.
 321          */
 322         if (op->addr.buswidth) {
 323                 switch (op->addr.nbytes) {
 324                 case 0:
 325                         break;
 326                 case 1:
 327                         ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
 328                         icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
 329                         break;
 330                 case 2:
 331                         if (dummy_cycles < 8 / op->addr.buswidth) {
 332                                 ifr &= ~QSPI_IFR_INSTEN;
 333                                 ifr |= QSPI_IFR_ADDREN;
 334                                 iar = (op->cmd.opcode << 16) |
 335                                         (op->addr.val & 0xffff);
 336                         } else {
 337                                 ifr |= QSPI_IFR_ADDREN;
 338                                 iar = (op->addr.val << 8) & 0xffffff;
 339                                 dummy_cycles -= 8 / op->addr.buswidth;
 340                         }
 341                         break;
 342                 case 3:
 343                         ifr |= QSPI_IFR_ADDREN;
 344                         iar = op->addr.val & 0xffffff;
 345                         break;
 346                 case 4:
 347                         ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
 348                         iar = op->addr.val & 0x7ffffff;
 349                         break;
 350                 default:
 351                         return -ENOTSUPP;
 352                 }
 353         }
 354
 355         /* offset of the data access in the QSPI memory space */
 356         *offset = iar;
 357
 358         /* Set number of dummy cycles */
 359         if (dummy_cycles)
 360                 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
 361
 362         /* Set data enable */
 363         if (op->data.nbytes)
 364                 ifr |= QSPI_IFR_DATAEN;
 365
 366         /*
 367          * If the QSPI controller is set in regular SPI mode, set it in
 368          * Serial Memory Mode (SMM).
 369          */
 370         if (aq->mr != QSPI_MR_SMM) {
 371                 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
 372                 aq->mr = QSPI_MR_SMM;
 373         }
 374
 375         /* Clear pending interrupts */
 376         (void)atmel_qspi_read(aq, QSPI_SR);
 377
 378         if (aq->caps->has_ricr) {
 379                 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
 380                         ifr |= QSPI_IFR_APBTFRTYP_READ;
 381
 382                 /* Set QSPI Instruction Frame registers */
 383                 atmel_qspi_write(iar, aq, QSPI_IAR);
 384                 if (op->data.dir == SPI_MEM_DATA_IN)
 385                         atmel_qspi_write(icr, aq, QSPI_RICR);
 386                 else
 387                         atmel_qspi_write(icr, aq, QSPI_WICR);
 388                 atmel_qspi_write(ifr, aq, QSPI_IFR);
 389         } else {
 390                 if (op->data.dir == SPI_MEM_DATA_OUT)
 391                         ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
 392
 393                 /* Set QSPI Instruction Frame registers */
 394                 atmel_qspi_write(iar, aq, QSPI_IAR);
 395                 atmel_qspi_write(icr, aq, QSPI_ICR);
 396                 atmel_qspi_write(ifr, aq, QSPI_IFR);
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 403 {
 404         struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
 405         u32 sr, offset;
 406         int err;
 407
 408         /*
 409          * Check if the address exceeds the MMIO window size. An improvement
 410          * would be to add support for regular SPI mode and fall back to it
 411          * when the flash memories overrun the controller's memory space.
 412          */
 413         if (op->addr.val + op->data.nbytes > aq->mmap_size)
 414                 return -ENOTSUPP;
 415
 416         err = atmel_qspi_set_cfg(aq, op, &offset);
 417         if (err)
 418                 return err;
 419
 420         /* Skip to the final steps if there is no data */
 421         if (op->data.nbytes) {
 422                 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
 423                 (void)atmel_qspi_read(aq, QSPI_IFR);
 424
 425                 /* Send/Receive data */
 426                 if (op->data.dir == SPI_MEM_DATA_IN)
 427                         _memcpy_fromio(op->data.buf.in, aq->mem + offset,
 428                                        op->data.nbytes);
 429                 else
 430                         _memcpy_toio(aq->mem + offset, op->data.buf.out,
 431                                      op->data.nbytes);
 432
 433                 /* Release the chip-select */
 434                 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
 435         }
 436
 437         /* Poll INSTRuction End status */
 438         sr = atmel_qspi_read(aq, QSPI_SR);
 439         if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 440                 return err;
 441
 442         /* Wait for INSTRuction End interrupt */
 443         reinit_completion(&aq->cmd_completion);
 444         aq->pending = sr & QSPI_SR_CMD_COMPLETED;
 445         atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
 446         if (!wait_for_completion_timeout(&aq->cmd_completion,
 447                                          msecs_to_jiffies(1000)))
 448                 err = -ETIMEDOUT;
 449         atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
 450
 451         return err;
 452 }
 453
 454 static const char *atmel_qspi_get_name(struct spi_mem *spimem)
 455 {
 456         return dev_name(spimem->spi->dev.parent);
 457 }
 458
 459 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
 460         .supports_op = atmel_qspi_supports_op,
 461         .exec_op = atmel_qspi_exec_op,
 462         .get_name = atmel_qspi_get_name
 463 };
 464
 465 static int atmel_qspi_setup(struct spi_device *spi)
 466 {
 467         struct spi_controller *ctrl = spi->master;
 468         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 469         unsigned long src_rate;
 470         u32 scbr;
 471
 472         if (ctrl->busy)
 473                 return -EBUSY;
 474
 475         if (!spi->max_speed_hz)
 476                 return -EINVAL;
 477
 478         src_rate = clk_get_rate(aq->pclk);
 479         if (!src_rate)
 480                 return -EINVAL;
 481
 482         /* Compute the QSPI baudrate */
 483         scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
 484         if (scbr > 0)
 485                 scbr--;
 486
 487         aq->scr = QSPI_SCR_SCBR(scbr);
 488         atmel_qspi_write(aq->scr, aq, QSPI_SCR);
 489
 490         return 0;
 491 }
 492
 493 static void atmel_qspi_init(struct atmel_qspi *aq)
 494 {
 495         /* Reset the QSPI controller */
 496         atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
 497
 498         /* Set the QSPI controller by default in Serial Memory Mode */
 499         atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
 500         aq->mr = QSPI_MR_SMM;
 501
 502         /* Enable the QSPI controller */
 503         atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
 504 }
 505
 506 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
 507 {
 508         struct atmel_qspi *aq = dev_id;
 509         u32 status, mask, pending;
 510
 511         status = atmel_qspi_read(aq, QSPI_SR);
 512         mask = atmel_qspi_read(aq, QSPI_IMR);
 513         pending = status & mask;
 514
 515         if (!pending)
 516                 return IRQ_NONE;
 517
 518         aq->pending |= pending;
 519         if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 520                 complete(&aq->cmd_completion);
 521
 522         return IRQ_HANDLED;
 523 }
 524
 525 static int atmel_qspi_probe(struct platform_device *pdev)
 526 {
 527         struct spi_controller *ctrl;
 528         struct atmel_qspi *aq;
 529         struct resource *res;
 530         int irq, err = 0;
 531
 532         ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
 533         if (!ctrl)
 534                 return -ENOMEM;
 535
 536         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
 537         ctrl->setup = atmel_qspi_setup;
 538         ctrl->bus_num = -1;
 539         ctrl->mem_ops = &atmel_qspi_mem_ops;
 540         ctrl->num_chipselect = 1;
 541         ctrl->dev.of_node = pdev->dev.of_node;
 542         platform_set_drvdata(pdev, ctrl);
 543
 544         aq = spi_controller_get_devdata(ctrl);
 545
 546         init_completion(&aq->cmd_completion);
 547         aq->pdev = pdev;
 548
 549         /* Map the registers */
 550         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 551         aq->regs = devm_ioremap_resource(&pdev->dev, res);
 552         if (IS_ERR(aq->regs)) {
 553                 dev_err(&pdev->dev, "missing registers\n");
 554                 err = PTR_ERR(aq->regs);
 555                 goto exit;
 556         }
 557
 558         /* Map the AHB memory */
 559         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
 560         aq->mem = devm_ioremap_resource(&pdev->dev, res);
 561         if (IS_ERR(aq->mem)) {
 562                 dev_err(&pdev->dev, "missing AHB memory\n");
 563                 err = PTR_ERR(aq->mem);
 564                 goto exit;
 565         }
 566
 567         aq->mmap_size = resource_size(res);
 568
 569         /* Get the peripheral clock */
 570         aq->pclk = devm_clk_get(&pdev->dev, "pclk");
 571         if (IS_ERR(aq->pclk))
 572                 aq->pclk = devm_clk_get(&pdev->dev, NULL);
 573
 574         if (IS_ERR(aq->pclk)) {
 575                 dev_err(&pdev->dev, "missing peripheral clock\n");
 576                 err = PTR_ERR(aq->pclk);
 577                 goto exit;
 578         }
 579
 580         /* Enable the peripheral clock */
 581         err = clk_prepare_enable(aq->pclk);
 582         if (err) {
 583                 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
 584                 goto exit;
 585         }
 586
 587         aq->caps = of_device_get_match_data(&pdev->dev);
 588         if (!aq->caps) {
 589                 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
 590                 err = -EINVAL;
 591                 goto exit;
 592         }
 593
 594         if (aq->caps->has_qspick) {
 595                 /* Get the QSPI system clock */
 596                 aq->qspick = devm_clk_get(&pdev->dev, "qspick");
 597                 if (IS_ERR(aq->qspick)) {
 598                         dev_err(&pdev->dev, "missing system clock\n");
 599                         err = PTR_ERR(aq->qspick);
 600                         goto disable_pclk;
 601                 }
 602
 603                 /* Enable the QSPI system clock */
 604                 err = clk_prepare_enable(aq->qspick);
 605                 if (err) {
 606                         dev_err(&pdev->dev,
 607                                 "failed to enable the QSPI system clock\n");
 608                         goto disable_pclk;
 609                 }
 610         }
 611
 612         /* Request the IRQ */
 613         irq = platform_get_irq(pdev, 0);
 614         if (irq < 0) {
 615                 err = irq;
 616                 goto disable_qspick;
 617         }
 618         err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
 619                                0, dev_name(&pdev->dev), aq);
 620         if (err)
 621                 goto disable_qspick;
 622
 623         atmel_qspi_init(aq);
 624
 625         err = spi_register_controller(ctrl);
 626         if (err)
 627                 goto disable_qspick;
 628
 629         return 0;
 630
 631 disable_qspick:
 632         clk_disable_unprepare(aq->qspick);
 633 disable_pclk:
 634         clk_disable_unprepare(aq->pclk);
 635 exit:
 636         spi_controller_put(ctrl);
 637
 638         return err;
 639 }
 640
 641 static int atmel_qspi_remove(struct platform_device *pdev)
 642 {
 643         struct spi_controller *ctrl = platform_get_drvdata(pdev);
 644         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 645
 646         spi_unregister_controller(ctrl);
 647         atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
 648         clk_disable_unprepare(aq->qspick);
 649         clk_disable_unprepare(aq->pclk);
 650         return 0;
 651 }
 652
 653 static int __maybe_unused atmel_qspi_suspend(struct device *dev)
 654 {
 655         struct spi_controller *ctrl = dev_get_drvdata(dev);
 656         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 657
 658         clk_disable_unprepare(aq->qspick);
 659         clk_disable_unprepare(aq->pclk);
 660
 661         return 0;
 662 }
 663
 664 static int __maybe_unused atmel_qspi_resume(struct device *dev)
 665 {
 666         struct spi_controller *ctrl = dev_get_drvdata(dev);
 667         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 668
 669         clk_prepare_enable(aq->pclk);
 670         clk_prepare_enable(aq->qspick);
 671
 672         atmel_qspi_init(aq);
 673
 674         atmel_qspi_write(aq->scr, aq, QSPI_SCR);
 675
 676         return 0;
 677 }
 678
 679 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
 680                          atmel_qspi_resume);
 681
 682 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
 683
 684 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
 685         .has_qspick = true,
 686         .has_ricr = true,
 687 };
 688
 689 static const struct of_device_id atmel_qspi_dt_ids[] = {
 690         {
 691                 .compatible = "atmel,sama5d2-qspi",
 692                 .data = &atmel_sama5d2_qspi_caps,
 693         },
 694         {
 695                 .compatible = "microchip,sam9x60-qspi",
 696                 .data = &atmel_sam9x60_qspi_caps,
 697         },
 698         { /* sentinel */ }
 699 };
 700
 701 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
 702
 703 static struct platform_driver atmel_qspi_driver = {
 704         .driver = {
 705                 .name   = "atmel_qspi",
 706                 .of_match_table = atmel_qspi_dt_ids,
 707                 .pm     = &atmel_qspi_pm_ops,
 708         },
 709         .probe          = atmel_qspi_probe,
 710         .remove         = atmel_qspi_remove,
 711 };
 712 module_platform_driver(atmel_qspi_driver);
 713
 714 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
 715 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
 716 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
 717 MODULE_LICENSE("GPL v2");