drivers/spi/atmel_dataflash_spi.c

   1 /*
   2  * Driver for ATMEL DataFlash support
   3  * Author : Hamid Ikdoumi (Atmel)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  */
  21
  22 #include <common.h>
  23 #ifndef CONFIG_AT91_LEGACY
  24 #define CONFIG_AT91_LEGACY
  25 #warning Please update to use C structur SoC access !
  26 #endif
  27 #include <asm/arch/hardware.h>
  28 #include <asm/arch/clk.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/arch/io.h>
  31 #include <asm/arch/at91_pio.h>
  32 #include <asm/arch/at91_spi.h>
  33
  34 #include <dataflash.h>
  35
  36 #define AT91_SPI_PCS0_DATAFLASH_CARD    0xE     /* Chip Select 0: NPCS0%1110 */
  37 #define AT91_SPI_PCS1_DATAFLASH_CARD    0xD     /* Chip Select 1: NPCS1%1101 */
  38 #define AT91_SPI_PCS2_DATAFLASH_CARD    0xB     /* Chip Select 2: NPCS2%1011 */
  39 #define AT91_SPI_PCS3_DATAFLASH_CARD    0x7     /* Chip Select 3: NPCS3%0111 */
  40
  41 void AT91F_SpiInit(void)
  42 {
  43         /* Reset the SPI */
  44         writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
  45
  46         /* Configure SPI in Master Mode with No CS selected !!! */
  47         writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
  48                AT91_BASE_SPI + AT91_SPI_MR);
  49
  50         /* Configure CS0 */
  51         writel(AT91_SPI_NCPHA |
  52                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  53                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  54                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  55                AT91_BASE_SPI + AT91_SPI_CSR(0));
  56
  57 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
  58         /* Configure CS1 */
  59         writel(AT91_SPI_NCPHA |
  60                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  61                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  62                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  63                AT91_BASE_SPI + AT91_SPI_CSR(1));
  64 #endif
  65 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
  66         /* Configure CS2 */
  67         writel(AT91_SPI_NCPHA |
  68                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  69                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  70                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  71                AT91_BASE_SPI + AT91_SPI_CSR(2));
  72 #endif
  73 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
  74         /* Configure CS3 */
  75         writel(AT91_SPI_NCPHA |
  76                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  77                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  78                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  79                AT91_BASE_SPI + AT91_SPI_CSR(3));
  80 #endif
  81
  82         /* SPI_Enable */
  83         writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
  84
  85         while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
  86
  87         /*
  88          * Add tempo to get SPI in a safe state.
  89          * Should not be needed for new silicon (Rev B)
  90          */
  91         udelay(500000);
  92         readl(AT91_BASE_SPI + AT91_SPI_SR);
  93         readl(AT91_BASE_SPI + AT91_SPI_RDR);
  94
  95 }
  96
  97 void AT91F_SpiEnable(int cs)
  98 {
  99         unsigned long mode;
 100
 101         switch (cs) {
 102         case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
 103                 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
 104                 mode &= 0xFFF0FFFF;
 105                 writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 106                        AT91_BASE_SPI + AT91_SPI_MR);
 107                 break;
 108         case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
 109                 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
 110                 mode &= 0xFFF0FFFF;
 111                 writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 112                        AT91_BASE_SPI + AT91_SPI_MR);
 113                 break;
 114         case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
 115                 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
 116                 mode &= 0xFFF0FFFF;
 117                 writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 118                        AT91_BASE_SPI + AT91_SPI_MR);
 119                 break;
 120         case 3:
 121                 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
 122                 mode &= 0xFFF0FFFF;
 123                 writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 124                        AT91_BASE_SPI + AT91_SPI_MR);
 125                 break;
 126         }
 127
 128         /* SPI_Enable */
 129         writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
 130 }
 131
 132 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
 133
 134 unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
 135 {
 136         unsigned int timeout;
 137
 138         pDesc->state = BUSY;
 139
 140         writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
 141
 142         /* Initialize the Transmit and Receive Pointer */
 143         writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
 144         writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
 145
 146         /* Intialize the Transmit and Receive Counters */
 147         writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
 148         writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
 149
 150         if (pDesc->tx_data_size != 0) {
 151                 /* Initialize the Next Transmit and Next Receive Pointer */
 152                 writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
 153                 writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
 154
 155                 /* Intialize the Next Transmit and Next Receive Counters */
 156                 writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
 157                 writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
 158         }
 159
 160         /* arm simple, non interrupt dependent timer */
 161         reset_timer_masked();
 162         timeout = 0;
 163
 164         writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
 165         while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
 166                 ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
 167         writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
 168         pDesc->state = IDLE;
 169
 170         if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
 171                 printf("Error Timeout\n\r");
 172                 return DATAFLASH_ERROR;
 173         }
 174
 175         return DATAFLASH_OK;
 176 }