2 * Driver for ATMEL DataFlash support
3 * Author : Hamid Ikdoumi (Atmel)
5 * SPDX-License-Identifier: GPL-2.0+
9 * This driver desperately needs rework:
11 * - use structure SoC access
12 * - get rid of including asm/arch/at91_spi.h
13 * - remove asm/arch/at91_spi.h
14 * - get rid of all CONFIG_ATMEL_LEGACY defines and uses
16 * 02-Aug-2010 Reinhard Meyer <uboot@emk-elektronik.de>
20 #ifndef CONFIG_ATMEL_LEGACY
21 # define CONFIG_ATMEL_LEGACY
28 #include <asm/arch/clk.h>
29 #include <asm/arch/hardware.h>
31 #include "atmel_spi.h"
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/at91_pio.h>
35 #include <asm/arch/at91_spi.h>
37 #include <dataflash.h>
39 #define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
40 #define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */
41 #define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */
42 #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
44 void AT91F_SpiInit(void)
47 writel(AT91_SPI_SWRST
, ATMEL_BASE_SPI0
+ AT91_SPI_CR
);
49 /* Configure SPI in Master Mode with No CS selected !!! */
50 writel(AT91_SPI_MSTR
| AT91_SPI_MODFDIS
| AT91_SPI_PCS
,
51 ATMEL_BASE_SPI0
+ AT91_SPI_MR
);
54 writel(AT91_SPI_NCPHA
|
55 (AT91_SPI_DLYBS
& DATAFLASH_TCSS
) |
56 (AT91_SPI_DLYBCT
& DATAFLASH_TCHS
) |
57 ((get_mck_clk_rate() / AT91_SPI_CLK
) << 8),
58 ATMEL_BASE_SPI0
+ AT91_SPI_CSR(0));
60 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
62 writel(AT91_SPI_NCPHA
|
63 (AT91_SPI_DLYBS
& DATAFLASH_TCSS
) |
64 (AT91_SPI_DLYBCT
& DATAFLASH_TCHS
) |
65 ((get_mck_clk_rate() / AT91_SPI_CLK
) << 8),
66 ATMEL_BASE_SPI0
+ AT91_SPI_CSR(1));
68 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
70 writel(AT91_SPI_NCPHA
|
71 (AT91_SPI_DLYBS
& DATAFLASH_TCSS
) |
72 (AT91_SPI_DLYBCT
& DATAFLASH_TCHS
) |
73 ((get_mck_clk_rate() / AT91_SPI_CLK
) << 8),
74 ATMEL_BASE_SPI0
+ AT91_SPI_CSR(2));
76 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
78 writel(AT91_SPI_NCPHA
|
79 (AT91_SPI_DLYBS
& DATAFLASH_TCSS
) |
80 (AT91_SPI_DLYBCT
& DATAFLASH_TCHS
) |
81 ((get_mck_clk_rate() / AT91_SPI_CLK
) << 8),
82 ATMEL_BASE_SPI0
+ AT91_SPI_CSR(3));
86 writel(AT91_SPI_SPIEN
, ATMEL_BASE_SPI0
+ AT91_SPI_CR
);
88 while (!(readl(ATMEL_BASE_SPI0
+ AT91_SPI_SR
) & AT91_SPI_SPIENS
))
92 * Add tempo to get SPI in a safe state.
93 * Should not be needed for new silicon (Rev B)
96 readl(ATMEL_BASE_SPI0
+ AT91_SPI_SR
);
97 readl(ATMEL_BASE_SPI0
+ AT91_SPI_RDR
);
101 void AT91F_SpiEnable(int cs
)
105 mode
= readl(ATMEL_BASE_SPI0
+ AT91_SPI_MR
);
106 mode
&= ~AT91_SPI_PCS
;
110 mode
|= AT91_SPI_PCS0_DATAFLASH_CARD
<< 16;
113 mode
|= AT91_SPI_PCS1_DATAFLASH_CARD
<< 16;
116 mode
|= AT91_SPI_PCS2_DATAFLASH_CARD
<< 16;
119 mode
|= AT91_SPI_PCS3_DATAFLASH_CARD
<< 16;
123 writel(mode
, ATMEL_BASE_SPI0
+ AT91_SPI_MR
);
126 writel(AT91_SPI_SPIEN
, ATMEL_BASE_SPI0
+ AT91_SPI_CR
);
129 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc
);
131 unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc
)
133 unsigned int timeout
;
134 unsigned int timebase
;
138 writel(AT91_SPI_TXTDIS
+ AT91_SPI_RXTDIS
,
139 ATMEL_BASE_SPI0
+ AT91_SPI_PTCR
);
141 /* Initialize the Transmit and Receive Pointer */
142 writel((unsigned int)pDesc
->rx_cmd_pt
,
143 ATMEL_BASE_SPI0
+ AT91_SPI_RPR
);
144 writel((unsigned int)pDesc
->tx_cmd_pt
,
145 ATMEL_BASE_SPI0
+ AT91_SPI_TPR
);
147 /* Intialize the Transmit and Receive Counters */
148 writel(pDesc
->rx_cmd_size
, ATMEL_BASE_SPI0
+ AT91_SPI_RCR
);
149 writel(pDesc
->tx_cmd_size
, ATMEL_BASE_SPI0
+ AT91_SPI_TCR
);
151 if (pDesc
->tx_data_size
!= 0) {
152 /* Initialize the Next Transmit and Next Receive Pointer */
153 writel((unsigned int)pDesc
->rx_data_pt
,
154 ATMEL_BASE_SPI0
+ AT91_SPI_RNPR
);
155 writel((unsigned int)pDesc
->tx_data_pt
,
156 ATMEL_BASE_SPI0
+ AT91_SPI_TNPR
);
158 /* Intialize the Next Transmit and Next Receive Counters */
159 writel(pDesc
->rx_data_size
,
160 ATMEL_BASE_SPI0
+ AT91_SPI_RNCR
);
161 writel(pDesc
->tx_data_size
,
162 ATMEL_BASE_SPI0
+ AT91_SPI_TNCR
);
165 /* arm simple, non interrupt dependent timer */
166 timebase
= get_timer(0);
169 writel(AT91_SPI_TXTEN
+ AT91_SPI_RXTEN
,
170 ATMEL_BASE_SPI0
+ AT91_SPI_PTCR
);
171 while (!(readl(ATMEL_BASE_SPI0
+ AT91_SPI_SR
) & AT91_SPI_RXBUFF
) &&
172 ((timeout
= get_timer(timebase
)) < CONFIG_SYS_SPI_WRITE_TOUT
))
174 writel(AT91_SPI_TXTDIS
+ AT91_SPI_RXTDIS
,
175 ATMEL_BASE_SPI0
+ AT91_SPI_PTCR
);
178 if (timeout
>= CONFIG_SYS_SPI_WRITE_TOUT
) {
179 printf("Error Timeout\n\r");
180 return DATAFLASH_ERROR
;