drivers/spi/atmel_spi.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <fdtdec.h>
  10 #include <spi.h>
  11 #include <malloc.h>
  12 #include <wait_bit.h>
  13
  14 #include <asm/io.h>
  15
  16 #include <asm/arch/clk.h>
  17 #include <asm/arch/hardware.h>
  18 #ifdef CONFIG_DM_SPI
  19 #include <asm/arch/at91_spi.h>
  20 #endif
  21 #ifdef CONFIG_DM_GPIO
  22 #include <asm/gpio.h>
  23 #endif
  24
  25 #include "atmel_spi.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifndef CONFIG_DM_SPI
  30
  31 static int spi_has_wdrbt(struct atmel_spi_slave *slave)
  32 {
  33         unsigned int ver;
  34
  35         ver = spi_readl(slave, VERSION);
  36
  37         return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
  38 }
  39
  40 void spi_init()
  41 {
  42
  43 }
  44
  45 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  46                         unsigned int max_hz, unsigned int mode)
  47 {
  48         struct atmel_spi_slave  *as;
  49         unsigned int            scbr;
  50         u32                     csrx;
  51         void                    *regs;
  52
  53         if (!spi_cs_is_valid(bus, cs))
  54                 return NULL;
  55
  56         switch (bus) {
  57         case 0:
  58                 regs = (void *)ATMEL_BASE_SPI0;
  59                 break;
  60 #ifdef ATMEL_BASE_SPI1
  61         case 1:
  62                 regs = (void *)ATMEL_BASE_SPI1;
  63                 break;
  64 #endif
  65 #ifdef ATMEL_BASE_SPI2
  66         case 2:
  67                 regs = (void *)ATMEL_BASE_SPI2;
  68                 break;
  69 #endif
  70 #ifdef ATMEL_BASE_SPI3
  71         case 3:
  72                 regs = (void *)ATMEL_BASE_SPI3;
  73                 break;
  74 #endif
  75         default:
  76                 return NULL;
  77         }
  78
  79
  80         scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
  81         if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
  82                 /* Too low max SCK rate */
  83                 return NULL;
  84         if (scbr < 1)
  85                 scbr = 1;
  86
  87         csrx = ATMEL_SPI_CSRx_SCBR(scbr);
  88         csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
  89         if (!(mode & SPI_CPHA))
  90                 csrx |= ATMEL_SPI_CSRx_NCPHA;
  91         if (mode & SPI_CPOL)
  92                 csrx |= ATMEL_SPI_CSRx_CPOL;
  93
  94         as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
  95         if (!as)
  96                 return NULL;
  97
  98         as->regs = regs;
  99         as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
 100                         | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
 101         if (spi_has_wdrbt(as))
 102                 as->mr |= ATMEL_SPI_MR_WDRBT;
 103
 104         spi_writel(as, CSR(cs), csrx);
 105
 106         return &as->slave;
 107 }
 108
 109 void spi_free_slave(struct spi_slave *slave)
 110 {
 111         struct atmel_spi_slave *as = to_atmel_spi(slave);
 112
 113         free(as);
 114 }
 115
 116 int spi_claim_bus(struct spi_slave *slave)
 117 {
 118         struct atmel_spi_slave *as = to_atmel_spi(slave);
 119
 120         /* Enable the SPI hardware */
 121         spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
 122
 123         /*
 124          * Select the slave. This should set SCK to the correct
 125          * initial state, etc.
 126          */
 127         spi_writel(as, MR, as->mr);
 128
 129         return 0;
 130 }
 131
 132 void spi_release_bus(struct spi_slave *slave)
 133 {
 134         struct atmel_spi_slave *as = to_atmel_spi(slave);
 135
 136         /* Disable the SPI hardware */
 137         spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
 138 }
 139
 140 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 141                 const void *dout, void *din, unsigned long flags)
 142 {
 143         struct atmel_spi_slave *as = to_atmel_spi(slave);
 144         unsigned int    len_tx;
 145         unsigned int    len_rx;
 146         unsigned int    len;
 147         u32             status;
 148         const u8        *txp = dout;
 149         u8              *rxp = din;
 150         u8              value;
 151
 152         if (bitlen == 0)
 153                 /* Finish any previously submitted transfers */
 154                 goto out;
 155
 156         /*
 157          * TODO: The controller can do non-multiple-of-8 bit
 158          * transfers, but this driver currently doesn't support it.
 159          *
 160          * It's also not clear how such transfers are supposed to be
 161          * represented as a stream of bytes...this is a limitation of
 162          * the current SPI interface.
 163          */
 164         if (bitlen % 8) {
 165                 /* Errors always terminate an ongoing transfer */
 166                 flags |= SPI_XFER_END;
 167                 goto out;
 168         }
 169
 170         len = bitlen / 8;
 171
 172         /*
 173          * The controller can do automatic CS control, but it is
 174          * somewhat quirky, and it doesn't really buy us much anyway
 175          * in the context of U-Boot.
 176          */
 177         if (flags & SPI_XFER_BEGIN) {
 178                 spi_cs_activate(slave);
 179                 /*
 180                  * sometimes the RDR is not empty when we get here,
 181                  * in theory that should not happen, but it DOES happen.
 182                  * Read it here to be on the safe side.
 183                  * That also clears the OVRES flag. Required if the
 184                  * following loop exits due to OVRES!
 185                  */
 186                 spi_readl(as, RDR);
 187         }
 188
 189         for (len_tx = 0, len_rx = 0; len_rx < len; ) {
 190                 status = spi_readl(as, SR);
 191
 192                 if (status & ATMEL_SPI_SR_OVRES)
 193                         return -1;
 194
 195                 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
 196                         if (txp)
 197                                 value = *txp++;
 198                         else
 199                                 value = 0;
 200                         spi_writel(as, TDR, value);
 201                         len_tx++;
 202                 }
 203                 if (status & ATMEL_SPI_SR_RDRF) {
 204                         value = spi_readl(as, RDR);
 205                         if (rxp)
 206                                 *rxp++ = value;
 207                         len_rx++;
 208                 }
 209         }
 210
 211 out:
 212         if (flags & SPI_XFER_END) {
 213                 /*
 214                  * Wait until the transfer is completely done before
 215                  * we deactivate CS.
 216                  */
 217                 do {
 218                         status = spi_readl(as, SR);
 219                 } while (!(status & ATMEL_SPI_SR_TXEMPTY));
 220
 221                 spi_cs_deactivate(slave);
 222         }
 223
 224         return 0;
 225 }
 226
 227 #else
 228
 229 #define MAX_CS_COUNT    4
 230
 231 struct atmel_spi_platdata {
 232         struct at91_spi *regs;
 233 };
 234
 235 struct atmel_spi_priv {
 236         unsigned int freq;              /* Default frequency */
 237         unsigned int mode;
 238         ulong bus_clk_rate;
 239         struct gpio_desc cs_gpios[MAX_CS_COUNT];
 240 };
 241
 242 static int atmel_spi_claim_bus(struct udevice *dev)
 243 {
 244         struct udevice *bus = dev_get_parent(dev);
 245         struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
 246         struct atmel_spi_priv *priv = dev_get_priv(bus);
 247         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 248         struct at91_spi *reg_base = bus_plat->regs;
 249         u32 cs = slave_plat->cs;
 250         u32 freq = priv->freq;
 251         u32 scbr, csrx, mode;
 252
 253         scbr = (priv->bus_clk_rate + freq - 1) / freq;
 254         if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
 255                 return -EINVAL;
 256
 257         if (scbr < 1)
 258                 scbr = 1;
 259
 260         csrx = ATMEL_SPI_CSRx_SCBR(scbr);
 261         csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
 262
 263         if (!(priv->mode & SPI_CPHA))
 264                 csrx |= ATMEL_SPI_CSRx_NCPHA;
 265         if (priv->mode & SPI_CPOL)
 266                 csrx |= ATMEL_SPI_CSRx_CPOL;
 267
 268         writel(csrx, &reg_base->csr[cs]);
 269
 270         mode = ATMEL_SPI_MR_MSTR |
 271                ATMEL_SPI_MR_MODFDIS |
 272                ATMEL_SPI_MR_WDRBT |
 273                ATMEL_SPI_MR_PCS(~(1 << cs));
 274
 275         writel(mode, &reg_base->mr);
 276
 277         writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr);
 278
 279         return 0;
 280 }
 281
 282 static int atmel_spi_release_bus(struct udevice *dev)
 283 {
 284         struct udevice *bus = dev_get_parent(dev);
 285         struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
 286
 287         writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
 288
 289         return 0;
 290 }
 291
 292 static void atmel_spi_cs_activate(struct udevice *dev)
 293 {
 294         struct udevice *bus = dev_get_parent(dev);
 295         struct atmel_spi_priv *priv = dev_get_priv(bus);
 296         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 297         u32 cs = slave_plat->cs;
 298
 299         dm_gpio_set_value(&priv->cs_gpios[cs], 0);
 300 }
 301
 302 static void atmel_spi_cs_deactivate(struct udevice *dev)
 303 {
 304         struct udevice *bus = dev_get_parent(dev);
 305         struct atmel_spi_priv *priv = dev_get_priv(bus);
 306         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 307         u32 cs = slave_plat->cs;
 308
 309         dm_gpio_set_value(&priv->cs_gpios[cs], 1);
 310 }
 311
 312 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
 313                           const void *dout, void *din, unsigned long flags)
 314 {
 315         struct udevice *bus = dev_get_parent(dev);
 316         struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
 317         struct at91_spi *reg_base = bus_plat->regs;
 318
 319         u32 len_tx, len_rx, len;
 320         u32 status;
 321         const u8 *txp = dout;
 322         u8 *rxp = din;
 323         u8 value;
 324
 325         if (bitlen == 0)
 326                 goto out;
 327
 328         /*
 329          * The controller can do non-multiple-of-8 bit
 330          * transfers, but this driver currently doesn't support it.
 331          *
 332          * It's also not clear how such transfers are supposed to be
 333          * represented as a stream of bytes...this is a limitation of
 334          * the current SPI interface.
 335          */
 336         if (bitlen % 8) {
 337                 /* Errors always terminate an ongoing transfer */
 338                 flags |= SPI_XFER_END;
 339                 goto out;
 340         }
 341
 342         len = bitlen / 8;
 343
 344         /*
 345          * The controller can do automatic CS control, but it is
 346          * somewhat quirky, and it doesn't really buy us much anyway
 347          * in the context of U-Boot.
 348          */
 349         if (flags & SPI_XFER_BEGIN) {
 350                 atmel_spi_cs_activate(dev);
 351
 352                 /*
 353                  * sometimes the RDR is not empty when we get here,
 354                  * in theory that should not happen, but it DOES happen.
 355                  * Read it here to be on the safe side.
 356                  * That also clears the OVRES flag. Required if the
 357                  * following loop exits due to OVRES!
 358                  */
 359                 readl(&reg_base->rdr);
 360         }
 361
 362         for (len_tx = 0, len_rx = 0; len_rx < len; ) {
 363                 status = readl(&reg_base->sr);
 364
 365                 if (status & ATMEL_SPI_SR_OVRES)
 366                         return -1;
 367
 368                 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
 369                         if (txp)
 370                                 value = *txp++;
 371                         else
 372                                 value = 0;
 373                         writel(value, &reg_base->tdr);
 374                         len_tx++;
 375                 }
 376
 377                 if (status & ATMEL_SPI_SR_RDRF) {
 378                         value = readl(&reg_base->rdr);
 379                         if (rxp)
 380                                 *rxp++ = value;
 381                         len_rx++;
 382                 }
 383         }
 384
 385 out:
 386         if (flags & SPI_XFER_END) {
 387                 /*
 388                  * Wait until the transfer is completely done before
 389                  * we deactivate CS.
 390                  */
 391                 wait_for_bit(__func__, &reg_base->sr,
 392                              ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
 393
 394                 atmel_spi_cs_deactivate(dev);
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
 401 {
 402         struct atmel_spi_priv *priv = dev_get_priv(bus);
 403
 404         priv->freq = speed;
 405
 406         return 0;
 407 }
 408
 409 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
 410 {
 411         struct atmel_spi_priv *priv = dev_get_priv(bus);
 412
 413         priv->mode = mode;
 414
 415         return 0;
 416 }
 417
 418 static const struct dm_spi_ops atmel_spi_ops = {
 419         .claim_bus      = atmel_spi_claim_bus,
 420         .release_bus    = atmel_spi_release_bus,
 421         .xfer           = atmel_spi_xfer,
 422         .set_speed      = atmel_spi_set_speed,
 423         .set_mode       = atmel_spi_set_mode,
 424         /*
 425          * cs_info is not needed, since we require all chip selects to be
 426          * in the device tree explicitly
 427          */
 428 };
 429
 430 static int atmel_spi_enable_clk(struct udevice *bus)
 431 {
 432         struct atmel_spi_priv *priv = dev_get_priv(bus);
 433         struct clk clk;
 434         ulong clk_rate;
 435         int ret;
 436
 437         ret = clk_get_by_index(bus, 0, &clk);
 438         if (ret)
 439                 return -EINVAL;
 440
 441         ret = clk_enable(&clk);
 442         if (ret)
 443                 return ret;
 444
 445         clk_rate = clk_get_rate(&clk);
 446         if (!clk_rate)
 447                 return -EINVAL;
 448
 449         priv->bus_clk_rate = clk_rate;
 450
 451         clk_free(&clk);
 452
 453         return 0;
 454 }
 455
 456 static int atmel_spi_probe(struct udevice *bus)
 457 {
 458         struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
 459         struct atmel_spi_priv *priv = dev_get_priv(bus);
 460         int i, ret;
 461
 462         ret = atmel_spi_enable_clk(bus);
 463         if (ret)
 464                 return ret;
 465
 466         bus_plat->regs = (struct at91_spi *)dev_get_addr(bus);
 467
 468         ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
 469                                         ARRAY_SIZE(priv->cs_gpios), 0);
 470         if (ret < 0) {
 471                 error("Can't get %s gpios! Error: %d", bus->name, ret);
 472                 return ret;
 473         }
 474
 475         for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
 476                 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
 477                                       GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 478         }
 479
 480         writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
 481
 482         return 0;
 483 }
 484
 485 static const struct udevice_id atmel_spi_ids[] = {
 486         { .compatible = "atmel,at91rm9200-spi" },
 487         { }
 488 };
 489
 490 U_BOOT_DRIVER(atmel_spi) = {
 491         .name   = "atmel_spi",
 492         .id     = UCLASS_SPI,
 493         .of_match = atmel_spi_ids,
 494         .ops    = &atmel_spi_ops,
 495         .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
 496         .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
 497         .probe  = atmel_spi_probe,
 498 };
 499 #endif