drivers/spi/bcm63xx_hsspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
   6  *      Copyright (C) 2000-2010 Broadcom Corporation
   7  *      Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <dm.h>
  13 #include <malloc.h>
  14 #include <spi.h>
  15 #include <reset.h>
  16 #include <wait_bit.h>
  17 #include <asm/io.h>
  18
  19 #define HSSPI_PP                        0
  20
  21 #define SPI_MAX_SYNC_CLOCK              30000000
  22
  23 /* SPI Control register */
  24 #define SPI_CTL_REG                     0x000
  25 #define SPI_CTL_CS_POL_SHIFT            0
  26 #define SPI_CTL_CS_POL_MASK             (0xff << SPI_CTL_CS_POL_SHIFT)
  27 #define SPI_CTL_CLK_GATE_SHIFT          16
  28 #define SPI_CTL_CLK_GATE_MASK           (1 << SPI_CTL_CLK_GATE_SHIFT)
  29 #define SPI_CTL_CLK_POL_SHIFT           17
  30 #define SPI_CTL_CLK_POL_MASK            (1 << SPI_CTL_CLK_POL_SHIFT)
  31
  32 /* SPI Interrupts registers */
  33 #define SPI_IR_STAT_REG                 0x008
  34 #define SPI_IR_ST_MASK_REG              0x00c
  35 #define SPI_IR_MASK_REG                 0x010
  36
  37 #define SPI_IR_CLEAR_ALL                0xff001f1f
  38
  39 /* SPI Ping-Pong Command registers */
  40 #define SPI_CMD_REG                     (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
  41 #define SPI_CMD_OP_SHIFT                0
  42 #define SPI_CMD_OP_START                (0x1 << SPI_CMD_OP_SHIFT)
  43 #define SPI_CMD_PFL_SHIFT               8
  44 #define SPI_CMD_PFL_MASK                (0x7 << SPI_CMD_PFL_SHIFT)
  45 #define SPI_CMD_SLAVE_SHIFT             12
  46 #define SPI_CMD_SLAVE_MASK              (0x7 << SPI_CMD_SLAVE_SHIFT)
  47
  48 /* SPI Ping-Pong Status registers */
  49 #define SPI_STAT_REG                    (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
  50 #define SPI_STAT_SRCBUSY_SHIFT          1
  51 #define SPI_STAT_SRCBUSY_MASK           (1 << SPI_STAT_SRCBUSY_SHIFT)
  52
  53 /* SPI Profile Clock registers */
  54 #define SPI_PFL_CLK_REG(x)              (0x100 + (0x20 * (x)) + 0x00)
  55 #define SPI_PFL_CLK_FREQ_SHIFT          0
  56 #define SPI_PFL_CLK_FREQ_MASK           (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
  57 #define SPI_PFL_CLK_RSTLOOP_SHIFT       15
  58 #define SPI_PFL_CLK_RSTLOOP_MASK        (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
  59
  60 /* SPI Profile Signal registers */
  61 #define SPI_PFL_SIG_REG(x)              (0x100 + (0x20 * (x)) + 0x04)
  62 #define SPI_PFL_SIG_LATCHRIS_SHIFT      12
  63 #define SPI_PFL_SIG_LATCHRIS_MASK       (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
  64 #define SPI_PFL_SIG_LAUNCHRIS_SHIFT     13
  65 #define SPI_PFL_SIG_LAUNCHRIS_MASK      (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
  66 #define SPI_PFL_SIG_ASYNCIN_SHIFT       16
  67 #define SPI_PFL_SIG_ASYNCIN_MASK        (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
  68
  69 /* SPI Profile Mode registers */
  70 #define SPI_PFL_MODE_REG(x)             (0x100 + (0x20 * (x)) + 0x08)
  71 #define SPI_PFL_MODE_FILL_SHIFT         0
  72 #define SPI_PFL_MODE_FILL_MASK          (0xff << SPI_PFL_MODE_FILL_SHIFT)
  73 #define SPI_PFL_MODE_MDRDSZ_SHIFT       16
  74 #define SPI_PFL_MODE_MDRDSZ_MASK        (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
  75 #define SPI_PFL_MODE_MDWRSZ_SHIFT       18
  76 #define SPI_PFL_MODE_MDWRSZ_MASK        (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
  77 #define SPI_PFL_MODE_3WIRE_SHIFT        20
  78 #define SPI_PFL_MODE_3WIRE_MASK         (1 << SPI_PFL_MODE_3WIRE_SHIFT)
  79
  80 /* SPI Ping-Pong FIFO registers */
  81 #define HSSPI_FIFO_SIZE                 0x200
  82 #define HSSPI_FIFO_BASE                 (0x200 + \
  83                                          (HSSPI_FIFO_SIZE * HSSPI_PP))
  84
  85 /* SPI Ping-Pong FIFO OP register */
  86 #define HSSPI_FIFO_OP_SIZE              0x2
  87 #define HSSPI_FIFO_OP_REG               (HSSPI_FIFO_BASE + 0x00)
  88 #define HSSPI_FIFO_OP_BYTES_SHIFT       0
  89 #define HSSPI_FIFO_OP_BYTES_MASK        (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
  90 #define HSSPI_FIFO_OP_MBIT_SHIFT        11
  91 #define HSSPI_FIFO_OP_MBIT_MASK         (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
  92 #define HSSPI_FIFO_OP_CODE_SHIFT        13
  93 #define HSSPI_FIFO_OP_READ_WRITE        (1 << HSSPI_FIFO_OP_CODE_SHIFT)
  94 #define HSSPI_FIFO_OP_CODE_W            (2 << HSSPI_FIFO_OP_CODE_SHIFT)
  95 #define HSSPI_FIFO_OP_CODE_R            (3 << HSSPI_FIFO_OP_CODE_SHIFT)
  96
  97 struct bcm63xx_hsspi_priv {
  98         void __iomem *regs;
  99         ulong clk_rate;
 100         uint8_t num_cs;
 101         uint8_t cs_pols;
 102         uint speed;
 103 };
 104
 105 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
 106                            struct spi_cs_info *info)
 107 {
 108         struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
 109
 110         if (cs >= priv->num_cs) {
 111                 printf("no cs %u\n", cs);
 112                 return -EINVAL;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
 119 {
 120         struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
 121
 122         /* clock polarity */
 123         if (mode & SPI_CPOL)
 124                 setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
 125         else
 126                 clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
 127
 128         return 0;
 129 }
 130
 131 static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
 132 {
 133         struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
 134
 135         priv->speed = speed;
 136
 137         return 0;
 138 }
 139
 140 static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
 141                                    struct dm_spi_slave_platdata *plat)
 142 {
 143         uint32_t clr, set;
 144
 145         /* profile clock */
 146         set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
 147         set = DIV_ROUND_UP(2048, set);
 148         set &= SPI_PFL_CLK_FREQ_MASK;
 149         set |= SPI_PFL_CLK_RSTLOOP_MASK;
 150         writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
 151
 152         /* profile signal */
 153         set = 0;
 154         clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
 155               SPI_PFL_SIG_LATCHRIS_MASK |
 156               SPI_PFL_SIG_ASYNCIN_MASK;
 157
 158         /* latch/launch config */
 159         if (plat->mode & SPI_CPHA)
 160                 set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
 161         else
 162                 set |= SPI_PFL_SIG_LATCHRIS_MASK;
 163
 164         /* async clk */
 165         if (priv->speed > SPI_MAX_SYNC_CLOCK)
 166                 set |= SPI_PFL_SIG_ASYNCIN_MASK;
 167
 168         clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
 169
 170         /* global control */
 171         set = 0;
 172         clr = 0;
 173
 174         /* invert cs polarity */
 175         if (priv->cs_pols & BIT(plat->cs))
 176                 clr |= BIT(plat->cs);
 177         else
 178                 set |= BIT(plat->cs);
 179
 180         /* invert dummy cs polarity */
 181         if (priv->cs_pols & BIT(!plat->cs))
 182                 clr |= BIT(!plat->cs);
 183         else
 184                 set |= BIT(!plat->cs);
 185
 186         clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
 187 }
 188
 189 static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
 190 {
 191         /* restore cs polarities */
 192         clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
 193                         priv->cs_pols);
 194 }
 195
 196 /*
 197  * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
 198  * because they are controlled by HW.
 199  * However, it provides a mechanism to prepend write transfers prior to read
 200  * transfers (with a maximum prepend of 15 bytes), which is usually enough for
 201  * SPI-connected flashes since reading requires prepending a write transfer of
 202  * 5 bytes. On the other hand it also provides a way to invert each CS
 203  * polarity, not only between transfers like the older BCM63xx SPI driver, but
 204  * also the rest of the time.
 205  *
 206  * Instead of using the prepend mechanism, this implementation inverts the
 207  * polarity of both the desired CS and another dummy CS when the bus is
 208  * claimed. This way, the dummy CS is restored to its inactive value when
 209  * transfers are issued and the desired CS is preserved in its active value
 210  * all the time. This hack is also used in the upstream linux driver and
 211  * allows keeping CS active between trasnfers even if the HW doesn't give
 212  * this possibility.
 213  */
 214 static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 215                 const void *dout, void *din, unsigned long flags)
 216 {
 217         struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
 218         struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
 219         size_t data_bytes = bitlen / 8;
 220         size_t step_size = HSSPI_FIFO_SIZE;
 221         uint16_t opcode = 0;
 222         uint32_t val;
 223         const uint8_t *tx = dout;
 224         uint8_t *rx = din;
 225
 226         if (flags & SPI_XFER_BEGIN)
 227                 bcm63xx_hsspi_activate_cs(priv, plat);
 228
 229         /* fifo operation */
 230         if (tx && rx)
 231                 opcode = HSSPI_FIFO_OP_READ_WRITE;
 232         else if (rx)
 233                 opcode = HSSPI_FIFO_OP_CODE_R;
 234         else if (tx)
 235                 opcode = HSSPI_FIFO_OP_CODE_W;
 236
 237         if (opcode != HSSPI_FIFO_OP_CODE_R)
 238                 step_size -= HSSPI_FIFO_OP_SIZE;
 239
 240         /* dual mode */
 241         if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
 242             (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
 243                 opcode |= HSSPI_FIFO_OP_MBIT_MASK;
 244
 245         /* profile mode */
 246         val = SPI_PFL_MODE_FILL_MASK |
 247               SPI_PFL_MODE_MDRDSZ_MASK |
 248               SPI_PFL_MODE_MDWRSZ_MASK;
 249         if (plat->mode & SPI_3WIRE)
 250                 val |= SPI_PFL_MODE_3WIRE_MASK;
 251         writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
 252
 253         /* transfer loop */
 254         while (data_bytes > 0) {
 255                 size_t curr_step = min(step_size, data_bytes);
 256                 int ret;
 257
 258                 /* copy tx data */
 259                 if (tx) {
 260                         memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
 261                                     HSSPI_FIFO_OP_SIZE, tx, curr_step);
 262                         tx += curr_step;
 263                 }
 264
 265                 /* set fifo operation */
 266                 writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
 267                           priv->regs + HSSPI_FIFO_OP_REG);
 268
 269                 /* issue the transfer */
 270                 val = SPI_CMD_OP_START;
 271                 val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
 272                        SPI_CMD_PFL_MASK;
 273                 val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
 274                        SPI_CMD_SLAVE_MASK;
 275                 writel(val, priv->regs + SPI_CMD_REG);
 276
 277                 /* wait for completion */
 278                 ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
 279                                         SPI_STAT_SRCBUSY_MASK, false,
 280                                         1000, false);
 281                 if (ret) {
 282                         printf("interrupt timeout\n");
 283                         return ret;
 284                 }
 285
 286                 /* copy rx data */
 287                 if (rx) {
 288                         memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
 289                                       curr_step);
 290                         rx += curr_step;
 291                 }
 292
 293                 data_bytes -= curr_step;
 294         }
 295
 296         if (flags & SPI_XFER_END)
 297                 bcm63xx_hsspi_deactivate_cs(priv);
 298
 299         return 0;
 300 }
 301
 302 static const struct dm_spi_ops bcm63xx_hsspi_ops = {
 303         .cs_info = bcm63xx_hsspi_cs_info,
 304         .set_mode = bcm63xx_hsspi_set_mode,
 305         .set_speed = bcm63xx_hsspi_set_speed,
 306         .xfer = bcm63xx_hsspi_xfer,
 307 };
 308
 309 static const struct udevice_id bcm63xx_hsspi_ids[] = {
 310         { .compatible = "brcm,bcm6328-hsspi", },
 311         { /* sentinel */ }
 312 };
 313
 314 static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
 315 {
 316         struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
 317         struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
 318
 319         /* check cs */
 320         if (plat->cs >= priv->num_cs) {
 321                 printf("no cs %u\n", plat->cs);
 322                 return -ENODEV;
 323         }
 324
 325         /* cs polarity */
 326         if (plat->mode & SPI_CS_HIGH)
 327                 priv->cs_pols |= BIT(plat->cs);
 328         else
 329                 priv->cs_pols &= ~BIT(plat->cs);
 330
 331         return 0;
 332 }
 333
 334 static int bcm63xx_hsspi_probe(struct udevice *dev)
 335 {
 336         struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
 337         struct reset_ctl rst_ctl;
 338         struct clk clk;
 339         int ret;
 340
 341         priv->regs = dev_remap_addr(dev);
 342         if (!priv->regs)
 343                 return -EINVAL;
 344
 345         priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
 346
 347         /* enable clock */
 348         ret = clk_get_by_name(dev, "hsspi", &clk);
 349         if (ret < 0)
 350                 return ret;
 351
 352         ret = clk_enable(&clk);
 353         if (ret < 0 && ret != -ENOSYS)
 354                 return ret;
 355
 356         ret = clk_free(&clk);
 357         if (ret < 0 && ret != -ENOSYS)
 358                 return ret;
 359
 360         /* get clock rate */
 361         ret = clk_get_by_name(dev, "pll", &clk);
 362         if (ret < 0 && ret != -ENOSYS)
 363                 return ret;
 364
 365         priv->clk_rate = clk_get_rate(&clk);
 366
 367         ret = clk_free(&clk);
 368         if (ret < 0 && ret != -ENOSYS)
 369                 return ret;
 370
 371         /* perform reset */
 372         ret = reset_get_by_index(dev, 0, &rst_ctl);
 373         if (ret >= 0) {
 374                 ret = reset_deassert(&rst_ctl);
 375                 if (ret < 0)
 376                         return ret;
 377         }
 378
 379         ret = reset_free(&rst_ctl);
 380         if (ret < 0)
 381                 return ret;
 382
 383         /* initialize hardware */
 384         writel(0, priv->regs + SPI_IR_MASK_REG);
 385
 386         /* clear pending interrupts */
 387         writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
 388
 389         /* enable clk gate */
 390         setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
 391
 392         /* read default cs polarities */
 393         priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
 394                         SPI_CTL_CS_POL_MASK;
 395
 396         return 0;
 397 }
 398
 399 U_BOOT_DRIVER(bcm63xx_hsspi) = {
 400         .name = "bcm63xx_hsspi",
 401         .id = UCLASS_SPI,
 402         .of_match = bcm63xx_hsspi_ids,
 403         .ops = &bcm63xx_hsspi_ops,
 404         .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
 405         .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
 406         .probe = bcm63xx_hsspi_probe,
 407 };