drivers/spi/bfin_spi.c

   1 /*
   2  * Driver for Blackfin On-Chip SPI device
   3  *
   4  * Copyright (c) 2005-2010 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 /*#define DEBUG*/
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14
  15 #include <asm/blackfin.h>
  16 #include <asm/gpio.h>
  17 #include <asm/portmux.h>
  18 #include <asm/mach-common/bits/spi.h>
  19
  20 struct bfin_spi_slave {
  21         struct spi_slave slave;
  22         void *mmr_base;
  23         u16 ctl, baud, flg;
  24 };
  25
  26 #define MAKE_SPI_FUNC(mmr, off) \
  27 static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
  28 static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
  29 MAKE_SPI_FUNC(SPI_CTL,  0x00)
  30 MAKE_SPI_FUNC(SPI_FLG,  0x04)
  31 MAKE_SPI_FUNC(SPI_STAT, 0x08)
  32 MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
  33 MAKE_SPI_FUNC(SPI_RDBR, 0x10)
  34 MAKE_SPI_FUNC(SPI_BAUD, 0x14)
  35
  36 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
  37
  38 #define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
  39 #ifdef CONFIG_BFIN_SPI_GPIO_CS
  40 # define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
  41 #else
  42 # define is_gpio_cs(cs) 0
  43 #endif
  44
  45 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  46 {
  47         if (is_gpio_cs(cs))
  48                 return gpio_is_valid(gpio_cs(cs));
  49         else
  50                 return (cs >= 1 && cs <= MAX_CTRL_CS);
  51 }
  52
  53 void spi_cs_activate(struct spi_slave *slave)
  54 {
  55         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
  56
  57         if (is_gpio_cs(slave->cs)) {
  58                 unsigned int cs = gpio_cs(slave->cs);
  59                 gpio_set_value(cs, bss->flg);
  60                 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
  61         } else {
  62                 write_SPI_FLG(bss,
  63                         (read_SPI_FLG(bss) &
  64                         ~((!bss->flg << 8) << slave->cs)) |
  65                         (1 << slave->cs));
  66                 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
  67         }
  68
  69         SSYNC();
  70 }
  71
  72 void spi_cs_deactivate(struct spi_slave *slave)
  73 {
  74         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
  75
  76         if (is_gpio_cs(slave->cs)) {
  77                 unsigned int cs = gpio_cs(slave->cs);
  78                 gpio_set_value(cs, !bss->flg);
  79                 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
  80         } else {
  81                 u16 flg;
  82
  83                 /* make sure we force the cs to deassert rather than let the
  84                  * pin float back up.  otherwise, exact timings may not be
  85                  * met some of the time leading to random behavior (ugh).
  86                  */
  87                 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
  88                 write_SPI_FLG(bss, flg);
  89                 SSYNC();
  90                 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
  91
  92                 flg &= ~(1 << slave->cs);
  93                 write_SPI_FLG(bss, flg);
  94                 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
  95         }
  96
  97         SSYNC();
  98 }
  99
 100 void spi_init()
 101 {
 102 }
 103
 104 #ifdef SPI_CTL
 105 # define SPI0_CTL SPI_CTL
 106 #endif
 107
 108 #define SPI_PINS(n) \
 109         [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
 110 static unsigned short pins[][5] = {
 111 #ifdef SPI0_CTL
 112         SPI_PINS(0),
 113 #endif
 114 #ifdef SPI1_CTL
 115         SPI_PINS(1),
 116 #endif
 117 #ifdef SPI2_CTL
 118         SPI_PINS(2),
 119 #endif
 120 };
 121
 122 #define SPI_CS_PINS(n) \
 123         [n] = { \
 124                 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
 125                 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
 126                 P_SPI##n##_SSEL7, \
 127         }
 128 static const unsigned short cs_pins[][7] = {
 129 #ifdef SPI0_CTL
 130         SPI_CS_PINS(0),
 131 #endif
 132 #ifdef SPI1_CTL
 133         SPI_CS_PINS(1),
 134 #endif
 135 #ifdef SPI2_CTL
 136         SPI_CS_PINS(2),
 137 #endif
 138 };
 139
 140 void spi_set_speed(struct spi_slave *slave, uint hz)
 141 {
 142         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 143         ulong sclk;
 144         u32 baud;
 145
 146         sclk = get_sclk();
 147         /* baud should be rounded up */
 148         baud = DIV_ROUND_UP(sclk, 2 * hz);
 149         if (baud < 2)
 150                 baud = 2;
 151         else if (baud > (u16)-1)
 152                 baud = -1;
 153         bss->baud = baud;
 154 }
 155
 156 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 157                 unsigned int max_hz, unsigned int mode)
 158 {
 159         struct bfin_spi_slave *bss;
 160         u32 mmr_base;
 161
 162         if (!spi_cs_is_valid(bus, cs))
 163                 return NULL;
 164
 165         if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
 166                 debug("%s: invalid bus %u\n", __func__, bus);
 167                 return NULL;
 168         }
 169         switch (bus) {
 170 #ifdef SPI0_CTL
 171                 case 0: mmr_base = SPI0_CTL; break;
 172 #endif
 173 #ifdef SPI1_CTL
 174                 case 1: mmr_base = SPI1_CTL; break;
 175 #endif
 176 #ifdef SPI2_CTL
 177                 case 2: mmr_base = SPI2_CTL; break;
 178 #endif
 179                 default: return NULL;
 180         }
 181
 182         bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
 183         if (!bss)
 184                 return NULL;
 185
 186         bss->mmr_base = (void *)mmr_base;
 187         bss->ctl = SPE | MSTR | TDBR_CORE;
 188         if (mode & SPI_CPHA) bss->ctl |= CPHA;
 189         if (mode & SPI_CPOL) bss->ctl |= CPOL;
 190         if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
 191         bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
 192         spi_set_speed(&bss->slave, max_hz);
 193
 194         debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
 195                 bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
 196
 197         return &bss->slave;
 198 }
 199
 200 void spi_free_slave(struct spi_slave *slave)
 201 {
 202         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 203         free(bss);
 204 }
 205
 206 int spi_claim_bus(struct spi_slave *slave)
 207 {
 208         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 209
 210         debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 211
 212         if (is_gpio_cs(slave->cs)) {
 213                 unsigned int cs = gpio_cs(slave->cs);
 214                 gpio_request(cs, "bfin-spi");
 215                 gpio_direction_output(cs, !bss->flg);
 216                 pins[slave->bus][0] = P_DONTCARE;
 217         } else
 218                 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
 219         peripheral_request_list(pins[slave->bus], "bfin-spi");
 220
 221         write_SPI_CTL(bss, bss->ctl);
 222         write_SPI_BAUD(bss, bss->baud);
 223         SSYNC();
 224
 225         return 0;
 226 }
 227
 228 void spi_release_bus(struct spi_slave *slave)
 229 {
 230         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 231
 232         debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 233
 234         peripheral_free_list(pins[slave->bus]);
 235         if (is_gpio_cs(slave->cs))
 236                 gpio_free(gpio_cs(slave->cs));
 237
 238         write_SPI_CTL(bss, 0);
 239         SSYNC();
 240 }
 241
 242 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
 243 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
 244 #endif
 245
 246 static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
 247                         uint bytes)
 248 {
 249         /* discard invalid data and clear RXS */
 250         read_SPI_RDBR(bss);
 251         /* todo: take advantage of hardware fifos  */
 252         while (bytes--) {
 253                 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
 254                 debug("%s: tx:%x ", __func__, value);
 255                 write_SPI_TDBR(bss, value);
 256                 SSYNC();
 257                 while ((read_SPI_STAT(bss) & TXS))
 258                         if (ctrlc())
 259                                 return -1;
 260                 while (!(read_SPI_STAT(bss) & SPIF))
 261                         if (ctrlc())
 262                                 return -1;
 263                 while (!(read_SPI_STAT(bss) & RXS))
 264                         if (ctrlc())
 265                                 return -1;
 266                 value = read_SPI_RDBR(bss);
 267                 if (rx)
 268                         *rx++ = value;
 269                 debug("rx:%x\n", value);
 270         }
 271
 272         return 0;
 273 }
 274
 275 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 276                 void *din, unsigned long flags)
 277 {
 278         struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 279         const u8 *tx = dout;
 280         u8 *rx = din;
 281         uint bytes = bitlen / 8;
 282         int ret = 0;
 283
 284         debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
 285                 slave->bus, slave->cs, bitlen, bytes, flags);
 286
 287         if (bitlen == 0)
 288                 goto done;
 289
 290         /* we can only do 8 bit transfers */
 291         if (bitlen % 8) {
 292                 flags |= SPI_XFER_END;
 293                 goto done;
 294         }
 295
 296         if (flags & SPI_XFER_BEGIN)
 297                 spi_cs_activate(slave);
 298
 299         ret = spi_pio_xfer(bss, tx, rx, bytes);
 300
 301  done:
 302         if (flags & SPI_XFER_END)
 303                 spi_cs_deactivate(slave);
 304
 305         return ret;
 306 }