drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <log.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <malloc.h>
  13 #include <reset.h>
  14 #include <spi.h>
  15 #include <spi-mem.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/err.h>
  18 #include <linux/errno.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21 #include <linux/time.h>
  22 #include <zynqmp_firmware.h>
  23 #include "cadence_qspi.h"
  24 #include <dt-bindings/power/xlnx-versal-power.h>
  25
  26 #define CQSPI_STIG_READ                 0
  27 #define CQSPI_STIG_WRITE                1
  28 #define CQSPI_READ                      2
  29 #define CQSPI_WRITE                     3
  30
  31 __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
  32                                      const struct spi_mem_op *op)
  33 {
  34         return 0;
  35 }
  36
  37 __weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
  38 {
  39         return 0;
  40 }
  41
  42 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  43 {
  44         struct cadence_spi_priv *priv = dev_get_priv(bus);
  45
  46         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  47                                              priv->ref_clk_hz, hz);
  48
  49         /* Reconfigure delay timing if speed is changed. */
  50         cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz,
  51                                priv->tshsl_ns, priv->tsd2d_ns,
  52                                priv->tchsh_ns, priv->tslch_ns);
  53
  54         return 0;
  55 }
  56
  57 static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len,
  58                                u8 *idcode)
  59 {
  60         int err;
  61
  62         struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
  63                                           SPI_MEM_OP_NO_ADDR,
  64                                           SPI_MEM_OP_NO_DUMMY,
  65                                           SPI_MEM_OP_DATA_IN(len, idcode, 1));
  66
  67         err = cadence_qspi_apb_command_read_setup(priv, &op);
  68         if (!err)
  69                 err = cadence_qspi_apb_command_read(priv, &op);
  70
  71         return err;
  72 }
  73
  74 /* Calibration sequence to determine the read data capture delay register */
  75 static int spi_calibration(struct udevice *bus, uint hz)
  76 {
  77         struct cadence_spi_priv *priv = dev_get_priv(bus);
  78         void *base = priv->regbase;
  79         unsigned int idcode = 0, temp = 0;
  80         int err = 0, i, range_lo = -1, range_hi = -1;
  81
  82         /* start with slowest clock (1 MHz) */
  83         cadence_spi_write_speed(bus, 1000000);
  84
  85         /* configure the read data capture delay register to 0 */
  86         cadence_qspi_apb_readdata_capture(base, 1, 0);
  87
  88         /* Enable QSPI */
  89         cadence_qspi_apb_controller_enable(base);
  90
  91         /* read the ID which will be our golden value */
  92         err = cadence_spi_read_id(priv, 3, (u8 *)&idcode);
  93         if (err) {
  94                 puts("SF: Calibration failed (read)\n");
  95                 return err;
  96         }
  97
  98         /* use back the intended clock and find low range */
  99         cadence_spi_write_speed(bus, hz);
 100         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
 101                 /* Disable QSPI */
 102                 cadence_qspi_apb_controller_disable(base);
 103
 104                 /* reconfigure the read data capture delay register */
 105                 cadence_qspi_apb_readdata_capture(base, 1, i);
 106
 107                 /* Enable back QSPI */
 108                 cadence_qspi_apb_controller_enable(base);
 109
 110                 /* issue a RDID to get the ID value */
 111                 err = cadence_spi_read_id(priv, 3, (u8 *)&temp);
 112                 if (err) {
 113                         puts("SF: Calibration failed (read)\n");
 114                         return err;
 115                 }
 116
 117                 /* search for range lo */
 118                 if (range_lo == -1 && temp == idcode) {
 119                         range_lo = i;
 120                         continue;
 121                 }
 122
 123                 /* search for range hi */
 124                 if (range_lo != -1 && temp != idcode) {
 125                         range_hi = i - 1;
 126                         break;
 127                 }
 128                 range_hi = i;
 129         }
 130
 131         if (range_lo == -1) {
 132                 puts("SF: Calibration failed (low range)\n");
 133                 return err;
 134         }
 135
 136         /* Disable QSPI for subsequent initialization */
 137         cadence_qspi_apb_controller_disable(base);
 138
 139         /* configure the final value for read data capture delay register */
 140         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 141         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 142               (range_hi + range_lo) / 2, range_lo, range_hi);
 143
 144         /* just to ensure we do once only when speed or chip select change */
 145         priv->qspi_calibrated_hz = hz;
 146         priv->qspi_calibrated_cs = spi_chip_select(bus);
 147
 148         return 0;
 149 }
 150
 151 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 152 {
 153         struct cadence_spi_priv *priv = dev_get_priv(bus);
 154         int err;
 155
 156         if (!hz || hz > priv->max_hz)
 157                 hz = priv->max_hz;
 158         /* Disable QSPI */
 159         cadence_qspi_apb_controller_disable(priv->regbase);
 160
 161         /*
 162          * If the device tree already provides a read delay value, use that
 163          * instead of calibrating.
 164          */
 165         if (priv->read_delay >= 0) {
 166                 cadence_spi_write_speed(bus, hz);
 167                 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
 168                                                   priv->read_delay);
 169         } else if (priv->previous_hz != hz ||
 170                    priv->qspi_calibrated_hz != hz ||
 171                    priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 172                 /*
 173                  * Calibration required for different current SCLK speed,
 174                  * requested SCLK speed or chip select
 175                  */
 176                 err = spi_calibration(bus, hz);
 177                 if (err)
 178                         return err;
 179
 180                 /* prevent calibration run when same as previous request */
 181                 priv->previous_hz = hz;
 182         }
 183
 184         /* Enable QSPI */
 185         cadence_qspi_apb_controller_enable(priv->regbase);
 186
 187         debug("%s: speed=%d\n", __func__, hz);
 188
 189         return 0;
 190 }
 191
 192 static int cadence_spi_probe(struct udevice *bus)
 193 {
 194         struct cadence_spi_plat *plat = dev_get_plat(bus);
 195         struct cadence_spi_priv *priv = dev_get_priv(bus);
 196         struct clk clk;
 197         int ret;
 198
 199         priv->regbase           = plat->regbase;
 200         priv->ahbbase           = plat->ahbbase;
 201         priv->is_dma            = plat->is_dma;
 202         priv->is_decoded_cs     = plat->is_decoded_cs;
 203         priv->fifo_depth        = plat->fifo_depth;
 204         priv->fifo_width        = plat->fifo_width;
 205         priv->trigger_address   = plat->trigger_address;
 206         priv->read_delay        = plat->read_delay;
 207         priv->ahbsize           = plat->ahbsize;
 208         priv->max_hz            = plat->max_hz;
 209
 210         priv->page_size         = plat->page_size;
 211         priv->block_size        = plat->block_size;
 212         priv->tshsl_ns          = plat->tshsl_ns;
 213         priv->tsd2d_ns          = plat->tsd2d_ns;
 214         priv->tchsh_ns          = plat->tchsh_ns;
 215         priv->tslch_ns          = plat->tslch_ns;
 216
 217         if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
 218                 xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
 219                                   ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
 220                                   ZYNQMP_PM_REQUEST_ACK_NO, NULL);
 221
 222         if (priv->ref_clk_hz == 0) {
 223                 ret = clk_get_by_index(bus, 0, &clk);
 224                 if (ret) {
 225 #ifdef CONFIG_HAS_CQSPI_REF_CLK
 226                         priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
 227 #elif defined(CONFIG_ARCH_SOCFPGA)
 228                         priv->ref_clk_hz = cm_get_qspi_controller_clk_hz();
 229 #else
 230                         return ret;
 231 #endif
 232                 } else {
 233                         priv->ref_clk_hz = clk_get_rate(&clk);
 234                         clk_free(&clk);
 235                         if (IS_ERR_VALUE(priv->ref_clk_hz))
 236                                 return priv->ref_clk_hz;
 237                 }
 238         }
 239
 240         priv->resets = devm_reset_bulk_get_optional(bus);
 241         if (priv->resets)
 242                 reset_deassert_bulk(priv->resets);
 243
 244         if (!priv->qspi_is_init) {
 245                 cadence_qspi_apb_controller_init(priv);
 246                 priv->qspi_is_init = 1;
 247         }
 248
 249         priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
 250
 251         /* Versal and Versal-NET use spi calibration to set read delay */
 252         if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
 253             CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
 254                 if (priv->read_delay >= 0)
 255                         priv->read_delay = -1;
 256
 257         /* Reset ospi flash device */
 258         return cadence_qspi_versal_flash_reset(bus);
 259 }
 260
 261 static int cadence_spi_remove(struct udevice *dev)
 262 {
 263         struct cadence_spi_priv *priv = dev_get_priv(dev);
 264         int ret = 0;
 265
 266         if (priv->resets)
 267                 ret = reset_release_bulk(priv->resets);
 268
 269         return ret;
 270 }
 271
 272 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 273 {
 274         struct cadence_spi_priv *priv = dev_get_priv(bus);
 275
 276         /* Disable QSPI */
 277         cadence_qspi_apb_controller_disable(priv->regbase);
 278
 279         /* Set SPI mode */
 280         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 281
 282         /* Enable Direct Access Controller */
 283         if (priv->use_dac_mode)
 284                 cadence_qspi_apb_dac_mode_enable(priv->regbase);
 285
 286         /* Enable QSPI */
 287         cadence_qspi_apb_controller_enable(priv->regbase);
 288
 289         return 0;
 290 }
 291
 292 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
 293                                    const struct spi_mem_op *op)
 294 {
 295         struct udevice *bus = spi->dev->parent;
 296         struct cadence_spi_priv *priv = dev_get_priv(bus);
 297         void *base = priv->regbase;
 298         int err = 0;
 299         u32 mode;
 300
 301         /* Set Chip select */
 302         cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
 303                                     priv->is_decoded_cs);
 304
 305         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
 306                 /*
 307                  * Performing reads in DAC mode forces to read minimum 4 bytes
 308                  * which is unsupported on some flash devices during register
 309                  * reads, prefer STIG mode for such small reads.
 310                  */
 311                 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 312                         mode = CQSPI_STIG_READ;
 313                 else
 314                         mode = CQSPI_READ;
 315         } else {
 316                 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 317                         mode = CQSPI_STIG_WRITE;
 318                 else
 319                         mode = CQSPI_WRITE;
 320         }
 321
 322         switch (mode) {
 323         case CQSPI_STIG_READ:
 324                 err = cadence_qspi_apb_command_read_setup(priv, op);
 325                 if (!err)
 326                         err = cadence_qspi_apb_command_read(priv, op);
 327                 break;
 328         case CQSPI_STIG_WRITE:
 329                 err = cadence_qspi_apb_command_write_setup(priv, op);
 330                 if (!err)
 331                         err = cadence_qspi_apb_command_write(priv, op);
 332                 break;
 333         case CQSPI_READ:
 334                 err = cadence_qspi_apb_read_setup(priv, op);
 335                 if (!err) {
 336                         if (priv->is_dma)
 337                                 err = cadence_qspi_apb_dma_read(priv, op);
 338                         else
 339                                 err = cadence_qspi_apb_read_execute(priv, op);
 340                 }
 341                 break;
 342         case CQSPI_WRITE:
 343                 err = cadence_qspi_apb_write_setup(priv, op);
 344                 if (!err)
 345                         err = cadence_qspi_apb_write_execute(priv, op);
 346                 break;
 347         default:
 348                 err = -1;
 349                 break;
 350         }
 351
 352         return err;
 353 }
 354
 355 static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
 356                                         const struct spi_mem_op *op)
 357 {
 358         bool all_true, all_false;
 359
 360         /*
 361          * op->dummy.dtr is required for converting nbytes into ncycles.
 362          * Also, don't check the dtr field of the op phase having zero nbytes.
 363          */
 364         all_true = op->cmd.dtr &&
 365                    (!op->addr.nbytes || op->addr.dtr) &&
 366                    (!op->dummy.nbytes || op->dummy.dtr) &&
 367                    (!op->data.nbytes || op->data.dtr);
 368
 369         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
 370                     !op->data.dtr;
 371
 372         /* Mixed DTR modes not supported. */
 373         if (!(all_true || all_false))
 374                 return false;
 375
 376         if (all_true)
 377                 return spi_mem_dtr_supports_op(slave, op);
 378         else
 379                 return spi_mem_default_supports_op(slave, op);
 380 }
 381
 382 static int cadence_spi_of_to_plat(struct udevice *bus)
 383 {
 384         struct cadence_spi_plat *plat = dev_get_plat(bus);
 385         struct cadence_spi_priv *priv = dev_get_priv(bus);
 386         ofnode subnode;
 387
 388         plat->regbase = devfdt_get_addr_index_ptr(bus, 0);
 389         plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
 390         plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
 391         plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
 392         plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
 393         plat->trigger_address = dev_read_u32_default(bus,
 394                                                      "cdns,trigger-address",
 395                                                      0);
 396         /* Use DAC mode only when MMIO window is at least 8M wide */
 397         if (plat->ahbsize >= SZ_8M)
 398                 priv->use_dac_mode = true;
 399
 400         plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
 401
 402         /* All other parameters are embedded in the child node */
 403         subnode = dev_read_first_subnode(bus);
 404         if (!ofnode_valid(subnode)) {
 405                 printf("Error: subnode with SPI flash config missing!\n");
 406                 return -ENODEV;
 407         }
 408
 409         /* Use 500 KHz as a suitable default */
 410         plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
 411                                                500000);
 412
 413         /* Read other parameters from DT */
 414         plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
 415         plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
 416         plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
 417                                                  200);
 418         plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
 419                                                  255);
 420         plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 421         plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 422         /*
 423          * Read delay should be an unsigned value but we use a signed integer
 424          * so that negative values can indicate that the device tree did not
 425          * specify any signed values and we need to perform the calibration
 426          * sequence to find it out.
 427          */
 428         plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
 429                                                    -1);
 430
 431         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 432               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 433               plat->page_size);
 434
 435         return 0;
 436 }
 437
 438 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
 439         .exec_op = cadence_spi_mem_exec_op,
 440         .supports_op = cadence_spi_mem_supports_op,
 441 };
 442
 443 static const struct dm_spi_ops cadence_spi_ops = {
 444         .set_speed      = cadence_spi_set_speed,
 445         .set_mode       = cadence_spi_set_mode,
 446         .mem_ops        = &cadence_spi_mem_ops,
 447         /*
 448          * cs_info is not needed, since we require all chip selects to be
 449          * in the device tree explicitly
 450          */
 451 };
 452
 453 static const struct udevice_id cadence_spi_ids[] = {
 454         { .compatible = "cdns,qspi-nor" },
 455         { .compatible = "ti,am654-ospi" },
 456         { }
 457 };
 458
 459 U_BOOT_DRIVER(cadence_spi) = {
 460         .name = "cadence_spi",
 461         .id = UCLASS_SPI,
 462         .of_match = cadence_spi_ids,
 463         .ops = &cadence_spi_ops,
 464         .of_to_plat = cadence_spi_of_to_plat,
 465         .plat_auto      = sizeof(struct cadence_spi_plat),
 466         .priv_auto      = sizeof(struct cadence_spi_priv),
 467         .probe = cadence_spi_probe,
 468         .remove = cadence_spi_remove,
 469         .flags = DM_FLAG_OS_PREPARE,
 470 };