drivers/spi/cadence_qspi.h

   1 /*
   2  * Copyright (C) 2012
   3  * Altera Corporation <www.altera.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CADENCE_QSPI_H__
   9 #define __CADENCE_QSPI_H__
  10
  11 #define CQSPI_IS_ADDR(cmd_len)          (cmd_len > 1 ? 1 : 0)
  12
  13 #define CQSPI_NO_DECODER_MAX_CS         4
  14 #define CQSPI_DECODER_MAX_CS            16
  15 #define CQSPI_READ_CAPTURE_MAX_DELAY    16
  16
  17 struct cadence_spi_platdata {
  18         unsigned int    max_hz;
  19         void            *regbase;
  20         void            *ahbbase;
  21
  22         u32             page_size;
  23         u32             block_size;
  24         u32             tshsl_ns;
  25         u32             tsd2d_ns;
  26         u32             tchsh_ns;
  27         u32             tslch_ns;
  28 };
  29
  30 struct cadence_spi_priv {
  31         void            *regbase;
  32         void            *ahbbase;
  33         size_t          cmd_len;
  34         u8              cmd_buf[32];
  35         size_t          data_len;
  36
  37         int             qspi_is_init;
  38         unsigned int    qspi_calibrated_hz;
  39         unsigned int    qspi_calibrated_cs;
  40 };
  41
  42 /* Functions call declaration */
  43 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
  44 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
  45 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
  46
  47 int cadence_qspi_apb_command_read(void *reg_base_addr,
  48         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
  49 int cadence_qspi_apb_command_write(void *reg_base_addr,
  50         unsigned int cmdlen, const u8 *cmdbuf,
  51         unsigned int txlen,  const u8 *txbuf);
  52
  53 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
  54         unsigned int cmdlen, const u8 *cmdbuf);
  55 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
  56         unsigned int rxlen, u8 *rxbuf);
  57 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
  58         unsigned int cmdlen, const u8 *cmdbuf);
  59 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
  60         unsigned int txlen, const u8 *txbuf);
  61
  62 void cadence_qspi_apb_chipselect(void *reg_base,
  63         unsigned int chip_select, unsigned int decoder_enable);
  64 void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
  65         unsigned int clk_pol, unsigned int clk_pha);
  66 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
  67         unsigned int ref_clk_hz, unsigned int sclk_hz);
  68 void cadence_qspi_apb_delay(void *reg_base,
  69         unsigned int ref_clk, unsigned int sclk_hz,
  70         unsigned int tshsl_ns, unsigned int tsd2d_ns,
  71         unsigned int tchsh_ns, unsigned int tslch_ns);
  72 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
  73 void cadence_qspi_apb_readdata_capture(void *reg_base,
  74         unsigned int bypass, unsigned int delay);
  75
  76 #endif /* __CADENCE_QSPI_H__ */