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Merge branch 'master' of git://git.denx.de/u-boot-spi
[people/ms/u-boot.git] / drivers / spi / cadence_qspi_apb.c
1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <linux/errno.h>
31 #include <wait_bit.h>
32 #include <spi.h>
33 #include "cadence_qspi.h"
34
35 #define CQSPI_REG_POLL_US 1 /* 1us */
36 #define CQSPI_REG_RETRY 10000
37 #define CQSPI_POLL_IDLE_RETRY 3
38
39 #define CQSPI_FIFO_WIDTH 4
40
41 #define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
42
43 /* Transfer mode */
44 #define CQSPI_INST_TYPE_SINGLE 0
45 #define CQSPI_INST_TYPE_DUAL 1
46 #define CQSPI_INST_TYPE_QUAD 2
47
48 #define CQSPI_STIG_DATA_LEN_MAX 8
49
50 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
51 #define CQSPI_DUMMY_BYTES_MAX 4
52
53 #define CQSPI_REG_SRAM_FILL_THRESHOLD \
54 ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
55
56 /****************************************************************************
57 * Controller's configuration and status register (offset from QSPI_BASE)
58 ****************************************************************************/
59 #define CQSPI_REG_CONFIG 0x00
60 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
62 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
63 #define CQSPI_REG_CONFIG_DIRECT BIT(7)
64 #define CQSPI_REG_CONFIG_DECODE BIT(9)
65 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
67 #define CQSPI_REG_CONFIG_BAUD_LSB 19
68 #define CQSPI_REG_CONFIG_IDLE_LSB 31
69 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
70 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
71
72 #define CQSPI_REG_RD_INSTR 0x04
73 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
77 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
78 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
82 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
83
84 #define CQSPI_REG_WR_INSTR 0x08
85 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
86
87 #define CQSPI_REG_DELAY 0x0C
88 #define CQSPI_REG_DELAY_TSLCH_LSB 0
89 #define CQSPI_REG_DELAY_TCHSH_LSB 8
90 #define CQSPI_REG_DELAY_TSD2D_LSB 16
91 #define CQSPI_REG_DELAY_TSHSL_LSB 24
92 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
93 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
94 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
95 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
96
97 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
98 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
99 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
100 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
101
102 #define CQSPI_REG_SIZE 0x14
103 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
104 #define CQSPI_REG_SIZE_PAGE_LSB 4
105 #define CQSPI_REG_SIZE_BLOCK_LSB 16
106 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
107 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
108 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
109
110 #define CQSPI_REG_SRAMPARTITION 0x18
111 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
112
113 #define CQSPI_REG_REMAP 0x24
114 #define CQSPI_REG_MODE_BIT 0x28
115
116 #define CQSPI_REG_SDRAMLEVEL 0x2C
117 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
118 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
119 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
120 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
121
122 #define CQSPI_REG_IRQSTATUS 0x40
123 #define CQSPI_REG_IRQMASK 0x44
124
125 #define CQSPI_REG_INDIRECTRD 0x60
126 #define CQSPI_REG_INDIRECTRD_START BIT(0)
127 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
128 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
129 #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
130
131 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
132 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
133 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
134
135 #define CQSPI_REG_CMDCTRL 0x90
136 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
137 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
138 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
139 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
140 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
142 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
143 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
144 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
145 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
146 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
147 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
149 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
150 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
151
152 #define CQSPI_REG_INDIRECTWR 0x70
153 #define CQSPI_REG_INDIRECTWR_START BIT(0)
154 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
155 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
156 #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
157
158 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
159 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
160 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
161
162 #define CQSPI_REG_CMDADDRESS 0x94
163 #define CQSPI_REG_CMDREADDATALOWER 0xA0
164 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
165 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
166 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
167
168 #define CQSPI_REG_IS_IDLE(base) \
169 ((readl(base + CQSPI_REG_CONFIG) >> \
170 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
171
172 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
173 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
174 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
175
176 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
177 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
178 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
179
180 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
181 unsigned int addr_width)
182 {
183 unsigned int addr;
184
185 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
186
187 if (addr_width == 4)
188 addr = (addr << 8) | addr_buf[3];
189
190 return addr;
191 }
192
193 void cadence_qspi_apb_controller_enable(void *reg_base)
194 {
195 unsigned int reg;
196 reg = readl(reg_base + CQSPI_REG_CONFIG);
197 reg |= CQSPI_REG_CONFIG_ENABLE;
198 writel(reg, reg_base + CQSPI_REG_CONFIG);
199 }
200
201 void cadence_qspi_apb_controller_disable(void *reg_base)
202 {
203 unsigned int reg;
204 reg = readl(reg_base + CQSPI_REG_CONFIG);
205 reg &= ~CQSPI_REG_CONFIG_ENABLE;
206 writel(reg, reg_base + CQSPI_REG_CONFIG);
207 }
208
209 /* Return 1 if idle, otherwise return 0 (busy). */
210 static unsigned int cadence_qspi_wait_idle(void *reg_base)
211 {
212 unsigned int start, count = 0;
213 /* timeout in unit of ms */
214 unsigned int timeout = 5000;
215
216 start = get_timer(0);
217 for ( ; get_timer(start) < timeout ; ) {
218 if (CQSPI_REG_IS_IDLE(reg_base))
219 count++;
220 else
221 count = 0;
222 /*
223 * Ensure the QSPI controller is in true idle state after
224 * reading back the same idle status consecutively
225 */
226 if (count >= CQSPI_POLL_IDLE_RETRY)
227 return 1;
228 }
229
230 /* Timeout, still in busy mode. */
231 printf("QSPI: QSPI is still busy after poll for %d times.\n",
232 CQSPI_REG_RETRY);
233 return 0;
234 }
235
236 void cadence_qspi_apb_readdata_capture(void *reg_base,
237 unsigned int bypass, unsigned int delay)
238 {
239 unsigned int reg;
240 cadence_qspi_apb_controller_disable(reg_base);
241
242 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
243
244 if (bypass)
245 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
246 else
247 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
248
249 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
250 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
251
252 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
253 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
254
255 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
256
257 cadence_qspi_apb_controller_enable(reg_base);
258 }
259
260 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
261 unsigned int ref_clk_hz, unsigned int sclk_hz)
262 {
263 unsigned int reg;
264 unsigned int div;
265
266 cadence_qspi_apb_controller_disable(reg_base);
267 reg = readl(reg_base + CQSPI_REG_CONFIG);
268 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
269
270 /*
271 * The baud_div field in the config reg is 4 bits, and the ref clock is
272 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
273 * SPI clock rate is less than or equal to the requested clock rate.
274 */
275 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
276
277 /* ensure the baud rate doesn't exceed the max value */
278 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
279 div = CQSPI_REG_CONFIG_BAUD_MASK;
280
281 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
282 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
283
284 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
285 writel(reg, reg_base + CQSPI_REG_CONFIG);
286
287 cadence_qspi_apb_controller_enable(reg_base);
288 }
289
290 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
291 {
292 unsigned int reg;
293
294 cadence_qspi_apb_controller_disable(reg_base);
295 reg = readl(reg_base + CQSPI_REG_CONFIG);
296 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
297
298 if (mode & SPI_CPOL)
299 reg |= CQSPI_REG_CONFIG_CLK_POL;
300 if (mode & SPI_CPHA)
301 reg |= CQSPI_REG_CONFIG_CLK_PHA;
302
303 writel(reg, reg_base + CQSPI_REG_CONFIG);
304
305 cadence_qspi_apb_controller_enable(reg_base);
306 }
307
308 void cadence_qspi_apb_chipselect(void *reg_base,
309 unsigned int chip_select, unsigned int decoder_enable)
310 {
311 unsigned int reg;
312
313 cadence_qspi_apb_controller_disable(reg_base);
314
315 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
316 decoder_enable);
317
318 reg = readl(reg_base + CQSPI_REG_CONFIG);
319 /* docoder */
320 if (decoder_enable) {
321 reg |= CQSPI_REG_CONFIG_DECODE;
322 } else {
323 reg &= ~CQSPI_REG_CONFIG_DECODE;
324 /* Convert CS if without decoder.
325 * CS0 to 4b'1110
326 * CS1 to 4b'1101
327 * CS2 to 4b'1011
328 * CS3 to 4b'0111
329 */
330 chip_select = 0xF & ~(1 << chip_select);
331 }
332
333 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
334 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
335 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
336 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
337 writel(reg, reg_base + CQSPI_REG_CONFIG);
338
339 cadence_qspi_apb_controller_enable(reg_base);
340 }
341
342 void cadence_qspi_apb_delay(void *reg_base,
343 unsigned int ref_clk, unsigned int sclk_hz,
344 unsigned int tshsl_ns, unsigned int tsd2d_ns,
345 unsigned int tchsh_ns, unsigned int tslch_ns)
346 {
347 unsigned int ref_clk_ns;
348 unsigned int sclk_ns;
349 unsigned int tshsl, tchsh, tslch, tsd2d;
350 unsigned int reg;
351
352 cadence_qspi_apb_controller_disable(reg_base);
353
354 /* Convert to ns. */
355 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
356
357 /* Convert to ns. */
358 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
359
360 /* The controller adds additional delay to that programmed in the reg */
361 if (tshsl_ns >= sclk_ns + ref_clk_ns)
362 tshsl_ns -= sclk_ns + ref_clk_ns;
363 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
364 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
365 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
366 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
367 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
368 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
369
370 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
371 << CQSPI_REG_DELAY_TSHSL_LSB);
372 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
373 << CQSPI_REG_DELAY_TCHSH_LSB);
374 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
375 << CQSPI_REG_DELAY_TSLCH_LSB);
376 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
377 << CQSPI_REG_DELAY_TSD2D_LSB);
378 writel(reg, reg_base + CQSPI_REG_DELAY);
379
380 cadence_qspi_apb_controller_enable(reg_base);
381 }
382
383 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
384 {
385 unsigned reg;
386
387 cadence_qspi_apb_controller_disable(plat->regbase);
388
389 /* Configure the device size and address bytes */
390 reg = readl(plat->regbase + CQSPI_REG_SIZE);
391 /* Clear the previous value */
392 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
393 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
394 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
395 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
396 writel(reg, plat->regbase + CQSPI_REG_SIZE);
397
398 /* Configure the remap address register, no remap */
399 writel(0, plat->regbase + CQSPI_REG_REMAP);
400
401 /* Indirect mode configurations */
402 writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
403
404 /* Disable all interrupts */
405 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
406
407 cadence_qspi_apb_controller_enable(plat->regbase);
408 }
409
410 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
411 unsigned int reg)
412 {
413 unsigned int retry = CQSPI_REG_RETRY;
414
415 /* Write the CMDCTRL without start execution. */
416 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
417 /* Start execute */
418 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
419 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
420
421 while (retry--) {
422 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
423 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
424 break;
425 udelay(1);
426 }
427
428 if (!retry) {
429 printf("QSPI: flash command execution timeout\n");
430 return -EIO;
431 }
432
433 /* Polling QSPI idle status. */
434 if (!cadence_qspi_wait_idle(reg_base))
435 return -EIO;
436
437 return 0;
438 }
439
440 /* For command RDID, RDSR. */
441 int cadence_qspi_apb_command_read(void *reg_base,
442 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
443 u8 *rxbuf)
444 {
445 unsigned int reg;
446 unsigned int read_len;
447 int status;
448
449 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
450 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
451 cmdlen, rxlen);
452 return -EINVAL;
453 }
454
455 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
456
457 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
458
459 /* 0 means 1 byte. */
460 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
461 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
462 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
463 if (status != 0)
464 return status;
465
466 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
467
468 /* Put the read value into rx_buf */
469 read_len = (rxlen > 4) ? 4 : rxlen;
470 memcpy(rxbuf, &reg, read_len);
471 rxbuf += read_len;
472
473 if (rxlen > 4) {
474 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
475
476 read_len = rxlen - read_len;
477 memcpy(rxbuf, &reg, read_len);
478 }
479 return 0;
480 }
481
482 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
483 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
484 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
485 {
486 unsigned int reg = 0;
487 unsigned int addr_value;
488 unsigned int wr_data;
489 unsigned int wr_len;
490
491 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
492 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
493 cmdlen, txlen);
494 return -EINVAL;
495 }
496
497 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
498
499 if (cmdlen == 4 || cmdlen == 5) {
500 /* Command with address */
501 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
502 /* Number of bytes to write. */
503 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
504 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
505 /* Get address */
506 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
507 cmdlen >= 5 ? 4 : 3);
508
509 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
510 }
511
512 if (txlen) {
513 /* writing data = yes */
514 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
515 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
516 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
517
518 wr_len = txlen > 4 ? 4 : txlen;
519 memcpy(&wr_data, txbuf, wr_len);
520 writel(wr_data, reg_base +
521 CQSPI_REG_CMDWRITEDATALOWER);
522
523 if (txlen > 4) {
524 txbuf += wr_len;
525 wr_len = txlen - wr_len;
526 memcpy(&wr_data, txbuf, wr_len);
527 writel(wr_data, reg_base +
528 CQSPI_REG_CMDWRITEDATAUPPER);
529 }
530 }
531
532 /* Execute the command */
533 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
534 }
535
536 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
537 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
538 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
539 {
540 unsigned int reg;
541 unsigned int rd_reg;
542 unsigned int addr_value;
543 unsigned int dummy_clk;
544 unsigned int dummy_bytes;
545 unsigned int addr_bytes;
546
547 /*
548 * Identify addr_byte. All NOR flash device drivers are using fast read
549 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
550 * With that, the length is in value of 5 or 6. Only FRAM chip from
551 * ramtron using normal read (which won't need dummy byte).
552 * Unlikely NOR flash using normal read due to performance issue.
553 */
554 if (cmdlen >= 5)
555 /* to cater fast read where cmd + addr + dummy */
556 addr_bytes = cmdlen - 2;
557 else
558 /* for normal read (only ramtron as of now) */
559 addr_bytes = cmdlen - 1;
560
561 /* Setup the indirect trigger address */
562 writel((u32)plat->ahbbase,
563 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
564
565 /* Configure the opcode */
566 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
567
568 if (rx_width & SPI_RX_QUAD)
569 /* Instruction and address at DQ0, data at DQ0-3. */
570 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
571
572 /* Get address */
573 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
574 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
575
576 /* The remaining lenght is dummy bytes. */
577 dummy_bytes = cmdlen - addr_bytes - 1;
578 if (dummy_bytes) {
579 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
580 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
581
582 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
583 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
584 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
585 #else
586 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
587 #endif
588
589 /* Convert to clock cycles. */
590 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
591 /* Need to minus the mode byte (8 clocks). */
592 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
593
594 if (dummy_clk)
595 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
596 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
597 }
598
599 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
600
601 /* set device size */
602 reg = readl(plat->regbase + CQSPI_REG_SIZE);
603 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
604 reg |= (addr_bytes - 1);
605 writel(reg, plat->regbase + CQSPI_REG_SIZE);
606 return 0;
607 }
608
609 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
610 {
611 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
612 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
613 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
614 }
615
616 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
617 {
618 unsigned int timeout = 10000;
619 u32 reg;
620
621 while (timeout--) {
622 reg = cadence_qspi_get_rd_sram_level(plat);
623 if (reg)
624 return reg;
625 udelay(1);
626 }
627
628 return -ETIMEDOUT;
629 }
630
631 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
632 unsigned int n_rx, u8 *rxbuf)
633 {
634 unsigned int remaining = n_rx;
635 unsigned int bytes_to_read = 0;
636 int ret;
637
638 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
639
640 /* Start the indirect read transfer */
641 writel(CQSPI_REG_INDIRECTRD_START,
642 plat->regbase + CQSPI_REG_INDIRECTRD);
643
644 while (remaining > 0) {
645 ret = cadence_qspi_wait_for_data(plat);
646 if (ret < 0) {
647 printf("Indirect write timed out (%i)\n", ret);
648 goto failrd;
649 }
650
651 bytes_to_read = ret;
652
653 while (bytes_to_read != 0) {
654 bytes_to_read *= CQSPI_FIFO_WIDTH;
655 bytes_to_read = bytes_to_read > remaining ?
656 remaining : bytes_to_read;
657 /* Handle non-4-byte aligned access to avoid data abort. */
658 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
659 readsb(plat->ahbbase, rxbuf, bytes_to_read);
660 else
661 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
662 rxbuf += bytes_to_read;
663 remaining -= bytes_to_read;
664 bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
665 }
666 }
667
668 /* Check indirect done status */
669 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
670 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
671 if (ret) {
672 printf("Indirect read completion error (%i)\n", ret);
673 goto failrd;
674 }
675
676 /* Clear indirect completion status */
677 writel(CQSPI_REG_INDIRECTRD_DONE,
678 plat->regbase + CQSPI_REG_INDIRECTRD);
679
680 return 0;
681
682 failrd:
683 /* Cancel the indirect read */
684 writel(CQSPI_REG_INDIRECTRD_CANCEL,
685 plat->regbase + CQSPI_REG_INDIRECTRD);
686 return ret;
687 }
688
689 /* Opcode + Address (3/4 bytes) */
690 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
691 unsigned int cmdlen, const u8 *cmdbuf)
692 {
693 unsigned int reg;
694 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
695
696 if (cmdlen < 4 || cmdbuf == NULL) {
697 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
698 cmdlen, (unsigned int)cmdbuf);
699 return -EINVAL;
700 }
701 /* Setup the indirect trigger address */
702 writel((u32)plat->ahbbase,
703 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
704
705 /* Configure the opcode */
706 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
707 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
708
709 /* Setup write address. */
710 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
711 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
712
713 reg = readl(plat->regbase + CQSPI_REG_SIZE);
714 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
715 reg |= (addr_bytes - 1);
716 writel(reg, plat->regbase + CQSPI_REG_SIZE);
717 return 0;
718 }
719
720 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
721 unsigned int n_tx, const u8 *txbuf)
722 {
723 unsigned int page_size = plat->page_size;
724 unsigned int remaining = n_tx;
725 unsigned int write_bytes;
726 int ret;
727
728 /* Configure the indirect read transfer bytes */
729 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
730
731 /* Start the indirect write transfer */
732 writel(CQSPI_REG_INDIRECTWR_START,
733 plat->regbase + CQSPI_REG_INDIRECTWR);
734
735 while (remaining > 0) {
736 write_bytes = remaining > page_size ? page_size : remaining;
737 /* Handle non-4-byte aligned access to avoid data abort. */
738 if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
739 writesb(plat->ahbbase, txbuf, write_bytes);
740 else
741 writesl(plat->ahbbase, txbuf, write_bytes >> 2);
742
743 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
744 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
745 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
746 if (ret) {
747 printf("Indirect write timed out (%i)\n", ret);
748 goto failwr;
749 }
750
751 txbuf += write_bytes;
752 remaining -= write_bytes;
753 }
754
755 /* Check indirect done status */
756 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
757 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
758 if (ret) {
759 printf("Indirect write completion error (%i)\n", ret);
760 goto failwr;
761 }
762
763 /* Clear indirect completion status */
764 writel(CQSPI_REG_INDIRECTWR_DONE,
765 plat->regbase + CQSPI_REG_INDIRECTWR);
766 return 0;
767
768 failwr:
769 /* Cancel the indirect write */
770 writel(CQSPI_REG_INDIRECTWR_CANCEL,
771 plat->regbase + CQSPI_REG_INDIRECTWR);
772 return ret;
773 }
774
775 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
776 {
777 unsigned int reg;
778
779 /* enter XiP mode immediately and enable direct mode */
780 reg = readl(reg_base + CQSPI_REG_CONFIG);
781 reg |= CQSPI_REG_CONFIG_ENABLE;
782 reg |= CQSPI_REG_CONFIG_DIRECT;
783 reg |= CQSPI_REG_CONFIG_XIP_IMM;
784 writel(reg, reg_base + CQSPI_REG_CONFIG);
785
786 /* keep the XiP mode */
787 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
788
789 /* Enable mode bit at devrd */
790 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
791 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
792 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
793 }
"Das U-Boot" Source Tree