drivers/spi/cf_spi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *
   4  * (C) Copyright 2000-2003
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   8  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   9  *
  10  * Support for DM and DT, non-DM code removed.
  11  * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
  12  *
  13  * TODO: fsl_dspi.c should work as a driver for the DSPI module.
  14  */
  15
  16 #include <common.h>
  17 #include <dm.h>
  18 #include <log.h>
  19 #include <asm/global_data.h>
  20 #include <dm/platform_data/spi_coldfire.h>
  21 #include <spi.h>
  22 #include <malloc.h>
  23 #include <asm/coldfire/dspi.h>
  24 #include <asm/io.h>
  25
  26 struct coldfire_spi_priv {
  27         struct dspi *regs;
  28         uint baudrate;
  29         int mode;
  30         int charbit;
  31 };
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifndef CONFIG_SPI_IDLE_VAL
  36 #if defined(CONFIG_SPI_MMC)
  37 #define CONFIG_SPI_IDLE_VAL     0xFFFF
  38 #else
  39 #define CONFIG_SPI_IDLE_VAL     0x0
  40 #endif
  41 #endif
  42
  43 /*
  44  * DSPI specific mode
  45  *
  46  * bit 31 - 28: Transfer size 3 to 16 bits
  47  *     27 - 26: PCS to SCK delay prescaler
  48  *     25 - 24: After SCK delay prescaler
  49  *     23 - 22: Delay after transfer prescaler
  50  *     21     : Allow overwrite for bit 31-22 and bit 20-8
  51  *     20     : Double baud rate
  52  *     19 - 16: PCS to SCK delay scaler
  53  *     15 - 12: After SCK delay scaler
  54  *     11 -  8: Delay after transfer scaler
  55  *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
  56  */
  57 #define SPI_MODE_MOD                    0x00200000
  58 #define SPI_MODE_DBLRATE                0x00100000
  59
  60 #define SPI_MODE_XFER_SZ_MASK           0xf0000000
  61 #define SPI_MODE_DLY_PRE_MASK           0x0fc00000
  62 #define SPI_MODE_DLY_SCA_MASK           0x000fff00
  63
  64 #define MCF_FRM_SZ_16BIT                DSPI_CTAR_TRSZ(0xf)
  65 #define MCF_DSPI_SPEED_BESTMATCH        0x7FFFFFFF
  66 #define MCF_DSPI_MAX_CTAR_REGS          8
  67
  68 /* Default values */
  69 #define MCF_DSPI_DEFAULT_SCK_FREQ       10000000
  70 #define MCF_DSPI_DEFAULT_MAX_CS         4
  71 #define MCF_DSPI_DEFAULT_MODE           0
  72
  73 #define MCF_DSPI_DEFAULT_CTAR           (DSPI_CTAR_TRSZ(7) | \
  74                                         DSPI_CTAR_PCSSCK_1CLK | \
  75                                         DSPI_CTAR_PASC(0) | \
  76                                         DSPI_CTAR_PDT(0) | \
  77                                         DSPI_CTAR_CSSCK(0) | \
  78                                         DSPI_CTAR_ASC(0) | \
  79                                         DSPI_CTAR_DT(1) | \
  80                                         DSPI_CTAR_BR(6))
  81
  82 #define MCF_CTAR_MODE_MASK              (MCF_FRM_SZ_16BIT | \
  83                                         DSPI_CTAR_PCSSCK(3) | \
  84                                         DSPI_CTAR_PASC_7CLK | \
  85                                         DSPI_CTAR_PDT(3) | \
  86                                         DSPI_CTAR_CSSCK(0x0f) | \
  87                                         DSPI_CTAR_ASC(0x0f) | \
  88                                         DSPI_CTAR_DT(0x0f))
  89
  90 #define setup_ctrl(ctrl, cs)    ((ctrl & 0xFF000000) | ((1 << cs) << 16))
  91
  92 static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
  93                             u32 ctrl, u16 data)
  94 {
  95         /*
  96          * Need to check fifo level here
  97          */
  98         while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
  99                 ;
 100
 101         writel(ctrl | data, &cfspi->regs->tfr);
 102 }
 103
 104 static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
 105 {
 106
 107         while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
 108                 ;
 109
 110         return readw(&cfspi->regs->rfr);
 111 }
 112
 113 static int coldfire_spi_claim_bus(struct udevice *dev)
 114 {
 115         struct udevice *bus = dev->parent;
 116         struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
 117         struct dspi *dspi = cfspi->regs;
 118         struct dm_spi_slave_plat *slave_plat =
 119                 dev_get_parent_plat(dev);
 120
 121         if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
 122                 return -1;
 123
 124         /* Clear FIFO and resume transfer */
 125         clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 126
 127         dspi_chip_select(slave_plat->cs);
 128
 129         return 0;
 130 }
 131
 132 static int coldfire_spi_release_bus(struct udevice *dev)
 133 {
 134         struct udevice *bus = dev->parent;
 135         struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
 136         struct dspi *dspi = cfspi->regs;
 137         struct dm_spi_slave_plat *slave_plat =
 138                 dev_get_parent_plat(dev);
 139
 140         /* Clear FIFO */
 141         clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 142
 143         dspi_chip_unselect(slave_plat->cs);
 144
 145         return 0;
 146 }
 147
 148 static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
 149                              const void *dout, void *din,
 150                              unsigned long flags)
 151 {
 152         struct udevice *bus = dev_get_parent(dev);
 153         struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
 154         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 155         u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
 156         u8 *spi_rd = NULL, *spi_wr = NULL;
 157         static u32 ctrl;
 158         uint len = bitlen >> 3;
 159
 160         if (cfspi->charbit == 16) {
 161                 bitlen >>= 1;
 162                 spi_wr16 = (u16 *)dout;
 163                 spi_rd16 = (u16 *)din;
 164         } else {
 165                 spi_wr = (u8 *)dout;
 166                 spi_rd = (u8 *)din;
 167         }
 168
 169         if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
 170                 ctrl |= DSPI_TFR_CONT;
 171
 172         ctrl = setup_ctrl(ctrl, slave_plat->cs);
 173
 174         if (len > 1) {
 175                 int tmp_len = len - 1;
 176
 177                 while (tmp_len--) {
 178                         if (dout) {
 179                                 if (cfspi->charbit == 16)
 180                                         cfspi_tx(cfspi, ctrl, *spi_wr16++);
 181                                 else
 182                                         cfspi_tx(cfspi, ctrl, *spi_wr++);
 183                                 cfspi_rx(cfspi);
 184                         }
 185
 186                         if (din) {
 187                                 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
 188                                 if (cfspi->charbit == 16)
 189                                         *spi_rd16++ = cfspi_rx(cfspi);
 190                                 else
 191                                         *spi_rd++ = cfspi_rx(cfspi);
 192                         }
 193                 }
 194
 195                 len = 1;        /* remaining byte */
 196         }
 197
 198         if (flags & SPI_XFER_END)
 199                 ctrl &= ~DSPI_TFR_CONT;
 200
 201         if (len) {
 202                 if (dout) {
 203                         if (cfspi->charbit == 16)
 204                                 cfspi_tx(cfspi, ctrl, *spi_wr16);
 205                         else
 206                                 cfspi_tx(cfspi, ctrl, *spi_wr);
 207                         cfspi_rx(cfspi);
 208                 }
 209
 210                 if (din) {
 211                         cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
 212                         if (cfspi->charbit == 16)
 213                                 *spi_rd16 = cfspi_rx(cfspi);
 214                         else
 215                                 *spi_rd = cfspi_rx(cfspi);
 216                 }
 217         } else {
 218                 /* dummy read */
 219                 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
 220                 cfspi_rx(cfspi);
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
 227 {
 228         struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
 229         struct dspi *dspi = cfspi->regs;
 230         int prescaler[] = { 2, 3, 5, 7 };
 231         int scaler[] = {
 232                 2, 4, 6, 8,
 233                 16, 32, 64, 128,
 234                 256, 512, 1024, 2048,
 235                 4096, 8192, 16384, 32768
 236         };
 237         int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
 238         int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
 239         u32 bus_setup;
 240
 241         cfspi->baudrate = max_hz;
 242
 243         /* Read current setup */
 244         bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
 245
 246         tmp = (prescaler[3] * scaler[15]);
 247         /* Maximum and minimum baudrate it can handle */
 248         if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
 249             (cfspi->baudrate < (gd->bus_clk / tmp))) {
 250                 printf("Exceed baudrate limitation: Max %d - Min %d\n",
 251                        (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
 252                 return -1;
 253         }
 254
 255         /* Activate Double Baud when it exceed 1/4 the bus clk */
 256         if ((bus_setup & DSPI_CTAR_DBR) ||
 257             (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
 258                 bus_setup |= DSPI_CTAR_DBR;
 259                 dbr = 1;
 260         }
 261
 262         /* Overwrite default value set in platform configuration file */
 263         if (cfspi->mode & SPI_MODE_MOD) {
 264                 /*
 265                  * Check to see if it is enabled by default in platform
 266                  * config, or manual setting passed by mode parameter
 267                  */
 268                 if (cfspi->mode & SPI_MODE_DBLRATE) {
 269                         bus_setup |= DSPI_CTAR_DBR;
 270                         dbr = 1;
 271                 }
 272         }
 273
 274         pbrcnt = sizeof(prescaler) / sizeof(int);
 275         brcnt = sizeof(scaler) / sizeof(int);
 276
 277         /* baudrate calculation - to closer value, may not be exact match */
 278         for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
 279                 baud_speed = gd->bus_clk / prescaler[i];
 280                 for (j = 0; j < brcnt; j++) {
 281                         tmp = (baud_speed / scaler[j]) * (1 + dbr);
 282
 283                         if (tmp > cfspi->baudrate)
 284                                 diff = tmp - cfspi->baudrate;
 285                         else
 286                                 diff = cfspi->baudrate - tmp;
 287
 288                         if (diff < bestmatch) {
 289                                 bestmatch = diff;
 290                                 best_i = i;
 291                                 best_j = j;
 292                         }
 293                 }
 294         }
 295
 296         bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
 297         bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
 298         writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
 299
 300         return 0;
 301 }
 302
 303 static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
 304 {
 305         struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
 306         struct dspi *dspi = cfspi->regs;
 307         u32 bus_setup = 0;
 308
 309         cfspi->mode = mode;
 310
 311         if (cfspi->mode & SPI_CPOL)
 312                 bus_setup |= DSPI_CTAR_CPOL;
 313         if (cfspi->mode & SPI_CPHA)
 314                 bus_setup |= DSPI_CTAR_CPHA;
 315         if (cfspi->mode & SPI_LSB_FIRST)
 316                 bus_setup |= DSPI_CTAR_LSBFE;
 317
 318         /* Overwrite default value set in platform configuration file */
 319         if (cfspi->mode & SPI_MODE_MOD) {
 320                 if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
 321                         bus_setup |=
 322                             readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
 323                 else
 324                         bus_setup |=
 325                             ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
 326
 327                 /* PSCSCK, PASC, PDT */
 328                 bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
 329                 /* CSSCK, ASC, DT */
 330                 bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
 331         } else {
 332                 bus_setup |=
 333                         (readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
 334         }
 335
 336         cfspi->charbit =
 337                 ((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
 338                         MCF_FRM_SZ_16BIT) ? 16 : 8;
 339
 340         setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
 341
 342         return 0;
 343 }
 344
 345 static int coldfire_spi_probe(struct udevice *bus)
 346 {
 347         struct coldfire_spi_plat *plat = dev_get_plat(bus);
 348         struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
 349         struct dspi *dspi = cfspi->regs;
 350         int i;
 351
 352         cfspi->regs = (struct dspi *)plat->regs_addr;
 353
 354         cfspi->baudrate = plat->speed_hz;
 355         cfspi->mode = plat->mode;
 356
 357         for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
 358                 unsigned int ctar = 0;
 359
 360                 if (plat->ctar[i][0] == 0)
 361                         break;
 362
 363                 ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
 364                         DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
 365                         DSPI_CTAR_PASC(plat->ctar[i][2]) |
 366                         DSPI_CTAR_PDT(plat->ctar[i][3]) |
 367                         DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
 368                         DSPI_CTAR_ASC(plat->ctar[i][5]) |
 369                         DSPI_CTAR_DT(plat->ctar[i][6]) |
 370                         DSPI_CTAR_BR(plat->ctar[i][7]);
 371
 372                 writel(ctar, &cfspi->regs->ctar[i]);
 373         }
 374
 375         /* Default CTARs */
 376         for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
 377                 writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
 378
 379         dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
 380             DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
 381             DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
 382             DSPI_MCR_CRXF | DSPI_MCR_CTXF;
 383
 384         return 0;
 385 }
 386
 387 #if CONFIG_IS_ENABLED(OF_REAL)
 388 static int coldfire_dspi_of_to_plat(struct udevice *bus)
 389 {
 390         fdt_addr_t addr;
 391         struct coldfire_spi_plat *plat = dev_get_plat(bus);
 392         const void *blob = gd->fdt_blob;
 393         int node = dev_of_offset(bus);
 394         int *ctar, len;
 395
 396         addr = dev_read_addr(bus);
 397         if (addr == FDT_ADDR_T_NONE)
 398                 return -ENOMEM;
 399
 400         plat->regs_addr = addr;
 401
 402         plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
 403                                       MCF_DSPI_DEFAULT_MAX_CS);
 404
 405         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
 406                                         MCF_DSPI_DEFAULT_SCK_FREQ);
 407
 408         plat->mode = fdtdec_get_int(blob, node, "spi-mode",
 409                                     MCF_DSPI_DEFAULT_MODE);
 410
 411         memset(plat->ctar, 0, sizeof(plat->ctar));
 412
 413         ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
 414
 415         if (ctar && len) {
 416                 int i, q, ctar_regs;
 417
 418                 ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
 419
 420                 if (ctar_regs > MAX_CTAR_REGS)
 421                         ctar_regs = MAX_CTAR_REGS;
 422
 423                 for (i = 0; i < ctar_regs; i++) {
 424                         for (q = 0; q < MAX_CTAR_FIELDS; q++)
 425                                 plat->ctar[i][q] = *ctar++;
 426                 }
 427         }
 428
 429         debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
 430               (void *)plat->regs_addr,
 431                plat->speed_hz, plat->num_cs, plat->mode);
 432
 433         return 0;
 434 }
 435
 436 static const struct udevice_id coldfire_spi_ids[] = {
 437         { .compatible = "fsl,mcf-dspi" },
 438         { }
 439 };
 440 #endif
 441
 442 static const struct dm_spi_ops coldfire_spi_ops = {
 443         .claim_bus      = coldfire_spi_claim_bus,
 444         .release_bus    = coldfire_spi_release_bus,
 445         .xfer           = coldfire_spi_xfer,
 446         .set_speed      = coldfire_spi_set_speed,
 447         .set_mode       = coldfire_spi_set_mode,
 448 };
 449
 450 U_BOOT_DRIVER(coldfire_spi) = {
 451         .name = "spi_coldfire",
 452         .id = UCLASS_SPI,
 453 #if CONFIG_IS_ENABLED(OF_REAL)
 454         .of_match = coldfire_spi_ids,
 455         .of_to_plat = coldfire_dspi_of_to_plat,
 456         .plat_auto      = sizeof(struct coldfire_spi_plat),
 457 #endif
 458         .probe = coldfire_spi_probe,
 459         .ops = &coldfire_spi_ops,
 460         .priv_auto      = sizeof(struct coldfire_spi_priv),
 461 };