drivers/spi/designware_spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Designware master SPI core controller driver
   4  *
   5  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   6  *
   7  * Very loosely based on the Linux driver:
   8  * drivers/spi/spi-dw.c, which is:
   9  * Copyright (c) 2009, Intel Corporation.
  10  */
  11
  12 #include <common.h>
  13 #include <asm-generic/gpio.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <malloc.h>
  18 #include <spi.h>
  19 #include <fdtdec.h>
  20 #include <reset.h>
  21 #include <dm/device_compat.h>
  22 #include <linux/compat.h>
  23 #include <linux/iopoll.h>
  24 #include <asm/io.h>
  25
  26 /* Register offsets */
  27 #define DW_SPI_CTRL0                    0x00
  28 #define DW_SPI_CTRL1                    0x04
  29 #define DW_SPI_SSIENR                   0x08
  30 #define DW_SPI_MWCR                     0x0c
  31 #define DW_SPI_SER                      0x10
  32 #define DW_SPI_BAUDR                    0x14
  33 #define DW_SPI_TXFLTR                   0x18
  34 #define DW_SPI_RXFLTR                   0x1c
  35 #define DW_SPI_TXFLR                    0x20
  36 #define DW_SPI_RXFLR                    0x24
  37 #define DW_SPI_SR                       0x28
  38 #define DW_SPI_IMR                      0x2c
  39 #define DW_SPI_ISR                      0x30
  40 #define DW_SPI_RISR                     0x34
  41 #define DW_SPI_TXOICR                   0x38
  42 #define DW_SPI_RXOICR                   0x3c
  43 #define DW_SPI_RXUICR                   0x40
  44 #define DW_SPI_MSTICR                   0x44
  45 #define DW_SPI_ICR                      0x48
  46 #define DW_SPI_DMACR                    0x4c
  47 #define DW_SPI_DMATDLR                  0x50
  48 #define DW_SPI_DMARDLR                  0x54
  49 #define DW_SPI_IDR                      0x58
  50 #define DW_SPI_VERSION                  0x5c
  51 #define DW_SPI_DR                       0x60
  52
  53 /* Bit fields in CTRLR0 */
  54 #define SPI_DFS_OFFSET                  0
  55
  56 #define SPI_FRF_OFFSET                  4
  57 #define SPI_FRF_SPI                     0x0
  58 #define SPI_FRF_SSP                     0x1
  59 #define SPI_FRF_MICROWIRE               0x2
  60 #define SPI_FRF_RESV                    0x3
  61
  62 #define SPI_MODE_OFFSET                 6
  63 #define SPI_SCPH_OFFSET                 6
  64 #define SPI_SCOL_OFFSET                 7
  65
  66 #define SPI_TMOD_OFFSET                 8
  67 #define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  68 #define SPI_TMOD_TR                     0x0             /* xmit & recv */
  69 #define SPI_TMOD_TO                     0x1             /* xmit only */
  70 #define SPI_TMOD_RO                     0x2             /* recv only */
  71 #define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  72
  73 #define SPI_SLVOE_OFFSET                10
  74 #define SPI_SRL_OFFSET                  11
  75 #define SPI_CFS_OFFSET                  12
  76
  77 /* Bit fields in SR, 7 bits */
  78 #define SR_MASK                         GENMASK(6, 0)   /* cover 7 bits */
  79 #define SR_BUSY                         BIT(0)
  80 #define SR_TF_NOT_FULL                  BIT(1)
  81 #define SR_TF_EMPT                      BIT(2)
  82 #define SR_RF_NOT_EMPT                  BIT(3)
  83 #define SR_RF_FULL                      BIT(4)
  84 #define SR_TX_ERR                       BIT(5)
  85 #define SR_DCOL                         BIT(6)
  86
  87 #define RX_TIMEOUT                      1000            /* timeout in ms */
  88
  89 struct dw_spi_platdata {
  90         s32 frequency;          /* Default clock frequency, -1 for none */
  91         void __iomem *regs;
  92 };
  93
  94 struct dw_spi_priv {
  95         void __iomem *regs;
  96         unsigned int freq;              /* Default frequency */
  97         unsigned int mode;
  98         struct clk clk;
  99         unsigned long bus_clk_rate;
 100
 101         struct gpio_desc cs_gpio;       /* External chip-select gpio */
 102
 103         int bits_per_word;
 104         u8 cs;                  /* chip select pin */
 105         u8 tmode;               /* TR/TO/RO/EEPROM */
 106         u8 type;                /* SPI/SSP/MicroWire */
 107         int len;
 108
 109         u32 fifo_len;           /* depth of the FIFO buffer */
 110         void *tx;
 111         void *tx_end;
 112         void *rx;
 113         void *rx_end;
 114
 115         struct reset_ctl_bulk   resets;
 116 };
 117
 118 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
 119 {
 120         return __raw_readl(priv->regs + offset);
 121 }
 122
 123 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
 124 {
 125         __raw_writel(val, priv->regs + offset);
 126 }
 127
 128 static int request_gpio_cs(struct udevice *bus)
 129 {
 130 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
 131         struct dw_spi_priv *priv = dev_get_priv(bus);
 132         int ret;
 133
 134         /* External chip select gpio line is optional */
 135         ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
 136         if (ret == -ENOENT)
 137                 return 0;
 138
 139         if (ret < 0) {
 140                 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
 141                 return ret;
 142         }
 143
 144         if (dm_gpio_is_valid(&priv->cs_gpio)) {
 145                 dm_gpio_set_dir_flags(&priv->cs_gpio,
 146                                       GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 147         }
 148
 149         debug("%s: used external gpio for CS management\n", __func__);
 150 #endif
 151         return 0;
 152 }
 153
 154 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
 155 {
 156         struct dw_spi_platdata *plat = bus->platdata;
 157
 158         plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
 159
 160         /* Use 500KHz as a suitable default */
 161         plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
 162                                                500000);
 163         debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
 164               plat->frequency);
 165
 166         return request_gpio_cs(bus);
 167 }
 168
 169 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
 170 {
 171         dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
 172 }
 173
 174 /* Restart the controller, disable all interrupts, clean rx fifo */
 175 static void spi_hw_init(struct dw_spi_priv *priv)
 176 {
 177         spi_enable_chip(priv, 0);
 178         dw_write(priv, DW_SPI_IMR, 0xff);
 179         spi_enable_chip(priv, 1);
 180
 181         /*
 182          * Try to detect the FIFO depth if not set by interface driver,
 183          * the depth could be from 2 to 256 from HW spec
 184          */
 185         if (!priv->fifo_len) {
 186                 u32 fifo;
 187
 188                 for (fifo = 1; fifo < 256; fifo++) {
 189                         dw_write(priv, DW_SPI_TXFLTR, fifo);
 190                         if (fifo != dw_read(priv, DW_SPI_TXFLTR))
 191                                 break;
 192                 }
 193
 194                 priv->fifo_len = (fifo == 1) ? 0 : fifo;
 195                 dw_write(priv, DW_SPI_TXFLTR, 0);
 196         }
 197         debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
 198 }
 199
 200 /*
 201  * We define dw_spi_get_clk function as 'weak' as some targets
 202  * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
 203  * and implement dw_spi_get_clk their own way in their clock manager.
 204  */
 205 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
 206 {
 207         struct dw_spi_priv *priv = dev_get_priv(bus);
 208         int ret;
 209
 210         ret = clk_get_by_index(bus, 0, &priv->clk);
 211         if (ret)
 212                 return ret;
 213
 214         ret = clk_enable(&priv->clk);
 215         if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
 216                 return ret;
 217
 218         *rate = clk_get_rate(&priv->clk);
 219         if (!*rate)
 220                 goto err_rate;
 221
 222         debug("%s: get spi controller clk via device tree: %lu Hz\n",
 223               __func__, *rate);
 224
 225         return 0;
 226
 227 err_rate:
 228         clk_disable(&priv->clk);
 229         clk_free(&priv->clk);
 230
 231         return -EINVAL;
 232 }
 233
 234 static int dw_spi_reset(struct udevice *bus)
 235 {
 236         int ret;
 237         struct dw_spi_priv *priv = dev_get_priv(bus);
 238
 239         ret = reset_get_bulk(bus, &priv->resets);
 240         if (ret) {
 241                 /*
 242                  * Return 0 if error due to !CONFIG_DM_RESET and reset
 243                  * DT property is not present.
 244                  */
 245                 if (ret == -ENOENT || ret == -ENOTSUPP)
 246                         return 0;
 247
 248                 dev_warn(bus, "Can't get reset: %d\n", ret);
 249                 return ret;
 250         }
 251
 252         ret = reset_deassert_bulk(&priv->resets);
 253         if (ret) {
 254                 reset_release_bulk(&priv->resets);
 255                 dev_err(bus, "Failed to reset: %d\n", ret);
 256                 return ret;
 257         }
 258
 259         return 0;
 260 }
 261
 262 static int dw_spi_probe(struct udevice *bus)
 263 {
 264         struct dw_spi_platdata *plat = dev_get_platdata(bus);
 265         struct dw_spi_priv *priv = dev_get_priv(bus);
 266         int ret;
 267
 268         priv->regs = plat->regs;
 269         priv->freq = plat->frequency;
 270
 271         ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
 272         if (ret)
 273                 return ret;
 274
 275         ret = dw_spi_reset(bus);
 276         if (ret)
 277                 return ret;
 278
 279         /* Currently only bits_per_word == 8 supported */
 280         priv->bits_per_word = 8;
 281
 282         priv->tmode = 0; /* Tx & Rx */
 283
 284         /* Basic HW init */
 285         spi_hw_init(priv);
 286
 287         return 0;
 288 }
 289
 290 /* Return the max entries we can fill into tx fifo */
 291 static inline u32 tx_max(struct dw_spi_priv *priv)
 292 {
 293         u32 tx_left, tx_room, rxtx_gap;
 294
 295         tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
 296         tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
 297
 298         /*
 299          * Another concern is about the tx/rx mismatch, we
 300          * thought about using (priv->fifo_len - rxflr - txflr) as
 301          * one maximum value for tx, but it doesn't cover the
 302          * data which is out of tx/rx fifo and inside the
 303          * shift registers. So a control from sw point of
 304          * view is taken.
 305          */
 306         rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
 307                 (priv->bits_per_word >> 3);
 308
 309         return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
 310 }
 311
 312 /* Return the max entries we should read out of rx fifo */
 313 static inline u32 rx_max(struct dw_spi_priv *priv)
 314 {
 315         u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
 316
 317         return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
 318 }
 319
 320 static void dw_writer(struct dw_spi_priv *priv)
 321 {
 322         u32 max = tx_max(priv);
 323         u16 txw = 0;
 324
 325         while (max--) {
 326                 /* Set the tx word if the transfer's original "tx" is not null */
 327                 if (priv->tx_end - priv->len) {
 328                         if (priv->bits_per_word == 8)
 329                                 txw = *(u8 *)(priv->tx);
 330                         else
 331                                 txw = *(u16 *)(priv->tx);
 332                 }
 333                 dw_write(priv, DW_SPI_DR, txw);
 334                 debug("%s: tx=0x%02x\n", __func__, txw);
 335                 priv->tx += priv->bits_per_word >> 3;
 336         }
 337 }
 338
 339 static void dw_reader(struct dw_spi_priv *priv)
 340 {
 341         u32 max = rx_max(priv);
 342         u16 rxw;
 343
 344         while (max--) {
 345                 rxw = dw_read(priv, DW_SPI_DR);
 346                 debug("%s: rx=0x%02x\n", __func__, rxw);
 347
 348                 /* Care about rx if the transfer's original "rx" is not null */
 349                 if (priv->rx_end - priv->len) {
 350                         if (priv->bits_per_word == 8)
 351                                 *(u8 *)(priv->rx) = rxw;
 352                         else
 353                                 *(u16 *)(priv->rx) = rxw;
 354                 }
 355                 priv->rx += priv->bits_per_word >> 3;
 356         }
 357 }
 358
 359 static int poll_transfer(struct dw_spi_priv *priv)
 360 {
 361         do {
 362                 dw_writer(priv);
 363                 dw_reader(priv);
 364         } while (priv->rx_end > priv->rx);
 365
 366         return 0;
 367 }
 368
 369 /*
 370  * We define external_cs_manage function as 'weak' as some targets
 371  * (like MSCC Ocelot) don't control the external CS pin using a GPIO
 372  * controller. These SoCs use specific registers to control by
 373  * software the SPI pins (and especially the CS).
 374  */
 375 __weak void external_cs_manage(struct udevice *dev, bool on)
 376 {
 377 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
 378         struct dw_spi_priv *priv = dev_get_priv(dev->parent);
 379
 380         if (!dm_gpio_is_valid(&priv->cs_gpio))
 381                 return;
 382
 383         dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
 384 #endif
 385 }
 386
 387 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 388                        const void *dout, void *din, unsigned long flags)
 389 {
 390         struct udevice *bus = dev->parent;
 391         struct dw_spi_priv *priv = dev_get_priv(bus);
 392         const u8 *tx = dout;
 393         u8 *rx = din;
 394         int ret = 0;
 395         u32 cr0 = 0;
 396         u32 val;
 397         u32 cs;
 398
 399         /* spi core configured to do 8 bit transfers */
 400         if (bitlen % 8) {
 401                 debug("Non byte aligned SPI transfer.\n");
 402                 return -1;
 403         }
 404
 405         /* Start the transaction if necessary. */
 406         if (flags & SPI_XFER_BEGIN)
 407                 external_cs_manage(dev, false);
 408
 409         cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
 410                 (priv->mode << SPI_MODE_OFFSET) |
 411                 (priv->tmode << SPI_TMOD_OFFSET);
 412
 413         if (rx && tx)
 414                 priv->tmode = SPI_TMOD_TR;
 415         else if (rx)
 416                 priv->tmode = SPI_TMOD_RO;
 417         else
 418                 /*
 419                  * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
 420                  * any data which breaks our logic in poll_transfer() above.
 421                  */
 422                 priv->tmode = SPI_TMOD_TR;
 423
 424         cr0 &= ~SPI_TMOD_MASK;
 425         cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
 426
 427         priv->len = bitlen >> 3;
 428         debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
 429
 430         priv->tx = (void *)tx;
 431         priv->tx_end = priv->tx + priv->len;
 432         priv->rx = rx;
 433         priv->rx_end = priv->rx + priv->len;
 434
 435         /* Disable controller before writing control registers */
 436         spi_enable_chip(priv, 0);
 437
 438         debug("%s: cr0=%08x\n", __func__, cr0);
 439         /* Reprogram cr0 only if changed */
 440         if (dw_read(priv, DW_SPI_CTRL0) != cr0)
 441                 dw_write(priv, DW_SPI_CTRL0, cr0);
 442
 443         /*
 444          * Configure the desired SS (slave select 0...3) in the controller
 445          * The DW SPI controller will activate and deactivate this CS
 446          * automatically. So no cs_activate() etc is needed in this driver.
 447          */
 448         cs = spi_chip_select(dev);
 449         dw_write(priv, DW_SPI_SER, 1 << cs);
 450
 451         /* Enable controller after writing control registers */
 452         spi_enable_chip(priv, 1);
 453
 454         /* Start transfer in a polling loop */
 455         ret = poll_transfer(priv);
 456
 457         /*
 458          * Wait for current transmit operation to complete.
 459          * Otherwise if some data still exists in Tx FIFO it can be
 460          * silently flushed, i.e. dropped on disabling of the controller,
 461          * which happens when writing 0 to DW_SPI_SSIENR which happens
 462          * in the beginning of new transfer.
 463          */
 464         if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
 465                                (val & SR_TF_EMPT) && !(val & SR_BUSY),
 466                                RX_TIMEOUT * 1000)) {
 467                 ret = -ETIMEDOUT;
 468         }
 469
 470         /* Stop the transaction if necessary */
 471         if (flags & SPI_XFER_END)
 472                 external_cs_manage(dev, true);
 473
 474         return ret;
 475 }
 476
 477 static int dw_spi_set_speed(struct udevice *bus, uint speed)
 478 {
 479         struct dw_spi_platdata *plat = bus->platdata;
 480         struct dw_spi_priv *priv = dev_get_priv(bus);
 481         u16 clk_div;
 482
 483         if (speed > plat->frequency)
 484                 speed = plat->frequency;
 485
 486         /* Disable controller before writing control registers */
 487         spi_enable_chip(priv, 0);
 488
 489         /* clk_div doesn't support odd number */
 490         clk_div = priv->bus_clk_rate / speed;
 491         clk_div = (clk_div + 1) & 0xfffe;
 492         dw_write(priv, DW_SPI_BAUDR, clk_div);
 493
 494         /* Enable controller after writing control registers */
 495         spi_enable_chip(priv, 1);
 496
 497         priv->freq = speed;
 498         debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
 499               priv->freq, clk_div);
 500
 501         return 0;
 502 }
 503
 504 static int dw_spi_set_mode(struct udevice *bus, uint mode)
 505 {
 506         struct dw_spi_priv *priv = dev_get_priv(bus);
 507
 508         /*
 509          * Can't set mode yet. Since this depends on if rx, tx, or
 510          * rx & tx is requested. So we have to defer this to the
 511          * real transfer function.
 512          */
 513         priv->mode = mode;
 514         debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
 515
 516         return 0;
 517 }
 518
 519 static int dw_spi_remove(struct udevice *bus)
 520 {
 521         struct dw_spi_priv *priv = dev_get_priv(bus);
 522         int ret;
 523
 524         ret = reset_release_bulk(&priv->resets);
 525         if (ret)
 526                 return ret;
 527
 528 #if CONFIG_IS_ENABLED(CLK)
 529         ret = clk_disable(&priv->clk);
 530         if (ret)
 531                 return ret;
 532
 533         ret = clk_free(&priv->clk);
 534         if (ret)
 535                 return ret;
 536 #endif
 537         return 0;
 538 }
 539
 540 static const struct dm_spi_ops dw_spi_ops = {
 541         .xfer           = dw_spi_xfer,
 542         .set_speed      = dw_spi_set_speed,
 543         .set_mode       = dw_spi_set_mode,
 544         /*
 545          * cs_info is not needed, since we require all chip selects to be
 546          * in the device tree explicitly
 547          */
 548 };
 549
 550 static const struct udevice_id dw_spi_ids[] = {
 551         { .compatible = "snps,dw-apb-ssi" },
 552         { }
 553 };
 554
 555 U_BOOT_DRIVER(dw_spi) = {
 556         .name = "dw_spi",
 557         .id = UCLASS_SPI,
 558         .of_match = dw_spi_ids,
 559         .ops = &dw_spi_ops,
 560         .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
 561         .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
 562         .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
 563         .probe = dw_spi_probe,
 564         .remove = dw_spi_remove,
 565 };