drivers/spi/fsl_dspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  * Chao Fu (B44548@freescale.com)
   9  * Haikun Wang (B53464@freescale.com)
  10  */
  11
  12 #include <asm/global_data.h>
  13 #include <linux/math64.h>
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <common.h>
  18 #include <log.h>
  19 #include <spi.h>
  20 #include <malloc.h>
  21 #include <asm/io.h>
  22 #include <fdtdec.h>
  23 #ifndef CONFIG_M68K
  24 #include <asm/arch/clock.h>
  25 #endif
  26 #include <fsl_dspi.h>
  27 #include <linux/bitops.h>
  28 #include <linux/delay.h>
  29 #include <linux/printk.h>
  30 #include <linux/time.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* fsl_dspi_plat flags */
  35 #define DSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  36
  37 /* idle data value */
  38 #define DSPI_IDLE_VAL                   0x0
  39
  40 /* max chipselect signals number */
  41 #define FSL_DSPI_MAX_CHIPSELECT         6
  42
  43 /* default SCK frequency, unit: HZ */
  44 #define FSL_DSPI_DEFAULT_SCK_FREQ       10000000
  45
  46 /* tx/rx data wait timeout value, unit: us */
  47 #define DSPI_TXRX_WAIT_TIMEOUT          1000000
  48
  49 /* CTAR register pre-configure value */
  50 #define DSPI_CTAR_DEFAULT_VALUE         (DSPI_CTAR_TRSZ(7) | \
  51                                         DSPI_CTAR_PCSSCK_1CLK | \
  52                                         DSPI_CTAR_PASC(0) | \
  53                                         DSPI_CTAR_PDT(0) | \
  54                                         DSPI_CTAR_CSSCK(0) | \
  55                                         DSPI_CTAR_ASC(0) | \
  56                                         DSPI_CTAR_DT(0))
  57
  58 /* CTAR register pre-configure mask */
  59 #define DSPI_CTAR_SET_MODE_MASK         (DSPI_CTAR_TRSZ(15) | \
  60                                         DSPI_CTAR_PCSSCK(3) | \
  61                                         DSPI_CTAR_PASC(3) | \
  62                                         DSPI_CTAR_PDT(3) | \
  63                                         DSPI_CTAR_CSSCK(15) | \
  64                                         DSPI_CTAR_ASC(15) | \
  65                                         DSPI_CTAR_DT(15))
  66
  67 /**
  68  * struct fsl_dspi_plat - platform data for Freescale DSPI
  69  *
  70  * @flags: Flags for DSPI DSPI_FLAG_...
  71  * @speed_hz: Default SCK frequency
  72  * @num_chipselect: Number of DSPI chipselect signals
  73  * @regs_addr: Base address of DSPI registers
  74  */
  75 struct fsl_dspi_plat {
  76         uint flags;
  77         uint speed_hz;
  78         uint num_chipselect;
  79         fdt_addr_t regs_addr;
  80 };
  81
  82 /**
  83  * struct fsl_dspi_priv - private data for Freescale DSPI
  84  *
  85  * @flags: Flags for DSPI DSPI_FLAG_...
  86  * @mode: SPI mode to use for slave device (see SPI mode flags)
  87  * @mcr_val: MCR register configure value
  88  * @bus_clk: DSPI input clk frequency
  89  * @speed_hz: Default SCK frequency
  90  * @charbit: How many bits in every transfer
  91  * @num_chipselect: Number of DSPI chipselect signals
  92  * @ctar_val: CTAR register configure value of per chipselect slave device
  93  * @regs: Point to DSPI register structure for I/O access
  94  */
  95 struct fsl_dspi_priv {
  96         uint flags;
  97         uint mode;
  98         uint mcr_val;
  99         uint bus_clk;
 100         uint speed_hz;
 101         uint charbit;
 102         uint num_chipselect;
 103         uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
 104         struct dspi *regs;
 105 };
 106
 107 __weak void cpu_dspi_port_conf(void)
 108 {
 109 }
 110
 111 __weak int cpu_dspi_claim_bus(uint bus, uint cs)
 112 {
 113         return 0;
 114 }
 115
 116 __weak void cpu_dspi_release_bus(uint bus, uint cs)
 117 {
 118 }
 119
 120 static uint dspi_read32(uint flags, uint *addr)
 121 {
 122         return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
 123                 in_be32(addr) : in_le32(addr);
 124 }
 125
 126 static void dspi_write32(uint flags, uint *addr, uint val)
 127 {
 128         flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
 129                 out_be32(addr, val) : out_le32(addr, val);
 130 }
 131
 132 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
 133 {
 134         uint mcr_val;
 135
 136         mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
 137
 138         if (halt)
 139                 mcr_val |= DSPI_MCR_HALT;
 140         else
 141                 mcr_val &= ~DSPI_MCR_HALT;
 142
 143         dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 144 }
 145
 146 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
 147 {
 148         /* halt DSPI module */
 149         dspi_halt(priv, 1);
 150
 151         dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
 152
 153         /* resume module */
 154         dspi_halt(priv, 0);
 155
 156         priv->mcr_val = cfg_val;
 157 }
 158
 159 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
 160                 uint cs, uint state)
 161 {
 162         uint mcr_val;
 163
 164         dspi_halt(priv, 1);
 165
 166         mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
 167         if (state & SPI_CS_HIGH)
 168                 /* CSx inactive state is low */
 169                 mcr_val &= ~DSPI_MCR_PCSIS(cs);
 170         else
 171                 /* CSx inactive state is high */
 172                 mcr_val |= DSPI_MCR_PCSIS(cs);
 173         dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 174
 175         dspi_halt(priv, 0);
 176 }
 177
 178 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
 179                 uint cs, uint mode)
 180 {
 181         uint bus_setup;
 182
 183         bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
 184
 185         bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
 186         bus_setup |= priv->ctar_val[cs];
 187         bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
 188
 189         if (mode & SPI_CPOL)
 190                 bus_setup |= DSPI_CTAR_CPOL;
 191         if (mode & SPI_CPHA)
 192                 bus_setup |= DSPI_CTAR_CPHA;
 193         if (mode & SPI_LSB_FIRST)
 194                 bus_setup |= DSPI_CTAR_LSBFE;
 195
 196         dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
 197
 198         priv->charbit =
 199                 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
 200                   DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
 201
 202         return 0;
 203 }
 204
 205 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
 206 {
 207         uint mcr_val;
 208
 209         dspi_halt(priv, 1);
 210         mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
 211         /* flush RX and TX FIFO */
 212         mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 213         dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 214         dspi_halt(priv, 0);
 215 }
 216
 217 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
 218 {
 219         int timeout = DSPI_TXRX_WAIT_TIMEOUT;
 220
 221         /* wait for empty entries in TXFIFO or timeout */
 222         while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
 223                         timeout--)
 224                 udelay(1);
 225
 226         if (timeout >= 0)
 227                 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
 228         else
 229                 debug("dspi_tx: waiting timeout!\n");
 230 }
 231
 232 static u16 dspi_rx(struct fsl_dspi_priv *priv)
 233 {
 234         int timeout = DSPI_TXRX_WAIT_TIMEOUT;
 235
 236         /* wait for valid entries in RXFIFO or timeout */
 237         while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
 238                         timeout--)
 239                 udelay(1);
 240
 241         if (timeout >= 0)
 242                 return (u16)DSPI_RFR_RXDATA(
 243                                 dspi_read32(priv->flags, &priv->regs->rfr));
 244         else {
 245                 debug("dspi_rx: waiting timeout!\n");
 246                 return (u16)(~0);
 247         }
 248 }
 249
 250 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
 251                 const void *dout, void *din, unsigned long flags)
 252 {
 253         u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
 254         u8 *spi_rd = NULL, *spi_wr = NULL;
 255         static u32 ctrl;
 256         uint len = bitlen >> 3;
 257
 258         if (priv->charbit == 16) {
 259                 bitlen >>= 1;
 260                 spi_wr16 = (u16 *)dout;
 261                 spi_rd16 = (u16 *)din;
 262         } else {
 263                 spi_wr = (u8 *)dout;
 264                 spi_rd = (u8 *)din;
 265         }
 266
 267         if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
 268                 ctrl |= DSPI_TFR_CONT;
 269
 270         ctrl = ctrl & DSPI_TFR_CONT;
 271         ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
 272
 273         if (len > 1) {
 274                 int tmp_len = len - 1;
 275                 while (tmp_len--) {
 276                         if ((dout != NULL) && (din != NULL)) {
 277                                 if (priv->charbit == 16) {
 278                                         dspi_tx(priv, ctrl, *spi_wr16++);
 279                                         *spi_rd16++ = dspi_rx(priv);
 280                                 }
 281                                 else {
 282                                         dspi_tx(priv, ctrl, *spi_wr++);
 283                                         *spi_rd++ = dspi_rx(priv);
 284                                 }
 285                         }
 286
 287                         else if (dout != NULL) {
 288                                 if (priv->charbit == 16)
 289                                         dspi_tx(priv, ctrl, *spi_wr16++);
 290                                 else
 291                                         dspi_tx(priv, ctrl, *spi_wr++);
 292                                 dspi_rx(priv);
 293                         }
 294
 295                         else if (din != NULL) {
 296                                 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
 297                                 if (priv->charbit == 16)
 298                                         *spi_rd16++ = dspi_rx(priv);
 299                                 else
 300                                         *spi_rd++ = dspi_rx(priv);
 301                         }
 302                 }
 303
 304                 len = 1;        /* remaining byte */
 305         }
 306
 307         if ((flags & SPI_XFER_END) == SPI_XFER_END)
 308                 ctrl &= ~DSPI_TFR_CONT;
 309
 310         if (len) {
 311                 if ((dout != NULL) && (din != NULL)) {
 312                         if (priv->charbit == 16) {
 313                                 dspi_tx(priv, ctrl, *spi_wr16++);
 314                                 *spi_rd16++ = dspi_rx(priv);
 315                         }
 316                         else {
 317                                 dspi_tx(priv, ctrl, *spi_wr++);
 318                                 *spi_rd++ = dspi_rx(priv);
 319                         }
 320                 }
 321
 322                 else if (dout != NULL) {
 323                         if (priv->charbit == 16)
 324                                 dspi_tx(priv, ctrl, *spi_wr16);
 325                         else
 326                                 dspi_tx(priv, ctrl, *spi_wr);
 327                         dspi_rx(priv);
 328                 }
 329
 330                 else if (din != NULL) {
 331                         dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
 332                         if (priv->charbit == 16)
 333                                 *spi_rd16 = dspi_rx(priv);
 334                         else
 335                                 *spi_rd = dspi_rx(priv);
 336                 }
 337         } else {
 338                 /* dummy read */
 339                 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
 340                 dspi_rx(priv);
 341         }
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * Calculate the divide value between input clk frequency and expected SCK frequency
 348  * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
 349  * Dbr: use default value 0
 350  *
 351  * @pbr: return Baud Rate Prescaler value
 352  * @br: return Baud Rate Scaler value
 353  * @speed_hz: expected SCK frequency
 354  * @clkrate: input clk frequency
 355  */
 356 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
 357                 int speed_hz, uint clkrate)
 358 {
 359         /* Valid baud rate pre-scaler values */
 360         int pbr_tbl[4] = {2, 3, 5, 7};
 361         int brs[16] = {2, 4, 6, 8,
 362                 16, 32, 64, 128,
 363                 256, 512, 1024, 2048,
 364                 4096, 8192, 16384, 32768};
 365         int temp, i = 0, j = 0;
 366
 367         temp = clkrate / speed_hz;
 368
 369         for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
 370                 for (j = 0; j < ARRAY_SIZE(brs); j++) {
 371                         if (pbr_tbl[i] * brs[j] >= temp) {
 372                                 *pbr = i;
 373                                 *br = j;
 374                                 return 0;
 375                         }
 376                 }
 377
 378         debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
 379         debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
 380
 381         *pbr = ARRAY_SIZE(pbr_tbl) - 1;
 382         *br =  ARRAY_SIZE(brs) - 1;
 383         return -EINVAL;
 384 }
 385
 386 static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
 387                            unsigned long clkrate)
 388 {
 389         int scale_needed, scale, minscale = INT_MAX;
 390         int pscale_tbl[4] = {1, 3, 5, 7};
 391         u32 remainder;
 392         int i, j;
 393
 394         scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
 395                                    &remainder);
 396         if (remainder)
 397                 scale_needed++;
 398
 399         for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
 400                 for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
 401                         scale = pscale_tbl[i] * (2 << j);
 402                         if (scale >= scale_needed) {
 403                                 if (scale < minscale) {
 404                                         minscale = scale;
 405                                         *psc = i;
 406                                         *sc = j;
 407                                 }
 408                                 break;
 409                         }
 410                 }
 411
 412         if (minscale == INT_MAX) {
 413                 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
 414                         delay_ns, clkrate);
 415                 *psc = ARRAY_SIZE(pscale_tbl) - 1;
 416                 *sc = DSPI_CTAR_SCALE_BITS;
 417         }
 418 }
 419
 420 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
 421 {
 422         int ret;
 423         uint bus_setup;
 424         int best_i, best_j, bus_clk;
 425
 426         bus_clk = priv->bus_clk;
 427
 428         debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
 429               speed, bus_clk);
 430
 431         bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
 432         bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
 433
 434         ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
 435         if (ret) {
 436                 speed = priv->speed_hz;
 437                 debug("DSPI set_speed use default SCK rate %u.\n", speed);
 438                 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
 439         }
 440
 441         bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
 442         dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
 443
 444         priv->speed_hz = speed;
 445
 446         return 0;
 447 }
 448
 449 static int fsl_dspi_child_pre_probe(struct udevice *dev)
 450 {
 451         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 452         struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
 453         u32 cs_sck_delay = 0, sck_cs_delay = 0;
 454         unsigned char pcssck = 0, cssck = 0;
 455         unsigned char pasc = 0, asc = 0;
 456
 457         if (slave_plat->cs >= priv->num_chipselect) {
 458                 debug("DSPI invalid chipselect number %d(max %d)!\n",
 459                       slave_plat->cs, priv->num_chipselect - 1);
 460                 return -EINVAL;
 461         }
 462
 463         ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
 464                         &cs_sck_delay);
 465         ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
 466                         &sck_cs_delay);
 467
 468         /* Set PCS to SCK delay scale values */
 469         ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
 470
 471         /* Set After SCK delay scale values */
 472         ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
 473
 474         priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
 475                                          DSPI_CTAR_PCSSCK(pcssck) |
 476                                          DSPI_CTAR_PASC(pasc);
 477
 478         debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
 479               slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
 480
 481         return 0;
 482 }
 483
 484 static int fsl_dspi_probe(struct udevice *bus)
 485 {
 486         struct fsl_dspi_plat *plat = dev_get_plat(bus);
 487         struct fsl_dspi_priv *priv = dev_get_priv(bus);
 488         struct dm_spi_bus *dm_spi_bus;
 489         uint mcr_cfg_val;
 490
 491         dm_spi_bus = dev_get_uclass_priv(bus);
 492
 493         /* cpu special pin muxing configure */
 494         cpu_dspi_port_conf();
 495
 496         /* get input clk frequency */
 497         priv->regs = (struct dspi *)plat->regs_addr;
 498         priv->flags = plat->flags;
 499 #ifdef CONFIG_M68K
 500         priv->bus_clk = gd->bus_clk;
 501 #else
 502         priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
 503 #endif
 504         priv->num_chipselect = plat->num_chipselect;
 505         priv->speed_hz = plat->speed_hz;
 506         /* frame data length in bits, default 8bits */
 507         priv->charbit = 8;
 508
 509         dm_spi_bus->max_hz = plat->speed_hz;
 510
 511         /* default: all CS signals inactive state is high */
 512         mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
 513                 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
 514         fsl_dspi_init_mcr(priv, mcr_cfg_val);
 515
 516         debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
 517
 518         return 0;
 519 }
 520
 521 static int fsl_dspi_claim_bus(struct udevice *dev)
 522 {
 523         uint sr_val;
 524         struct fsl_dspi_priv *priv;
 525         struct udevice *bus = dev->parent;
 526         struct dm_spi_slave_plat *slave_plat =
 527                 dev_get_parent_plat(dev);
 528
 529         priv = dev_get_priv(bus);
 530
 531         /* processor special preparation work */
 532         cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);
 533
 534         /* configure transfer mode */
 535         fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
 536
 537         /* configure active state of CSX */
 538         fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
 539                                      priv->mode);
 540
 541         fsl_dspi_clr_fifo(priv);
 542
 543         /* check module TX and RX status */
 544         sr_val = dspi_read32(priv->flags, &priv->regs->sr);
 545         if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
 546                 debug("DSPI RX/TX not ready!\n");
 547                 return -EIO;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int fsl_dspi_release_bus(struct udevice *dev)
 554 {
 555         struct udevice *bus = dev->parent;
 556         struct fsl_dspi_priv *priv = dev_get_priv(bus);
 557         struct dm_spi_slave_plat *slave_plat =
 558                 dev_get_parent_plat(dev);
 559
 560         /* halt module */
 561         dspi_halt(priv, 1);
 562
 563         /* processor special release work */
 564         cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);
 565
 566         return 0;
 567 }
 568
 569 /**
 570  * This function doesn't do anything except help with debugging
 571  */
 572 static int fsl_dspi_bind(struct udevice *bus)
 573 {
 574         debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
 575         return 0;
 576 }
 577
 578 static int fsl_dspi_of_to_plat(struct udevice *bus)
 579 {
 580         fdt_addr_t addr;
 581         struct fsl_dspi_plat *plat = dev_get_plat(bus);
 582         const void *blob = gd->fdt_blob;
 583         int node = dev_of_offset(bus);
 584
 585         if (fdtdec_get_bool(blob, node, "big-endian"))
 586                 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
 587
 588         plat->num_chipselect = fdtdec_get_int(blob, node,
 589                                               "spi-num-chipselects",
 590                                               FSL_DSPI_MAX_CHIPSELECT);
 591
 592         addr = dev_read_addr(bus);
 593         if (addr == FDT_ADDR_T_NONE) {
 594                 debug("DSPI: Can't get base address or size\n");
 595                 return -ENOMEM;
 596         }
 597         plat->regs_addr = addr;
 598
 599         plat->speed_hz = fdtdec_get_int(blob,
 600                         node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
 601
 602         debug("DSPI: regs=%pa, max-frequency=%d, endianness=%s, num-cs=%d\n",
 603               &plat->regs_addr, plat->speed_hz,
 604               plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
 605               plat->num_chipselect);
 606
 607         return 0;
 608 }
 609
 610 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
 611                 const void *dout, void *din, unsigned long flags)
 612 {
 613         struct fsl_dspi_priv *priv;
 614         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 615         struct udevice *bus;
 616
 617         bus = dev->parent;
 618         priv = dev_get_priv(bus);
 619
 620         return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
 621 }
 622
 623 static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
 624 {
 625         struct fsl_dspi_priv *priv = dev_get_priv(bus);
 626
 627         return fsl_dspi_cfg_speed(priv, speed);
 628 }
 629
 630 static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
 631 {
 632         struct fsl_dspi_priv *priv = dev_get_priv(bus);
 633
 634         debug("DSPI set_mode: mode 0x%x.\n", mode);
 635
 636         /*
 637          * We store some chipselect special configure value in priv->ctar_val,
 638          * and we can't get the correct chipselect number here,
 639          * so just store mode value.
 640          * Do really configuration when claim_bus.
 641          */
 642         priv->mode = mode;
 643
 644         return 0;
 645 }
 646
 647 static const struct dm_spi_ops fsl_dspi_ops = {
 648         .claim_bus      = fsl_dspi_claim_bus,
 649         .release_bus    = fsl_dspi_release_bus,
 650         .xfer           = fsl_dspi_xfer,
 651         .set_speed      = fsl_dspi_set_speed,
 652         .set_mode       = fsl_dspi_set_mode,
 653 };
 654
 655 static const struct udevice_id fsl_dspi_ids[] = {
 656         { .compatible = "fsl,vf610-dspi" },
 657         { .compatible = "fsl,ls1021a-v1.0-dspi" },
 658         { }
 659 };
 660
 661 U_BOOT_DRIVER(fsl_dspi) = {
 662         .name   = "fsl_dspi",
 663         .id     = UCLASS_SPI,
 664         .of_match = fsl_dspi_ids,
 665         .ops    = &fsl_dspi_ops,
 666         .of_to_plat = fsl_dspi_of_to_plat,
 667         .plat_auto      = sizeof(struct fsl_dspi_plat),
 668         .priv_auto      = sizeof(struct fsl_dspi_priv),
 669         .probe  = fsl_dspi_probe,
 670         .child_pre_probe = fsl_dspi_child_pre_probe,
 671         .bind = fsl_dspi_bind,
 672 };