3 * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
4 * Kuo-Jung Su <dantesu@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compat.h>
15 #ifndef CONFIG_FTSSP010_BASE_LIST
16 #define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
19 #ifndef CONFIG_FTSSP010_GPIO_BASE
20 #define CONFIG_FTSSP010_GPIO_BASE 0
23 #ifndef CONFIG_FTSSP010_GPIO_LIST
24 #define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
27 #ifndef CONFIG_FTSSP010_CLOCK
28 #define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP");
31 #ifndef CONFIG_FTSSP010_TIMEOUT
32 #define CONFIG_FTSSP010_TIMEOUT 100
35 /* FTSSP010 chip registers */
36 struct ftssp010_regs
{
37 uint32_t cr
[3];/* control register */
38 uint32_t sr
; /* status register */
39 uint32_t icr
; /* interrupt control register */
40 uint32_t isr
; /* interrupt status register */
41 uint32_t dr
; /* data register */
43 uint32_t revr
; /* revision register */
44 uint32_t fear
; /* feature register */
47 /* Control Register 0 */
48 #define CR0_FFMT_MASK (7 << 12)
49 #define CR0_FFMT_SSP (0 << 12)
50 #define CR0_FFMT_SPI (1 << 12)
51 #define CR0_FFMT_MICROWIRE (2 << 12)
52 #define CR0_FFMT_I2S (3 << 12)
53 #define CR0_FFMT_AC97 (4 << 12)
54 #define CR0_FLASH (1 << 11)
55 #define CR0_FSDIST(x) (((x) & 0x03) << 8)
56 #define CR0_LOOP (1 << 7) /* loopback mode */
57 #define CR0_LSB (1 << 6) /* LSB */
58 #define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */
59 #define CR0_FSJUSTIFY (1 << 4)
60 #define CR0_OPM_SLAVE (0 << 2)
61 #define CR0_OPM_MASTER (3 << 2)
62 #define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */
63 #define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */
64 #define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */
65 #define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */
66 #define CR0_SCLKPO (1 << 1) /* clock polarity */
67 #define CR0_SCLKPH (1 << 0) /* clock phase */
69 /* Control Register 1 */
70 #define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */
71 #define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */
72 #define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */
74 /* Control Register 2 */
75 #define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */
76 #define CR2_FS (1 << 9) /* CS/FS signal level */
77 #define CR2_TXEN (1 << 8) /* tx enable */
78 #define CR2_RXEN (1 << 7) /* rx enable */
79 #define CR2_RESET (1 << 6) /* chip reset */
80 #define CR2_TXFC (1 << 3) /* tx fifo Clear */
81 #define CR2_RXFC (1 << 2) /* rx fifo Clear */
82 #define CR2_TXDOE (1 << 1) /* tx data output enable */
83 #define CR2_EN (1 << 0) /* chip enable */
86 #define SR_RFF (1 << 0) /* rx fifo full */
87 #define SR_TFNF (1 << 1) /* tx fifo not full */
88 #define SR_BUSY (1 << 2) /* chip busy */
89 #define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */
90 #define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
92 /* Feature Register */
93 #define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */
94 #define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */
95 #define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
96 #define FEAR_AC97 (1 << 24)
97 #define FEAR_I2S (1 << 25)
98 #define FEAR_SPI_MWR (1 << 26)
99 #define FEAR_SSP (1 << 27)
100 #define FEAR_SPDIF (1 << 28)
102 /* FTGPIO010 chip registers */
103 struct ftgpio010_regs
{
104 uint32_t out
; /* 0x00: Data Output */
105 uint32_t in
; /* 0x04: Data Input */
106 uint32_t dir
; /* 0x08: Direction */
107 uint32_t bypass
; /* 0x0c: Bypass */
108 uint32_t set
; /* 0x10: Data Set */
109 uint32_t clr
; /* 0x14: Data Clear */
110 uint32_t pull_up
; /* 0x18: Pull-Up Enabled */
111 uint32_t pull_st
; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
114 struct ftssp010_gpio
{
115 struct ftgpio010_regs
*regs
;
119 struct ftssp010_spi
{
120 struct spi_slave slave
;
121 struct ftssp010_gpio gpio
;
122 struct ftssp010_regs
*regs
;
131 static inline struct ftssp010_spi
*to_ftssp010_spi(struct spi_slave
*slave
)
133 return container_of(slave
, struct ftssp010_spi
, slave
);
136 static int get_spi_chip(int bus
, struct ftssp010_spi
*chip
)
138 uint32_t fear
, base
[] = CONFIG_FTSSP010_BASE_LIST
;
140 if (bus
>= ARRAY_SIZE(base
) || !base
[bus
])
143 chip
->regs
= (struct ftssp010_regs
*)base
[bus
];
145 chip
->revision
= readl(&chip
->regs
->revr
);
147 fear
= readl(&chip
->regs
->fear
);
148 chip
->fifo
= min_t(uint32_t, FEAR_TFSZ(fear
), FEAR_RFSZ(fear
));
153 static int get_spi_gpio(int bus
, struct ftssp010_gpio
*chip
)
155 uint32_t base
[] = CONFIG_FTSSP010_GPIO_LIST
;
157 if (bus
>= ARRAY_SIZE(base
) || !base
[bus
])
160 chip
->regs
= (struct ftgpio010_regs
*)(base
[bus
] & 0xfff00000);
161 chip
->pin
= base
[bus
] & 0x1f;
163 /* make it an output pin */
164 setbits_le32(&chip
->regs
->dir
, 1 << chip
->pin
);
169 static int ftssp010_wait(struct ftssp010_spi
*chip
)
171 struct ftssp010_regs
*regs
= chip
->regs
;
174 /* wait until device idle */
175 for (t
= get_timer(0); get_timer(t
) < CONFIG_FTSSP010_TIMEOUT
; ) {
176 if (!(readl(®s
->sr
) & SR_BUSY
))
180 puts("ftspi010: busy timeout\n");
185 static int ftssp010_wait_tx(struct ftssp010_spi
*chip
)
187 struct ftssp010_regs
*regs
= chip
->regs
;
190 /* wait until tx fifo not full */
191 for (t
= get_timer(0); get_timer(t
) < CONFIG_FTSSP010_TIMEOUT
; ) {
192 if (readl(®s
->sr
) & SR_TFNF
)
196 puts("ftssp010: tx timeout\n");
201 static int ftssp010_wait_rx(struct ftssp010_spi
*chip
)
203 struct ftssp010_regs
*regs
= chip
->regs
;
206 /* wait until rx fifo not empty */
207 for (t
= get_timer(0); get_timer(t
) < CONFIG_FTSSP010_TIMEOUT
; ) {
208 if (SR_RFVE(readl(®s
->sr
)))
212 puts("ftssp010: rx timeout\n");
217 static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi
*chip
,
218 const void *tx_buf
, void *rx_buf
, int len
, uint flags
)
220 struct ftssp010_regs
*regs
= chip
->regs
;
221 const uint8_t *txb
= tx_buf
;
222 uint8_t *rxb
= rx_buf
;
225 int i
, depth
= min(chip
->fifo
>> 2, len
);
229 for (i
= 0; i
< depth
; ++i
) {
230 ftssp010_wait_tx(chip
);
231 writel(*txb
++, ®s
->dr
);
233 xmsk
|= CR2_TXEN
| CR2_TXDOE
;
234 if ((readl(®s
->cr
[2]) & xmsk
) != xmsk
)
235 setbits_le32(®s
->cr
[2], xmsk
);
239 if ((readl(®s
->cr
[2]) & xmsk
) != xmsk
)
240 setbits_le32(®s
->cr
[2], xmsk
);
241 for (i
= 0; i
< depth
; ++i
) {
242 ftssp010_wait_rx(chip
);
243 *rxb
++ = (uint8_t)readl(®s
->dr
);
253 static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi
*chip
,
254 const void *tx_buf
, void *rx_buf
, int len
, uint flags
)
256 struct ftssp010_regs
*regs
= chip
->regs
;
257 const uint8_t *txb
= tx_buf
;
258 uint8_t *rxb
= rx_buf
;
261 int i
, depth
= min(chip
->fifo
>> 2, len
);
264 for (i
= 0; i
< depth
; ++i
) {
265 ftssp010_wait_tx(chip
);
266 writel(txb
? (*txb
++) : 0, ®s
->dr
);
268 for (i
= 0; i
< depth
; ++i
) {
269 ftssp010_wait_rx(chip
);
270 tmp
= readl(®s
->dr
);
272 *rxb
++ = (uint8_t)tmp
;
281 static void ftssp010_cs_set(struct ftssp010_spi
*chip
, int high
)
283 struct ftssp010_regs
*regs
= chip
->regs
;
284 struct ftssp010_gpio
*gpio
= &chip
->gpio
;
287 /* cs pull high/low */
288 if (chip
->revision
>= 0x11900) {
289 mask
= CR2_CS(chip
->slave
.cs
) | (high
? CR2_FS
: 0);
290 writel(mask
, ®s
->cr
[2]);
291 } else if (gpio
->regs
) {
292 mask
= 1 << gpio
->pin
;
294 writel(mask
, &gpio
->regs
->set
);
296 writel(mask
, &gpio
->regs
->clr
);
299 /* extra delay for signal propagation */
304 * Determine if a SPI chipselect is valid.
305 * This function is provided by the board if the low-level SPI driver
306 * needs it to determine if a given chipselect is actually valid.
308 * Returns: 1 if bus:cs identifies a valid chip on this board, 0
311 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
313 struct ftssp010_spi chip
;
315 if (get_spi_chip(bus
, &chip
))
320 else if ((cs
< 4) && (chip
.revision
>= 0x11900))
327 * Activate a SPI chipselect.
328 * This function is provided by the board code when using a driver
329 * that can't control its chipselects automatically (e.g.
330 * common/soft_spi.c). When called, it should activate the chip select
331 * to the device identified by "slave".
333 void spi_cs_activate(struct spi_slave
*slave
)
335 struct ftssp010_spi
*chip
= to_ftssp010_spi(slave
);
336 struct ftssp010_regs
*regs
= chip
->regs
;
339 if (chip
->mode
& SPI_CS_HIGH
)
340 ftssp010_cs_set(chip
, 1);
342 ftssp010_cs_set(chip
, 0);
344 /* chip enable + fifo clear */
345 setbits_le32(®s
->cr
[2], CR2_EN
| CR2_TXFC
| CR2_RXFC
);
349 * Deactivate a SPI chipselect.
350 * This function is provided by the board code when using a driver
351 * that can't control its chipselects automatically (e.g.
352 * common/soft_spi.c). When called, it should deactivate the chip
353 * select to the device identified by "slave".
355 void spi_cs_deactivate(struct spi_slave
*slave
)
357 struct ftssp010_spi
*chip
= to_ftssp010_spi(slave
);
359 /* wait until chip idle */
363 if (chip
->mode
& SPI_CS_HIGH
)
364 ftssp010_cs_set(chip
, 0);
366 ftssp010_cs_set(chip
, 1);
374 struct spi_slave
*spi_setup_slave(uint bus
, uint cs
, uint max_hz
, uint mode
)
376 struct ftssp010_spi
*chip
;
378 if (mode
& SPI_3WIRE
) {
379 puts("ftssp010: can't do 3-wire\n");
383 if (mode
& SPI_SLAVE
) {
384 puts("ftssp010: can't do slave mode\n");
388 if (mode
& SPI_PREAMBLE
) {
389 puts("ftssp010: can't skip preamble bytes\n");
393 if (!spi_cs_is_valid(bus
, cs
)) {
394 puts("ftssp010: invalid (bus, cs)\n");
398 chip
= spi_alloc_slave(struct ftssp010_spi
, bus
, cs
);
402 if (get_spi_chip(bus
, chip
))
405 if (chip
->revision
< 0x11900 && get_spi_gpio(bus
, &chip
->gpio
)) {
406 puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
407 "controlled by tx engine which is not synced with rx engine,\n"
408 "so the clock & cs might be shutdown before rx engine\n"
409 "finishs its jobs.\n"
410 "If possible, please add a dedicated gpio for it.\n");
414 chip
->clk
= CONFIG_FTSSP010_CLOCK
;
417 while (chip
->div
< 0xffff) {
418 if ((chip
->clk
/ (2 * chip
->div
)) <= max_hz
)
423 chip
->speed
= chip
->clk
/ (2 * chip
->div
);
432 void spi_free_slave(struct spi_slave
*slave
)
437 int spi_claim_bus(struct spi_slave
*slave
)
439 struct ftssp010_spi
*chip
= to_ftssp010_spi(slave
);
440 struct ftssp010_regs
*regs
= chip
->regs
;
442 writel(CR1_SDL(8) | CR1_DIV(chip
->div
), ®s
->cr
[1]);
444 if (chip
->revision
>= 0x11900) {
445 writel(CR0_OPM_MASTER
| CR0_FFMT_SPI
| CR0_FSPO
| CR0_FLASH
,
447 writel(CR2_TXFC
| CR2_RXFC
,
450 writel(CR0_OPM_MASTER
| CR0_FFMT_SPI
| CR0_FSPO
,
452 writel(CR2_TXFC
| CR2_RXFC
| CR2_EN
| CR2_TXDOE
,
456 if (chip
->mode
& SPI_LOOP
)
457 setbits_le32(®s
->cr
[0], CR0_LOOP
);
459 if (chip
->mode
& SPI_CPOL
)
460 setbits_le32(®s
->cr
[0], CR0_SCLKPO
);
462 if (chip
->mode
& SPI_CPHA
)
463 setbits_le32(®s
->cr
[0], CR0_SCLKPH
);
465 spi_cs_deactivate(slave
);
470 void spi_release_bus(struct spi_slave
*slave
)
472 struct ftssp010_spi
*chip
= to_ftssp010_spi(slave
);
473 struct ftssp010_regs
*regs
= chip
->regs
;
475 writel(0, ®s
->cr
[2]);
478 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
,
479 const void *dout
, void *din
, unsigned long flags
)
481 struct ftssp010_spi
*chip
= to_ftssp010_spi(slave
);
482 uint32_t len
= bitlen
>> 3;
484 if (flags
& SPI_XFER_BEGIN
)
485 spi_cs_activate(slave
);
487 if (chip
->revision
>= 0x11900)
488 ftssp010_spi_work_transfer_v2(chip
, dout
, din
, len
, flags
);
490 ftssp010_spi_work_transfer_v1(chip
, dout
, din
, len
, flags
);
492 if (flags
& SPI_XFER_END
)
493 spi_cs_deactivate(slave
);