2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
21 DECLARE_GLOBAL_DATA_PTR
;
24 #define debug_trace(fmt, args...) debug(fmt, ##args)
26 #define debug_trace(x, args...)
29 static u8
ich_readb(struct ich_spi_priv
*priv
, int reg
)
31 u8 value
= readb(priv
->base
+ reg
);
33 debug_trace("read %2.2x from %4.4x\n", value
, reg
);
38 static u16
ich_readw(struct ich_spi_priv
*priv
, int reg
)
40 u16 value
= readw(priv
->base
+ reg
);
42 debug_trace("read %4.4x from %4.4x\n", value
, reg
);
47 static u32
ich_readl(struct ich_spi_priv
*priv
, int reg
)
49 u32 value
= readl(priv
->base
+ reg
);
51 debug_trace("read %8.8x from %4.4x\n", value
, reg
);
56 static void ich_writeb(struct ich_spi_priv
*priv
, u8 value
, int reg
)
58 writeb(value
, priv
->base
+ reg
);
59 debug_trace("wrote %2.2x to %4.4x\n", value
, reg
);
62 static void ich_writew(struct ich_spi_priv
*priv
, u16 value
, int reg
)
64 writew(value
, priv
->base
+ reg
);
65 debug_trace("wrote %4.4x to %4.4x\n", value
, reg
);
68 static void ich_writel(struct ich_spi_priv
*priv
, u32 value
, int reg
)
70 writel(value
, priv
->base
+ reg
);
71 debug_trace("wrote %8.8x to %4.4x\n", value
, reg
);
74 static void write_reg(struct ich_spi_priv
*priv
, const void *value
,
75 int dest_reg
, uint32_t size
)
77 memcpy_toio(priv
->base
+ dest_reg
, value
, size
);
80 static void read_reg(struct ich_spi_priv
*priv
, int src_reg
, void *value
,
83 memcpy_fromio(value
, priv
->base
+ src_reg
, size
);
86 static void ich_set_bbar(struct ich_spi_priv
*ctlr
, uint32_t minaddr
)
88 const uint32_t bbar_mask
= 0x00ffff00;
92 ichspi_bbar
= ich_readl(ctlr
, ctlr
->bbar
) & ~bbar_mask
;
93 ichspi_bbar
|= minaddr
;
94 ich_writel(ctlr
, ichspi_bbar
, ctlr
->bbar
);
97 /* @return 1 if the SPI flash supports the 33MHz speed */
98 static int ich9_can_do_33mhz(struct udevice
*dev
)
102 /* Observe SPI Descriptor Component Section 0 */
103 dm_pci_write_config32(dev
->parent
, 0xb0, 0x1000);
105 /* Extract the Write/Erase SPI Frequency from descriptor */
106 dm_pci_read_config32(dev
->parent
, 0xb4, &fdod
);
108 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
109 speed
= (fdod
>> 21) & 7;
114 static int ich_init_controller(struct udevice
*dev
,
115 struct ich_spi_platdata
*plat
,
116 struct ich_spi_priv
*ctlr
)
121 /* SBASE is similar */
122 pch_get_spi_base(dev
->parent
, &sbase_addr
);
123 sbase
= (void *)sbase_addr
;
124 debug("%s: sbase=%p\n", __func__
, sbase
);
126 if (plat
->ich_version
== ICHV_7
) {
127 struct ich7_spi_regs
*ich7_spi
= sbase
;
129 ich7_spi
= (struct ich7_spi_regs
*)sbase
;
130 ctlr
->ichspi_lock
= readw(&ich7_spi
->spis
) & SPIS_LOCK
;
131 ctlr
->opmenu
= offsetof(struct ich7_spi_regs
, opmenu
);
132 ctlr
->menubytes
= sizeof(ich7_spi
->opmenu
);
133 ctlr
->optype
= offsetof(struct ich7_spi_regs
, optype
);
134 ctlr
->addr
= offsetof(struct ich7_spi_regs
, spia
);
135 ctlr
->data
= offsetof(struct ich7_spi_regs
, spid
);
136 ctlr
->databytes
= sizeof(ich7_spi
->spid
);
137 ctlr
->status
= offsetof(struct ich7_spi_regs
, spis
);
138 ctlr
->control
= offsetof(struct ich7_spi_regs
, spic
);
139 ctlr
->bbar
= offsetof(struct ich7_spi_regs
, bbar
);
140 ctlr
->preop
= offsetof(struct ich7_spi_regs
, preop
);
141 ctlr
->base
= ich7_spi
;
142 } else if (plat
->ich_version
== ICHV_9
) {
143 struct ich9_spi_regs
*ich9_spi
= sbase
;
145 ctlr
->ichspi_lock
= readw(&ich9_spi
->hsfs
) & HSFS_FLOCKDN
;
146 ctlr
->opmenu
= offsetof(struct ich9_spi_regs
, opmenu
);
147 ctlr
->menubytes
= sizeof(ich9_spi
->opmenu
);
148 ctlr
->optype
= offsetof(struct ich9_spi_regs
, optype
);
149 ctlr
->addr
= offsetof(struct ich9_spi_regs
, faddr
);
150 ctlr
->data
= offsetof(struct ich9_spi_regs
, fdata
);
151 ctlr
->databytes
= sizeof(ich9_spi
->fdata
);
152 ctlr
->status
= offsetof(struct ich9_spi_regs
, ssfs
);
153 ctlr
->control
= offsetof(struct ich9_spi_regs
, ssfc
);
154 ctlr
->speed
= ctlr
->control
+ 2;
155 ctlr
->bbar
= offsetof(struct ich9_spi_regs
, bbar
);
156 ctlr
->preop
= offsetof(struct ich9_spi_regs
, preop
);
157 ctlr
->bcr
= offsetof(struct ich9_spi_regs
, bcr
);
158 ctlr
->pr
= &ich9_spi
->pr
[0];
159 ctlr
->base
= ich9_spi
;
161 debug("ICH SPI: Unrecognised ICH version %d\n",
166 /* Work out the maximum speed we can support */
167 ctlr
->max_speed
= 20000000;
168 if (plat
->ich_version
== ICHV_9
&& ich9_can_do_33mhz(dev
))
169 ctlr
->max_speed
= 33000000;
170 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
171 plat
->ich_version
, ctlr
->base
, ctlr
->max_speed
);
173 ich_set_bbar(ctlr
, 0);
178 static inline void spi_use_out(struct spi_trans
*trans
, unsigned bytes
)
181 trans
->bytesout
-= bytes
;
184 static inline void spi_use_in(struct spi_trans
*trans
, unsigned bytes
)
187 trans
->bytesin
-= bytes
;
190 static void spi_setup_type(struct spi_trans
*trans
, int data_bytes
)
194 /* Try to guess spi type from read/write sizes */
195 if (trans
->bytesin
== 0) {
196 if (trans
->bytesout
+ data_bytes
> 4)
198 * If bytesin = 0 and bytesout > 4, we presume this is
199 * a write data operation, which is accompanied by an
202 trans
->type
= SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
;
204 trans
->type
= SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
;
208 if (trans
->bytesout
== 1) { /* and bytesin is > 0 */
209 trans
->type
= SPI_OPCODE_TYPE_READ_NO_ADDRESS
;
213 if (trans
->bytesout
== 4) /* and bytesin is > 0 */
214 trans
->type
= SPI_OPCODE_TYPE_READ_WITH_ADDRESS
;
216 /* Fast read command is called with 5 bytes instead of 4 */
217 if (trans
->out
[0] == SPI_OPCODE_FAST_READ
&& trans
->bytesout
== 5) {
218 trans
->type
= SPI_OPCODE_TYPE_READ_WITH_ADDRESS
;
223 static int spi_setup_opcode(struct ich_spi_priv
*ctlr
, struct spi_trans
*trans
)
226 uint8_t opmenu
[ctlr
->menubytes
];
228 trans
->opcode
= trans
->out
[0];
229 spi_use_out(trans
, 1);
230 if (!ctlr
->ichspi_lock
) {
231 /* The lock is off, so just use index 0. */
232 ich_writeb(ctlr
, trans
->opcode
, ctlr
->opmenu
);
233 optypes
= ich_readw(ctlr
, ctlr
->optype
);
234 optypes
= (optypes
& 0xfffc) | (trans
->type
& 0x3);
235 ich_writew(ctlr
, optypes
, ctlr
->optype
);
238 /* The lock is on. See if what we need is on the menu. */
240 uint16_t opcode_index
;
242 /* Write Enable is handled as atomic prefix */
243 if (trans
->opcode
== SPI_OPCODE_WREN
)
246 read_reg(ctlr
, ctlr
->opmenu
, opmenu
, sizeof(opmenu
));
247 for (opcode_index
= 0; opcode_index
< ctlr
->menubytes
;
249 if (opmenu
[opcode_index
] == trans
->opcode
)
253 if (opcode_index
== ctlr
->menubytes
) {
254 printf("ICH SPI: Opcode %x not found\n",
259 optypes
= ich_readw(ctlr
, ctlr
->optype
);
260 optype
= (optypes
>> (opcode_index
* 2)) & 0x3;
261 if (trans
->type
== SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
&&
262 optype
== SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
&&
263 trans
->bytesout
>= 3) {
264 /* We guessed wrong earlier. Fix it up. */
265 trans
->type
= optype
;
267 if (optype
!= trans
->type
) {
268 printf("ICH SPI: Transaction doesn't fit type %d\n",
276 static int spi_setup_offset(struct spi_trans
*trans
)
278 /* Separate the SPI address and data */
279 switch (trans
->type
) {
280 case SPI_OPCODE_TYPE_READ_NO_ADDRESS
:
281 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
:
283 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS
:
284 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
:
285 trans
->offset
= ((uint32_t)trans
->out
[0] << 16) |
286 ((uint32_t)trans
->out
[1] << 8) |
287 ((uint32_t)trans
->out
[2] << 0);
288 spi_use_out(trans
, 3);
291 printf("Unrecognized SPI transaction type %#x\n", trans
->type
);
297 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
298 * below is true) or 0. In case the wait was for the bit(s) to set - write
299 * those bits back, which would cause resetting them.
301 * Return the last read status value on success or -1 on failure.
303 static int ich_status_poll(struct ich_spi_priv
*ctlr
, u16 bitmask
,
306 int timeout
= 600000; /* This will result in 6s */
310 status
= ich_readw(ctlr
, ctlr
->status
);
311 if (wait_til_set
^ ((status
& bitmask
) == 0)) {
313 ich_writew(ctlr
, status
& bitmask
,
321 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
326 static int ich_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
327 const void *dout
, void *din
, unsigned long flags
)
329 struct udevice
*bus
= dev_get_parent(dev
);
330 struct ich_spi_platdata
*plat
= dev_get_platdata(bus
);
331 struct ich_spi_priv
*ctlr
= dev_get_priv(bus
);
333 int16_t opcode_index
;
336 int bytes
= bitlen
/ 8;
337 struct spi_trans
*trans
= &ctlr
->trans
;
338 unsigned type
= flags
& (SPI_XFER_BEGIN
| SPI_XFER_END
);
342 /* We don't support writing partial bytes */
344 debug("ICH SPI: Accessing partial bytes not supported\n");
345 return -EPROTONOSUPPORT
;
348 /* An empty end transaction can be ignored */
349 if (type
== SPI_XFER_END
&& !dout
&& !din
)
352 if (type
& SPI_XFER_BEGIN
)
353 memset(trans
, '\0', sizeof(*trans
));
355 /* Dp we need to come back later to finish it? */
356 if (dout
&& type
== SPI_XFER_BEGIN
) {
357 if (bytes
> ICH_MAX_CMD_LEN
) {
358 debug("ICH SPI: Command length limit exceeded\n");
361 memcpy(trans
->cmd
, dout
, bytes
);
362 trans
->cmd_len
= bytes
;
363 debug_trace("ICH SPI: Saved %d bytes\n", bytes
);
368 * We process a 'middle' spi_xfer() call, which has no
369 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
370 * an end. We therefore repeat the command. This is because ICH
371 * seems to have no support for this, or because interest (in digging
372 * out the details and creating a special case in the code) is low.
374 if (trans
->cmd_len
) {
375 trans
->out
= trans
->cmd
;
376 trans
->bytesout
= trans
->cmd_len
;
378 debug_trace("ICH SPI: Using %d bytes\n", trans
->cmd_len
);
381 trans
->bytesout
= dout
? bytes
: 0;
385 trans
->bytesin
= din
? bytes
: 0;
387 /* There has to always at least be an opcode */
388 if (!trans
->bytesout
) {
389 debug("ICH SPI: No opcode for transfer\n");
393 ret
= ich_status_poll(ctlr
, SPIS_SCIP
, 0);
397 if (plat
->ich_version
== ICHV_7
)
398 ich_writew(ctlr
, SPIS_CDS
| SPIS_FCERR
, ctlr
->status
);
400 ich_writeb(ctlr
, SPIS_CDS
| SPIS_FCERR
, ctlr
->status
);
402 spi_setup_type(trans
, using_cmd
? bytes
: 0);
403 opcode_index
= spi_setup_opcode(ctlr
, trans
);
404 if (opcode_index
< 0)
406 with_address
= spi_setup_offset(trans
);
407 if (with_address
< 0)
410 if (trans
->opcode
== SPI_OPCODE_WREN
) {
412 * Treat Write Enable as Atomic Pre-Op if possible
413 * in order to prevent the Management Engine from
414 * issuing a transaction between WREN and DATA.
416 if (!ctlr
->ichspi_lock
)
417 ich_writew(ctlr
, trans
->opcode
, ctlr
->preop
);
421 if (ctlr
->speed
&& ctlr
->max_speed
>= 33000000) {
424 byte
= ich_readb(ctlr
, ctlr
->speed
);
425 if (ctlr
->cur_speed
>= 33000000)
426 byte
|= SSFC_SCF_33MHZ
;
428 byte
&= ~SSFC_SCF_33MHZ
;
429 ich_writeb(ctlr
, byte
, ctlr
->speed
);
432 /* See if we have used up the command data */
433 if (using_cmd
&& dout
&& bytes
) {
435 trans
->bytesout
= bytes
;
436 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes
);
439 /* Preset control fields */
440 control
= ich_readw(ctlr
, ctlr
->control
);
441 control
&= ~SSFC_RESERVED
;
442 control
= SPIC_SCGO
| ((opcode_index
& 0x07) << 4);
444 /* Issue atomic preop cycle if needed */
445 if (ich_readw(ctlr
, ctlr
->preop
))
448 if (!trans
->bytesout
&& !trans
->bytesin
) {
449 /* SPI addresses are 24 bit only */
451 ich_writel(ctlr
, trans
->offset
& 0x00FFFFFF,
455 * This is a 'no data' command (like Write Enable), its
456 * bitesout size was 1, decremented to zero while executing
457 * spi_setup_opcode() above. Tell the chip to send the
460 ich_writew(ctlr
, control
, ctlr
->control
);
462 /* wait for the result */
463 status
= ich_status_poll(ctlr
, SPIS_CDS
| SPIS_FCERR
, 1);
467 if (status
& SPIS_FCERR
) {
468 debug("ICH SPI: Command transaction error\n");
476 * Check if this is a write command atempting to transfer more bytes
477 * than the controller can handle. Iterations for writes are not
478 * supported here because each SPI write command needs to be preceded
479 * and followed by other SPI commands, and this sequence is controlled
480 * by the SPI chip driver.
482 if (trans
->bytesout
> ctlr
->databytes
) {
483 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
488 * Read or write up to databytes bytes at a time until everything has
491 while (trans
->bytesout
|| trans
->bytesin
) {
492 uint32_t data_length
;
494 /* SPI addresses are 24 bit only */
495 ich_writel(ctlr
, trans
->offset
& 0x00FFFFFF, ctlr
->addr
);
498 data_length
= min(trans
->bytesout
, ctlr
->databytes
);
500 data_length
= min(trans
->bytesin
, ctlr
->databytes
);
502 /* Program data into FDATA0 to N */
503 if (trans
->bytesout
) {
504 write_reg(ctlr
, trans
->out
, ctlr
->data
, data_length
);
505 spi_use_out(trans
, data_length
);
507 trans
->offset
+= data_length
;
510 /* Add proper control fields' values */
511 control
&= ~((ctlr
->databytes
- 1) << 8);
513 control
|= (data_length
- 1) << 8;
516 ich_writew(ctlr
, control
, ctlr
->control
);
518 /* Wait for Cycle Done Status or Flash Cycle Error */
519 status
= ich_status_poll(ctlr
, SPIS_CDS
| SPIS_FCERR
, 1);
523 if (status
& SPIS_FCERR
) {
524 debug("ICH SPI: Data transaction error %x\n", status
);
528 if (trans
->bytesin
) {
529 read_reg(ctlr
, ctlr
->data
, trans
->in
, data_length
);
530 spi_use_in(trans
, data_length
);
532 trans
->offset
+= data_length
;
536 /* Clear atomic preop now that xfer is done */
537 ich_writew(ctlr
, 0, ctlr
->preop
);
543 * This uses the SPI controller from the Intel Cougar Point and Panther Point
544 * PCH to write-protect portions of the SPI flash until reboot. The changes
545 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
548 int spi_write_protect_region(struct udevice
*dev
, uint32_t lower_limit
,
549 uint32_t length
, int hint
)
551 struct udevice
*bus
= dev
->parent
;
552 struct ich_spi_priv
*ctlr
= dev_get_priv(bus
);
554 uint32_t upper_limit
;
557 printf("%s: operation not supported on this chipset\n",
563 lower_limit
> (0xFFFFFFFFUL
- length
) + 1 ||
564 hint
< 0 || hint
> 4) {
565 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__
,
566 lower_limit
, length
, hint
);
570 upper_limit
= lower_limit
+ length
- 1;
573 * Determine bits to write, as follows:
574 * 31 Write-protection enable (includes erase operation)
576 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
577 * 15 Read-protection enable
579 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
581 tmplong
= 0x80000000 |
582 ((upper_limit
& 0x01fff000) << 4) |
583 ((lower_limit
& 0x01fff000) >> 12);
585 printf("%s: writing 0x%08x to %p\n", __func__
, tmplong
,
587 ctlr
->pr
[hint
] = tmplong
;
592 static int ich_spi_probe(struct udevice
*dev
)
594 struct ich_spi_platdata
*plat
= dev_get_platdata(dev
);
595 struct ich_spi_priv
*priv
= dev_get_priv(dev
);
599 ret
= ich_init_controller(dev
, plat
, priv
);
602 /* Disable the BIOS write protect so write commands are allowed */
603 ret
= pch_set_spi_protect(dev
->parent
, false);
604 if (ret
== -ENOSYS
) {
605 bios_cntl
= ich_readb(priv
, priv
->bcr
);
606 bios_cntl
&= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
607 bios_cntl
|= 1; /* Write Protect Disable (WPD) */
608 ich_writeb(priv
, bios_cntl
, priv
->bcr
);
610 debug("%s: Failed to disable write-protect: err=%d\n",
615 priv
->cur_speed
= priv
->max_speed
;
620 static int ich_spi_remove(struct udevice
*bus
)
622 struct ich_spi_priv
*ctlr
= dev_get_priv(bus
);
625 * Configure SPI controller so that the Linux MTD driver can fully
626 * access the SPI NOR chip
628 ich_writew(ctlr
, SPI_OPPREFIX
, ctlr
->preop
);
629 ich_writew(ctlr
, SPI_OPTYPE
, ctlr
->optype
);
630 ich_writel(ctlr
, SPI_OPMENU_LOWER
, ctlr
->opmenu
);
631 ich_writel(ctlr
, SPI_OPMENU_UPPER
, ctlr
->opmenu
+ sizeof(u32
));
636 static int ich_spi_set_speed(struct udevice
*bus
, uint speed
)
638 struct ich_spi_priv
*priv
= dev_get_priv(bus
);
640 priv
->cur_speed
= speed
;
645 static int ich_spi_set_mode(struct udevice
*bus
, uint mode
)
647 debug("%s: mode=%d\n", __func__
, mode
);
652 static int ich_spi_child_pre_probe(struct udevice
*dev
)
654 struct udevice
*bus
= dev_get_parent(dev
);
655 struct ich_spi_platdata
*plat
= dev_get_platdata(bus
);
656 struct ich_spi_priv
*priv
= dev_get_priv(bus
);
657 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
660 * Yes this controller can only write a small number of bytes at
661 * once! The limit is typically 64 bytes.
663 slave
->max_write_size
= priv
->databytes
;
665 * ICH 7 SPI controller only supports array read command
666 * and byte program command for SST flash
668 if (plat
->ich_version
== ICHV_7
)
669 slave
->mode
= SPI_RX_SLOW
| SPI_TX_BYTE
;
674 static int ich_spi_ofdata_to_platdata(struct udevice
*dev
)
676 struct ich_spi_platdata
*plat
= dev_get_platdata(dev
);
677 int node
= dev_of_offset(dev
);
680 ret
= fdt_node_check_compatible(gd
->fdt_blob
, node
, "intel,ich7-spi");
682 plat
->ich_version
= ICHV_7
;
684 ret
= fdt_node_check_compatible(gd
->fdt_blob
, node
,
687 plat
->ich_version
= ICHV_9
;
693 static const struct dm_spi_ops ich_spi_ops
= {
694 .xfer
= ich_spi_xfer
,
695 .set_speed
= ich_spi_set_speed
,
696 .set_mode
= ich_spi_set_mode
,
698 * cs_info is not needed, since we require all chip selects to be
699 * in the device tree explicitly
703 static const struct udevice_id ich_spi_ids
[] = {
704 { .compatible
= "intel,ich7-spi" },
705 { .compatible
= "intel,ich9-spi" },
709 U_BOOT_DRIVER(ich_spi
) = {
712 .of_match
= ich_spi_ids
,
714 .ofdata_to_platdata
= ich_spi_ofdata_to_platdata
,
715 .platdata_auto_alloc_size
= sizeof(struct ich_spi_platdata
),
716 .priv_auto_alloc_size
= sizeof(struct ich_spi_priv
),
717 .child_pre_probe
= ich_spi_child_pre_probe
,
718 .probe
= ich_spi_probe
,
719 .remove
= ich_spi_remove
,
720 .flags
= DM_FLAG_OS_PREPARE
,