2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
21 DECLARE_GLOBAL_DATA_PTR
;
24 #define debug_trace(fmt, args...) debug(fmt, ##args)
26 #define debug_trace(x, args...)
29 static u8
ich_readb(struct ich_spi_priv
*priv
, int reg
)
31 u8 value
= readb(priv
->base
+ reg
);
33 debug_trace("read %2.2x from %4.4x\n", value
, reg
);
38 static u16
ich_readw(struct ich_spi_priv
*priv
, int reg
)
40 u16 value
= readw(priv
->base
+ reg
);
42 debug_trace("read %4.4x from %4.4x\n", value
, reg
);
47 static u32
ich_readl(struct ich_spi_priv
*priv
, int reg
)
49 u32 value
= readl(priv
->base
+ reg
);
51 debug_trace("read %8.8x from %4.4x\n", value
, reg
);
56 static void ich_writeb(struct ich_spi_priv
*priv
, u8 value
, int reg
)
58 writeb(value
, priv
->base
+ reg
);
59 debug_trace("wrote %2.2x to %4.4x\n", value
, reg
);
62 static void ich_writew(struct ich_spi_priv
*priv
, u16 value
, int reg
)
64 writew(value
, priv
->base
+ reg
);
65 debug_trace("wrote %4.4x to %4.4x\n", value
, reg
);
68 static void ich_writel(struct ich_spi_priv
*priv
, u32 value
, int reg
)
70 writel(value
, priv
->base
+ reg
);
71 debug_trace("wrote %8.8x to %4.4x\n", value
, reg
);
74 static void write_reg(struct ich_spi_priv
*priv
, const void *value
,
75 int dest_reg
, uint32_t size
)
77 memcpy_toio(priv
->base
+ dest_reg
, value
, size
);
80 static void read_reg(struct ich_spi_priv
*priv
, int src_reg
, void *value
,
83 memcpy_fromio(value
, priv
->base
+ src_reg
, size
);
86 static void ich_set_bbar(struct ich_spi_priv
*ctlr
, uint32_t minaddr
)
88 const uint32_t bbar_mask
= 0x00ffff00;
92 ichspi_bbar
= ich_readl(ctlr
, ctlr
->bbar
) & ~bbar_mask
;
93 ichspi_bbar
|= minaddr
;
94 ich_writel(ctlr
, ichspi_bbar
, ctlr
->bbar
);
97 /* @return 1 if the SPI flash supports the 33MHz speed */
98 static int ich9_can_do_33mhz(struct udevice
*dev
)
102 /* Observe SPI Descriptor Component Section 0 */
103 dm_pci_write_config32(dev
->parent
, 0xb0, 0x1000);
105 /* Extract the Write/Erase SPI Frequency from descriptor */
106 dm_pci_read_config32(dev
->parent
, 0xb4, &fdod
);
108 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
109 speed
= (fdod
>> 21) & 7;
114 static int ich_init_controller(struct udevice
*dev
,
115 struct ich_spi_platdata
*plat
,
116 struct ich_spi_priv
*ctlr
)
121 /* SBASE is similar */
122 pch_get_spi_base(dev
->parent
, &sbase_addr
);
123 sbase
= (void *)sbase_addr
;
124 debug("%s: sbase=%p\n", __func__
, sbase
);
126 if (plat
->ich_version
== ICHV_7
) {
127 struct ich7_spi_regs
*ich7_spi
= sbase
;
129 ctlr
->opmenu
= offsetof(struct ich7_spi_regs
, opmenu
);
130 ctlr
->menubytes
= sizeof(ich7_spi
->opmenu
);
131 ctlr
->optype
= offsetof(struct ich7_spi_regs
, optype
);
132 ctlr
->addr
= offsetof(struct ich7_spi_regs
, spia
);
133 ctlr
->data
= offsetof(struct ich7_spi_regs
, spid
);
134 ctlr
->databytes
= sizeof(ich7_spi
->spid
);
135 ctlr
->status
= offsetof(struct ich7_spi_regs
, spis
);
136 ctlr
->control
= offsetof(struct ich7_spi_regs
, spic
);
137 ctlr
->bbar
= offsetof(struct ich7_spi_regs
, bbar
);
138 ctlr
->preop
= offsetof(struct ich7_spi_regs
, preop
);
139 ctlr
->base
= ich7_spi
;
140 } else if (plat
->ich_version
== ICHV_9
) {
141 struct ich9_spi_regs
*ich9_spi
= sbase
;
143 ctlr
->opmenu
= offsetof(struct ich9_spi_regs
, opmenu
);
144 ctlr
->menubytes
= sizeof(ich9_spi
->opmenu
);
145 ctlr
->optype
= offsetof(struct ich9_spi_regs
, optype
);
146 ctlr
->addr
= offsetof(struct ich9_spi_regs
, faddr
);
147 ctlr
->data
= offsetof(struct ich9_spi_regs
, fdata
);
148 ctlr
->databytes
= sizeof(ich9_spi
->fdata
);
149 ctlr
->status
= offsetof(struct ich9_spi_regs
, ssfs
);
150 ctlr
->control
= offsetof(struct ich9_spi_regs
, ssfc
);
151 ctlr
->speed
= ctlr
->control
+ 2;
152 ctlr
->bbar
= offsetof(struct ich9_spi_regs
, bbar
);
153 ctlr
->preop
= offsetof(struct ich9_spi_regs
, preop
);
154 ctlr
->bcr
= offsetof(struct ich9_spi_regs
, bcr
);
155 ctlr
->pr
= &ich9_spi
->pr
[0];
156 ctlr
->base
= ich9_spi
;
158 debug("ICH SPI: Unrecognised ICH version %d\n",
163 /* Work out the maximum speed we can support */
164 ctlr
->max_speed
= 20000000;
165 if (plat
->ich_version
== ICHV_9
&& ich9_can_do_33mhz(dev
))
166 ctlr
->max_speed
= 33000000;
167 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
168 plat
->ich_version
, ctlr
->base
, ctlr
->max_speed
);
170 ich_set_bbar(ctlr
, 0);
175 static inline void spi_use_out(struct spi_trans
*trans
, unsigned bytes
)
178 trans
->bytesout
-= bytes
;
181 static inline void spi_use_in(struct spi_trans
*trans
, unsigned bytes
)
184 trans
->bytesin
-= bytes
;
187 static void spi_lock_down(struct ich_spi_platdata
*plat
, void *sbase
)
189 if (plat
->ich_version
== ICHV_7
) {
190 struct ich7_spi_regs
*ich7_spi
= sbase
;
192 setbits_le16(&ich7_spi
->spis
, SPIS_LOCK
);
193 } else if (plat
->ich_version
== ICHV_9
) {
194 struct ich9_spi_regs
*ich9_spi
= sbase
;
196 setbits_le16(&ich9_spi
->hsfs
, HSFS_FLOCKDN
);
200 static bool spi_lock_status(struct ich_spi_platdata
*plat
, void *sbase
)
204 if (plat
->ich_version
== ICHV_7
) {
205 struct ich7_spi_regs
*ich7_spi
= sbase
;
207 lock
= readw(&ich7_spi
->spis
) & SPIS_LOCK
;
208 } else if (plat
->ich_version
== ICHV_9
) {
209 struct ich9_spi_regs
*ich9_spi
= sbase
;
211 lock
= readw(&ich9_spi
->hsfs
) & HSFS_FLOCKDN
;
217 static void spi_setup_type(struct spi_trans
*trans
, int data_bytes
)
221 /* Try to guess spi type from read/write sizes */
222 if (trans
->bytesin
== 0) {
223 if (trans
->bytesout
+ data_bytes
> 4)
225 * If bytesin = 0 and bytesout > 4, we presume this is
226 * a write data operation, which is accompanied by an
229 trans
->type
= SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
;
231 trans
->type
= SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
;
235 if (trans
->bytesout
== 1) { /* and bytesin is > 0 */
236 trans
->type
= SPI_OPCODE_TYPE_READ_NO_ADDRESS
;
240 if (trans
->bytesout
== 4) /* and bytesin is > 0 */
241 trans
->type
= SPI_OPCODE_TYPE_READ_WITH_ADDRESS
;
243 /* Fast read command is called with 5 bytes instead of 4 */
244 if (trans
->out
[0] == SPI_OPCODE_FAST_READ
&& trans
->bytesout
== 5) {
245 trans
->type
= SPI_OPCODE_TYPE_READ_WITH_ADDRESS
;
250 static int spi_setup_opcode(struct ich_spi_priv
*ctlr
, struct spi_trans
*trans
,
254 uint8_t opmenu
[ctlr
->menubytes
];
256 trans
->opcode
= trans
->out
[0];
257 spi_use_out(trans
, 1);
259 /* The lock is off, so just use index 0. */
260 ich_writeb(ctlr
, trans
->opcode
, ctlr
->opmenu
);
261 optypes
= ich_readw(ctlr
, ctlr
->optype
);
262 optypes
= (optypes
& 0xfffc) | (trans
->type
& 0x3);
263 ich_writew(ctlr
, optypes
, ctlr
->optype
);
266 /* The lock is on. See if what we need is on the menu. */
268 uint16_t opcode_index
;
270 /* Write Enable is handled as atomic prefix */
271 if (trans
->opcode
== SPI_OPCODE_WREN
)
274 read_reg(ctlr
, ctlr
->opmenu
, opmenu
, sizeof(opmenu
));
275 for (opcode_index
= 0; opcode_index
< ctlr
->menubytes
;
277 if (opmenu
[opcode_index
] == trans
->opcode
)
281 if (opcode_index
== ctlr
->menubytes
) {
282 printf("ICH SPI: Opcode %x not found\n",
287 optypes
= ich_readw(ctlr
, ctlr
->optype
);
288 optype
= (optypes
>> (opcode_index
* 2)) & 0x3;
289 if (trans
->type
== SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
&&
290 optype
== SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
&&
291 trans
->bytesout
>= 3) {
292 /* We guessed wrong earlier. Fix it up. */
293 trans
->type
= optype
;
295 if (optype
!= trans
->type
) {
296 printf("ICH SPI: Transaction doesn't fit type %d\n",
304 static int spi_setup_offset(struct spi_trans
*trans
)
306 /* Separate the SPI address and data */
307 switch (trans
->type
) {
308 case SPI_OPCODE_TYPE_READ_NO_ADDRESS
:
309 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
:
311 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS
:
312 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
:
313 trans
->offset
= ((uint32_t)trans
->out
[0] << 16) |
314 ((uint32_t)trans
->out
[1] << 8) |
315 ((uint32_t)trans
->out
[2] << 0);
316 spi_use_out(trans
, 3);
319 printf("Unrecognized SPI transaction type %#x\n", trans
->type
);
325 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
326 * below is true) or 0. In case the wait was for the bit(s) to set - write
327 * those bits back, which would cause resetting them.
329 * Return the last read status value on success or -1 on failure.
331 static int ich_status_poll(struct ich_spi_priv
*ctlr
, u16 bitmask
,
334 int timeout
= 600000; /* This will result in 6s */
338 status
= ich_readw(ctlr
, ctlr
->status
);
339 if (wait_til_set
^ ((status
& bitmask
) == 0)) {
341 ich_writew(ctlr
, status
& bitmask
,
349 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
354 void ich_spi_config_opcode(struct udevice
*dev
)
356 struct ich_spi_priv
*ctlr
= dev_get_priv(dev
);
359 * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
360 * to prevent accidental or intentional writes. Before they get
361 * locked down, these registers should be initialized properly.
363 ich_writew(ctlr
, SPI_OPPREFIX
, ctlr
->preop
);
364 ich_writew(ctlr
, SPI_OPTYPE
, ctlr
->optype
);
365 ich_writel(ctlr
, SPI_OPMENU_LOWER
, ctlr
->opmenu
);
366 ich_writel(ctlr
, SPI_OPMENU_UPPER
, ctlr
->opmenu
+ sizeof(u32
));
369 static int ich_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
370 const void *dout
, void *din
, unsigned long flags
)
372 struct udevice
*bus
= dev_get_parent(dev
);
373 struct ich_spi_platdata
*plat
= dev_get_platdata(bus
);
374 struct ich_spi_priv
*ctlr
= dev_get_priv(bus
);
376 int16_t opcode_index
;
379 int bytes
= bitlen
/ 8;
380 struct spi_trans
*trans
= &ctlr
->trans
;
381 unsigned type
= flags
& (SPI_XFER_BEGIN
| SPI_XFER_END
);
383 bool lock
= spi_lock_status(plat
, ctlr
->base
);
386 /* We don't support writing partial bytes */
388 debug("ICH SPI: Accessing partial bytes not supported\n");
389 return -EPROTONOSUPPORT
;
392 /* An empty end transaction can be ignored */
393 if (type
== SPI_XFER_END
&& !dout
&& !din
)
396 if (type
& SPI_XFER_BEGIN
)
397 memset(trans
, '\0', sizeof(*trans
));
399 /* Dp we need to come back later to finish it? */
400 if (dout
&& type
== SPI_XFER_BEGIN
) {
401 if (bytes
> ICH_MAX_CMD_LEN
) {
402 debug("ICH SPI: Command length limit exceeded\n");
405 memcpy(trans
->cmd
, dout
, bytes
);
406 trans
->cmd_len
= bytes
;
407 debug_trace("ICH SPI: Saved %d bytes\n", bytes
);
412 * We process a 'middle' spi_xfer() call, which has no
413 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
414 * an end. We therefore repeat the command. This is because ICH
415 * seems to have no support for this, or because interest (in digging
416 * out the details and creating a special case in the code) is low.
418 if (trans
->cmd_len
) {
419 trans
->out
= trans
->cmd
;
420 trans
->bytesout
= trans
->cmd_len
;
422 debug_trace("ICH SPI: Using %d bytes\n", trans
->cmd_len
);
425 trans
->bytesout
= dout
? bytes
: 0;
429 trans
->bytesin
= din
? bytes
: 0;
431 /* There has to always at least be an opcode */
432 if (!trans
->bytesout
) {
433 debug("ICH SPI: No opcode for transfer\n");
437 ret
= ich_status_poll(ctlr
, SPIS_SCIP
, 0);
441 if (plat
->ich_version
== ICHV_7
)
442 ich_writew(ctlr
, SPIS_CDS
| SPIS_FCERR
, ctlr
->status
);
444 ich_writeb(ctlr
, SPIS_CDS
| SPIS_FCERR
, ctlr
->status
);
446 spi_setup_type(trans
, using_cmd
? bytes
: 0);
447 opcode_index
= spi_setup_opcode(ctlr
, trans
, lock
);
448 if (opcode_index
< 0)
450 with_address
= spi_setup_offset(trans
);
451 if (with_address
< 0)
454 if (trans
->opcode
== SPI_OPCODE_WREN
) {
456 * Treat Write Enable as Atomic Pre-Op if possible
457 * in order to prevent the Management Engine from
458 * issuing a transaction between WREN and DATA.
461 ich_writew(ctlr
, trans
->opcode
, ctlr
->preop
);
465 if (ctlr
->speed
&& ctlr
->max_speed
>= 33000000) {
468 byte
= ich_readb(ctlr
, ctlr
->speed
);
469 if (ctlr
->cur_speed
>= 33000000)
470 byte
|= SSFC_SCF_33MHZ
;
472 byte
&= ~SSFC_SCF_33MHZ
;
473 ich_writeb(ctlr
, byte
, ctlr
->speed
);
476 /* See if we have used up the command data */
477 if (using_cmd
&& dout
&& bytes
) {
479 trans
->bytesout
= bytes
;
480 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes
);
483 /* Preset control fields */
484 control
= SPIC_SCGO
| ((opcode_index
& 0x07) << 4);
486 /* Issue atomic preop cycle if needed */
487 if (ich_readw(ctlr
, ctlr
->preop
))
490 if (!trans
->bytesout
&& !trans
->bytesin
) {
491 /* SPI addresses are 24 bit only */
493 ich_writel(ctlr
, trans
->offset
& 0x00FFFFFF,
497 * This is a 'no data' command (like Write Enable), its
498 * bitesout size was 1, decremented to zero while executing
499 * spi_setup_opcode() above. Tell the chip to send the
502 ich_writew(ctlr
, control
, ctlr
->control
);
504 /* wait for the result */
505 status
= ich_status_poll(ctlr
, SPIS_CDS
| SPIS_FCERR
, 1);
509 if (status
& SPIS_FCERR
) {
510 debug("ICH SPI: Command transaction error\n");
518 * Check if this is a write command atempting to transfer more bytes
519 * than the controller can handle. Iterations for writes are not
520 * supported here because each SPI write command needs to be preceded
521 * and followed by other SPI commands, and this sequence is controlled
522 * by the SPI chip driver.
524 if (trans
->bytesout
> ctlr
->databytes
) {
525 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
530 * Read or write up to databytes bytes at a time until everything has
533 while (trans
->bytesout
|| trans
->bytesin
) {
534 uint32_t data_length
;
536 /* SPI addresses are 24 bit only */
537 ich_writel(ctlr
, trans
->offset
& 0x00FFFFFF, ctlr
->addr
);
540 data_length
= min(trans
->bytesout
, ctlr
->databytes
);
542 data_length
= min(trans
->bytesin
, ctlr
->databytes
);
544 /* Program data into FDATA0 to N */
545 if (trans
->bytesout
) {
546 write_reg(ctlr
, trans
->out
, ctlr
->data
, data_length
);
547 spi_use_out(trans
, data_length
);
549 trans
->offset
+= data_length
;
552 /* Add proper control fields' values */
553 control
&= ~((ctlr
->databytes
- 1) << 8);
555 control
|= (data_length
- 1) << 8;
558 ich_writew(ctlr
, control
, ctlr
->control
);
560 /* Wait for Cycle Done Status or Flash Cycle Error */
561 status
= ich_status_poll(ctlr
, SPIS_CDS
| SPIS_FCERR
, 1);
565 if (status
& SPIS_FCERR
) {
566 debug("ICH SPI: Data transaction error %x\n", status
);
570 if (trans
->bytesin
) {
571 read_reg(ctlr
, ctlr
->data
, trans
->in
, data_length
);
572 spi_use_in(trans
, data_length
);
574 trans
->offset
+= data_length
;
578 /* Clear atomic preop now that xfer is done */
580 ich_writew(ctlr
, 0, ctlr
->preop
);
585 static int ich_spi_probe(struct udevice
*dev
)
587 struct ich_spi_platdata
*plat
= dev_get_platdata(dev
);
588 struct ich_spi_priv
*priv
= dev_get_priv(dev
);
592 ret
= ich_init_controller(dev
, plat
, priv
);
595 /* Disable the BIOS write protect so write commands are allowed */
596 ret
= pch_set_spi_protect(dev
->parent
, false);
597 if (ret
== -ENOSYS
) {
598 bios_cntl
= ich_readb(priv
, priv
->bcr
);
599 bios_cntl
&= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
600 bios_cntl
|= 1; /* Write Protect Disable (WPD) */
601 ich_writeb(priv
, bios_cntl
, priv
->bcr
);
603 debug("%s: Failed to disable write-protect: err=%d\n",
608 /* Lock down SPI controller settings if required */
609 if (plat
->lockdown
) {
610 ich_spi_config_opcode(dev
);
611 spi_lock_down(plat
, priv
->base
);
614 priv
->cur_speed
= priv
->max_speed
;
619 static int ich_spi_remove(struct udevice
*bus
)
622 * Configure SPI controller so that the Linux MTD driver can fully
623 * access the SPI NOR chip
625 ich_spi_config_opcode(bus
);
630 static int ich_spi_set_speed(struct udevice
*bus
, uint speed
)
632 struct ich_spi_priv
*priv
= dev_get_priv(bus
);
634 priv
->cur_speed
= speed
;
639 static int ich_spi_set_mode(struct udevice
*bus
, uint mode
)
641 debug("%s: mode=%d\n", __func__
, mode
);
646 static int ich_spi_child_pre_probe(struct udevice
*dev
)
648 struct udevice
*bus
= dev_get_parent(dev
);
649 struct ich_spi_platdata
*plat
= dev_get_platdata(bus
);
650 struct ich_spi_priv
*priv
= dev_get_priv(bus
);
651 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
654 * Yes this controller can only write a small number of bytes at
655 * once! The limit is typically 64 bytes.
657 slave
->max_write_size
= priv
->databytes
;
659 * ICH 7 SPI controller only supports array read command
660 * and byte program command for SST flash
662 if (plat
->ich_version
== ICHV_7
)
663 slave
->mode
= SPI_RX_SLOW
| SPI_TX_BYTE
;
668 static int ich_spi_ofdata_to_platdata(struct udevice
*dev
)
670 struct ich_spi_platdata
*plat
= dev_get_platdata(dev
);
671 int node
= dev_of_offset(dev
);
674 ret
= fdt_node_check_compatible(gd
->fdt_blob
, node
, "intel,ich7-spi");
676 plat
->ich_version
= ICHV_7
;
678 ret
= fdt_node_check_compatible(gd
->fdt_blob
, node
,
681 plat
->ich_version
= ICHV_9
;
684 plat
->lockdown
= fdtdec_get_bool(gd
->fdt_blob
, node
,
685 "intel,spi-lock-down");
690 static const struct dm_spi_ops ich_spi_ops
= {
691 .xfer
= ich_spi_xfer
,
692 .set_speed
= ich_spi_set_speed
,
693 .set_mode
= ich_spi_set_mode
,
695 * cs_info is not needed, since we require all chip selects to be
696 * in the device tree explicitly
700 static const struct udevice_id ich_spi_ids
[] = {
701 { .compatible
= "intel,ich7-spi" },
702 { .compatible
= "intel,ich9-spi" },
706 U_BOOT_DRIVER(ich_spi
) = {
709 .of_match
= ich_spi_ids
,
711 .ofdata_to_platdata
= ich_spi_ofdata_to_platdata
,
712 .platdata_auto_alloc_size
= sizeof(struct ich_spi_platdata
),
713 .priv_auto_alloc_size
= sizeof(struct ich_spi_priv
),
714 .child_pre_probe
= ich_spi_child_pre_probe
,
715 .probe
= ich_spi_probe
,
716 .remove
= ich_spi_remove
,
717 .flags
= DM_FLAG_OS_PREPARE
,