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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/spi/ich.h
2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
12 struct ich7_spi_regs
{
24 struct ich9_spi_regs
{
25 uint32_t bfpr
; /* 0x00 */
30 uint32_t fdata
[16]; /* 0x10 */
31 uint32_t frap
; /* 0x50 */
33 uint32_t _reserved1
[3];
34 uint32_t pr
[5]; /* 0x74 */
35 uint32_t _reserved2
[2];
36 uint8_t ssfs
; /* 0x90 */
38 uint16_t preop
; /* 0x94 */
40 uint8_t opmenu
[8]; /* 0x98 */
42 uint8_t _reserved3
[12];
43 uint32_t fdoc
; /* 0xb0 */
45 uint8_t _reserved4
[8];
46 uint32_t afc
; /* 0xc0 */
49 uint8_t _reserved5
[4];
50 uint32_t fpb
; /* 0xd0 */
51 uint8_t _reserved6
[28];
52 uint32_t srdl
; /* 0xf0 */
65 SPIS_RESERVED_MASK
= 0x7ff0,
66 SSFS_RESERVED_MASK
= 0x7fe2
76 SSFC_SCF_MASK
= 0x070000,
77 SSFC_RESERVED
= 0xf80000,
79 /* Mask for speed byte, biuts 23:16 of SSFC */
80 SSFC_SCF_33MHZ
= 0x01,
87 HSFS_BERASE_MASK
= 0x0018,
88 HSFS_BERASE_SHIFT
= 3,
97 HSFC_FCYCLE_MASK
= 0x0006,
98 HSFC_FCYCLE_SHIFT
= 1,
99 HSFC_FDBC_MASK
= 0x3f00,
109 uint8_t cmd
[ICH_MAX_CMD_LEN
];
120 #define SPI_OPCODE_WRSR 0x01
121 #define SPI_OPCODE_PAGE_PROGRAM 0x02
122 #define SPI_OPCODE_READ 0x03
123 #define SPI_OPCODE_WRDIS 0x04
124 #define SPI_OPCODE_RDSR 0x05
125 #define SPI_OPCODE_WREN 0x06
126 #define SPI_OPCODE_FAST_READ 0x0b
127 #define SPI_OPCODE_ERASE_SECT 0x20
128 #define SPI_OPCODE_READ_ID 0x9f
129 #define SPI_OPCODE_ERASE_BLOCK 0xd8
131 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
132 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
133 #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
134 #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
136 #define SPI_OPMENU_0 SPI_OPCODE_WRSR
137 #define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
139 #define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
140 #define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
142 #define SPI_OPMENU_2 SPI_OPCODE_READ
143 #define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
145 #define SPI_OPMENU_3 SPI_OPCODE_RDSR
146 #define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
148 #define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
149 #define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
151 #define SPI_OPMENU_5 SPI_OPCODE_READ_ID
152 #define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
154 #define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
155 #define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
157 #define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
158 #define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
160 #define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
161 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
162 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
163 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
164 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
165 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
166 (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
167 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
168 (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
175 struct ich_spi_platdata
{
176 enum ich_version ich_version
; /* Controller version, 7 or 9 */
177 bool lockdown
; /* lock down controller settings? */
180 struct ich_spi_priv
{
183 void *base
; /* Base of register set */
193 uint32_t *pr
; /* only for ich9 */
194 int speed
; /* pointer to speed control */
195 ulong max_speed
; /* Maximum bus speed in MHz */
196 ulong cur_speed
; /* Current bus speed */
197 struct spi_trans trans
; /* current transaction in progress */