2 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
3 * <nboppuri@trinetcommunication.com>,
4 * <pmpatel@trinetcommunication.com>
5 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
6 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
8 * SPDX-License-Identifier: GPL-2.0+
12 * MPC8xx CPM SPI interface.
14 * Parts of this code are probably not portable and/or specific to
15 * the board which I used for the tests. Please send fixes/complaints
23 #include <linux/ctype.h>
28 #define SPI_EEPROM_WREN 0x06
29 #define SPI_EEPROM_RDSR 0x05
30 #define SPI_EEPROM_READ 0x03
31 #define SPI_EEPROM_WRITE 0x02
33 /* ---------------------------------------------------------------
34 * Offset for initial SPI buffers in DPRAM:
35 * We need a 520 byte scratch DPRAM area to use at an early stage.
36 * It is used between the two initialization calls (spi_init_f()
38 * The value 0xb00 makes it far enough from the start of the data
39 * area (as well as from the stack pointer).
40 * --------------------------------------------------------------- */
41 #ifndef CONFIG_SYS_SPI_INIT_OFFSET
42 #define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
45 #define CPM_SPI_BASE_RX CPM_SPI_BASE
46 #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
48 /* -------------------
50 * ------------------- */
51 ssize_t
spi_xfer(size_t);
53 /* -------------------
55 * ------------------- */
57 #define MAX_BUFFER 0x104
59 /* ----------------------------------------------------------------------
60 * Initially we place the RX and TX buffers at a fixed location in DPRAM!
61 * ---------------------------------------------------------------------- */
63 (uchar
*)&((cpm8xx_t
*)&((immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
)->cp_dpmem
64 [CONFIG_SYS_SPI_INIT_OFFSET
];
66 (uchar
*)&((cpm8xx_t
*)&((immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
)->cp_dpmem
67 [CONFIG_SYS_SPI_INIT_OFFSET
+MAX_BUFFER
];
69 /* **************************************************************************
71 * Function: spi_init_f
73 * Description: Init SPI-Controller (ROM part)
77 * *********************************************************************** */
80 immap_t __iomem
*immr
= (immap_t __iomem
*)CONFIG_SYS_IMMR
;
81 cpm8xx_t __iomem
*cp
= &immr
->im_cpm
;
82 spi_t __iomem
*spi
= (spi_t __iomem
*)&cp
->cp_dparam
[PROFF_SPI
];
83 cbd_t __iomem
*tbdf
, *rbdf
;
85 /* Disable relocation */
86 out_be16(&spi
->spi_rpbase
, 0);
89 /* ------------------------------------------------
90 * Initialize Port B SPI pins -> page 34-8 MPC860UM
91 * (we are only in Master Mode !)
92 * ------------------------------------------------ */
94 /* --------------------------------------------
95 * GPIO or per. Function
96 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
97 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
98 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
99 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
100 * -------------------------------------------- */
101 clrsetbits_be32(&cp
->cp_pbpar
, 0x00000001, 0x0000000E); /* set bits */
103 /* ----------------------------------------------
104 * In/Out or per. Function 0/1
105 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
106 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
107 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
108 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
109 * ---------------------------------------------- */
110 setbits_be32(&cp
->cp_pbdir
, 0x0000000F);
112 /* ----------------------------------------------
113 * open drain or active output
114 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
115 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
116 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
117 * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
118 * ---------------------------------------------- */
120 clrsetbits_be16(&cp
->cp_pbodr
, 0x00000007, 0x00000008);
122 /* Initialize the parameter ram.
123 * We need to make sure many things are initialized to zero
125 out_be32(&spi
->spi_rstate
, 0);
126 out_be32(&spi
->spi_rdp
, 0);
127 out_be16(&spi
->spi_rbptr
, 0);
128 out_be16(&spi
->spi_rbc
, 0);
129 out_be32(&spi
->spi_rxtmp
, 0);
130 out_be32(&spi
->spi_tstate
, 0);
131 out_be32(&spi
->spi_tdp
, 0);
132 out_be16(&spi
->spi_tbptr
, 0);
133 out_be16(&spi
->spi_tbc
, 0);
134 out_be32(&spi
->spi_txtmp
, 0);
137 /* Set up the SPI parameters in the parameter ram */
138 out_be16(&spi
->spi_rbase
, CPM_SPI_BASE_RX
);
139 out_be16(&spi
->spi_tbase
, CPM_SPI_BASE_TX
);
141 /***********IMPORTANT******************/
144 * Setting transmit and receive buffer descriptor pointers
145 * initially to rbase and tbase. Only the microcode patches
146 * documentation talks about initializing this pointer. This
147 * is missing from the sample I2C driver. If you dont
148 * initialize these pointers, the kernel hangs.
150 out_be16(&spi
->spi_rbptr
, CPM_SPI_BASE_RX
);
151 out_be16(&spi
->spi_tbptr
, CPM_SPI_BASE_TX
);
154 /* Init SPI Tx + Rx Parameters */
155 while (in_be16(&cp
->cp_cpcr
) & CPM_CR_FLG
)
158 out_be16(&cp
->cp_cpcr
, mk_cr_cmd(CPM_CR_CH_SPI
, CPM_CR_INIT_TRX
) |
160 while (in_be16(&cp
->cp_cpcr
) & CPM_CR_FLG
)
164 /* Set SDMA configuration register */
165 out_be32(&immr
->im_siu_conf
.sc_sdcr
, 0x0001);
168 /* Set to big endian. */
169 out_8(&spi
->spi_tfcr
, SMC_EB
);
170 out_8(&spi
->spi_rfcr
, SMC_EB
);
173 /* Set maximum receive size. */
174 out_be16(&spi
->spi_mrblr
, MAX_BUFFER
);
177 /* tx and rx buffer descriptors */
178 tbdf
= (cbd_t __iomem
*)&cp
->cp_dpmem
[CPM_SPI_BASE_TX
];
179 rbdf
= (cbd_t __iomem
*)&cp
->cp_dpmem
[CPM_SPI_BASE_RX
];
181 clrbits_be16(&tbdf
->cbd_sc
, BD_SC_READY
);
182 clrbits_be16(&rbdf
->cbd_sc
, BD_SC_EMPTY
);
184 /* Set the bd's rx and tx buffer address pointers */
185 out_be32(&rbdf
->cbd_bufaddr
, (ulong
)rxbuf
);
186 out_be32(&tbdf
->cbd_bufaddr
, (ulong
)txbuf
);
189 out_8(&cp
->cp_spim
, 0); /* Mask all SPI events */
190 out_8(&cp
->cp_spie
, SPI_EMASK
); /* Clear all SPI events */
195 /* **************************************************************************
197 * Function: spi_init_r
199 * Description: Init SPI-Controller (RAM part) -
200 * The malloc engine is ready and we can move our buffers to
205 * *********************************************************************** */
206 void spi_init_r(void)
208 immap_t __iomem
*immr
= (immap_t __iomem
*)CONFIG_SYS_IMMR
;
209 cpm8xx_t __iomem
*cp
= &immr
->im_cpm
;
210 spi_t __iomem
*spi
= (spi_t __iomem
*)&cp
->cp_dparam
[PROFF_SPI
];
211 cbd_t __iomem
*tbdf
, *rbdf
;
213 /* Disable relocation */
214 out_be16(&spi
->spi_rpbase
, 0);
216 /* tx and rx buffer descriptors */
217 tbdf
= (cbd_t __iomem
*)&cp
->cp_dpmem
[CPM_SPI_BASE_TX
];
218 rbdf
= (cbd_t __iomem
*)&cp
->cp_dpmem
[CPM_SPI_BASE_RX
];
220 /* Allocate memory for RX and TX buffers */
221 rxbuf
= (uchar
*)malloc(MAX_BUFFER
);
222 txbuf
= (uchar
*)malloc(MAX_BUFFER
);
224 out_be32(&rbdf
->cbd_bufaddr
, (ulong
)rxbuf
);
225 out_be32(&tbdf
->cbd_bufaddr
, (ulong
)txbuf
);
230 /****************************************************************************
231 * Function: spi_write
232 **************************************************************************** */
233 ssize_t
spi_write(uchar
*addr
, int alen
, uchar
*buffer
, int len
)
237 memset(rxbuf
, 0, MAX_BUFFER
);
238 memset(txbuf
, 0, MAX_BUFFER
);
239 *txbuf
= SPI_EEPROM_WREN
; /* write enable */
241 memcpy(txbuf
, addr
, alen
);
242 *txbuf
= SPI_EEPROM_WRITE
; /* WRITE memory array */
243 memcpy(alen
+ txbuf
, buffer
, len
);
244 spi_xfer(alen
+ len
);
245 /* ignore received data */
246 for (i
= 0; i
< 1000; i
++) {
247 *txbuf
= SPI_EEPROM_RDSR
; /* read status */
255 printf("*** spi_write: Time out while writing!\n");
260 /****************************************************************************
262 **************************************************************************** */
263 ssize_t
spi_read(uchar
*addr
, int alen
, uchar
*buffer
, int len
)
265 memset(rxbuf
, 0, MAX_BUFFER
);
266 memset(txbuf
, 0, MAX_BUFFER
);
267 memcpy(txbuf
, addr
, alen
);
268 *txbuf
= SPI_EEPROM_READ
; /* READ memory array */
271 * There is a bug in 860T (?) that cuts the last byte of input
272 * if we're reading into DPRAM. The solution we choose here is
273 * to always read len+1 bytes (we have one extra byte at the
274 * end of the buffer).
276 spi_xfer(alen
+ len
+ 1);
277 memcpy(buffer
, alen
+ rxbuf
, len
);
282 /****************************************************************************
284 **************************************************************************** */
285 ssize_t
spi_xfer(size_t count
)
287 immap_t __iomem
*immr
= (immap_t __iomem
*)CONFIG_SYS_IMMR
;
288 cpm8xx_t __iomem
*cp
= &immr
->im_cpm
;
289 spi_t __iomem
*spi
= (spi_t __iomem
*)&cp
->cp_dparam
[PROFF_SPI
];
290 cbd_t __iomem
*tbdf
, *rbdf
;
293 /* Disable relocation */
294 out_be16(&spi
->spi_rpbase
, 0);
296 tbdf
= (cbd_t __iomem
*)&cp
->cp_dpmem
[CPM_SPI_BASE_TX
];
297 rbdf
= (cbd_t __iomem
*)&cp
->cp_dpmem
[CPM_SPI_BASE_RX
];
299 /* Set CS for device */
300 clrbits_be32(&cp
->cp_pbdat
, 0x0001);
302 /* Setting tx bd status and data length */
303 out_be16(&tbdf
->cbd_sc
, BD_SC_READY
| BD_SC_LAST
| BD_SC_WRAP
);
304 out_be16(&tbdf
->cbd_datlen
, count
);
306 /* Setting rx bd status and data length */
307 out_be16(&rbdf
->cbd_sc
, BD_SC_EMPTY
| BD_SC_WRAP
);
308 out_be16(&rbdf
->cbd_datlen
, 0); /* rx length has no significance */
310 clrsetbits_be16(&cp
->cp_spmode
, ~SPMODE_LOOP
, SPMODE_REV
| SPMODE_MSTR
|
311 SPMODE_EN
| SPMODE_LEN(8) | SPMODE_PM(0x8));
312 out_8(&cp
->cp_spim
, 0); /* Mask all SPI events */
313 out_8(&cp
->cp_spie
, SPI_EMASK
); /* Clear all SPI events */
315 /* start spi transfer */
316 setbits_8(&cp
->cp_spcom
, SPI_STR
); /* Start transmit */
318 /* --------------------------------
319 * Wait for SPI transmit to get out
320 * or time out (1 second = 1000 ms)
321 * -------------------------------- */
322 for (tm
= 0; tm
< 1000; ++tm
) {
323 if (in_8(&cp
->cp_spie
) & SPI_TXB
) /* Tx Buffer Empty */
325 if ((in_be16(&tbdf
->cbd_sc
) & BD_SC_READY
) == 0)
330 printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
332 /* Clear CS for device */
333 setbits_be32(&cp
->cp_pbdat
, 0x0001);