2 * Copyright (C) 2015 Marvell International Ltd.
4 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
16 DECLARE_GLOBAL_DATA_PTR
;
18 #define MVEBU_SPI_A3700_XFER_RDY BIT(1)
19 #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
20 #define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
21 #define MVEBU_SPI_A3700_CLK_PHA BIT(6)
22 #define MVEBU_SPI_A3700_CLK_POL BIT(7)
23 #define MVEBU_SPI_A3700_FIFO_EN BIT(17)
24 #define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
25 #define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0
26 #define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \
27 (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT)
31 u32 ctrl
; /* 0x10600 */
32 u32 cfg
; /* 0x10604 */
33 u32 dout
; /* 0x10608 */
34 u32 din
; /* 0x1060c */
37 struct mvebu_spi_platdata
{
38 struct spi_reg
*spireg
;
39 unsigned int frequency
;
43 static void spi_cs_activate(struct spi_reg
*reg
, int cs
)
45 setbits_le32(®
->ctrl
, MVEBU_SPI_A3700_SPI_EN_0
<< cs
);
48 static void spi_cs_deactivate(struct spi_reg
*reg
, int cs
)
50 clrbits_le32(®
->ctrl
, MVEBU_SPI_A3700_SPI_EN_0
<< cs
);
54 * spi_legacy_shift_byte() - triggers the real SPI transfer
55 * @bytelen: Indicate how many bytes to transfer.
56 * @dout: Buffer address of what to send.
57 * @din: Buffer address of where to receive.
59 * This function triggers the real SPI transfer in legacy mode. It
60 * will shift out char buffer from @dout, and shift in char buffer to
63 * This function assumes that only one byte is shifted at one time.
64 * However, it is not its responisbility to set the transfer type to
65 * one-byte. Also, it does not guarantee that it will work if transfer
66 * type becomes two-byte. See spi_set_legacy() for details.
68 * In legacy mode, simply write to the SPI_DOUT register will trigger
71 * If @dout == NULL, which means no actual data needs to be sent out,
72 * then the function will shift out 0x00 in order to shift in data.
73 * The XFER_RDY flag is checked every time before accessing SPI_DOUT
74 * and SPI_DIN register.
76 * The number of transfers to be triggerred is decided by @bytelen.
79 * -ETIMEDOUT - XFER_RDY flag timeout
81 static int spi_legacy_shift_byte(struct spi_reg
*reg
, unsigned int bytelen
,
82 const void *dout
, void *din
)
88 /* Use 0x00 as dummy dout */
89 const u8 dummy_dout
= 0x0;
90 u32 pending_dout
= 0x0;
92 /* dout_8: pointer of current dout */
94 /* din_8: pointer of current din */
98 ret
= wait_for_bit(__func__
, ®
->ctrl
,
99 MVEBU_SPI_A3700_XFER_RDY
, true, 100, false);
104 pending_dout
= (u32
)*dout_8
;
106 pending_dout
= (u32
)dummy_dout
;
108 /* Trigger the xfer */
109 writel(pending_dout
, ®
->dout
);
112 ret
= wait_for_bit(__func__
, ®
->ctrl
,
113 MVEBU_SPI_A3700_XFER_RDY
,
118 /* Read what is transferred in */
119 *din_8
= (u8
)readl(®
->din
);
122 /* Don't increment the current pointer if NULL */
134 static int mvebu_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
135 const void *dout
, void *din
, unsigned long flags
)
137 struct udevice
*bus
= dev
->parent
;
138 struct mvebu_spi_platdata
*plat
= dev_get_platdata(bus
);
139 struct spi_reg
*reg
= plat
->spireg
;
140 unsigned int bytelen
;
143 bytelen
= bitlen
/ 8;
146 debug("This is a duplex transfer.\n");
149 if (flags
& SPI_XFER_BEGIN
) {
150 debug("SPI: activate cs.\n");
151 spi_cs_activate(reg
, spi_chip_select(dev
));
154 /* Send and/or receive */
156 ret
= spi_legacy_shift_byte(reg
, bytelen
, dout
, din
);
162 if (flags
& SPI_XFER_END
) {
163 ret
= wait_for_bit(__func__
, ®
->ctrl
,
164 MVEBU_SPI_A3700_XFER_RDY
, true, 100, false);
168 debug("SPI: deactivate cs.\n");
169 spi_cs_deactivate(reg
, spi_chip_select(dev
));
175 static int mvebu_spi_set_speed(struct udevice
*bus
, uint hz
)
177 struct mvebu_spi_platdata
*plat
= dev_get_platdata(bus
);
178 struct spi_reg
*reg
= plat
->spireg
;
181 data
= readl(®
->cfg
);
184 data
&= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK
;
186 /* Calculate Prescaler = (spi_input_freq / spi_max_freq) */
187 if (hz
> plat
->frequency
)
188 hz
= plat
->frequency
;
189 data
|= plat
->clock
/ hz
;
191 writel(data
, ®
->cfg
);
196 static int mvebu_spi_set_mode(struct udevice
*bus
, uint mode
)
198 struct mvebu_spi_platdata
*plat
= dev_get_platdata(bus
);
199 struct spi_reg
*reg
= plat
->spireg
;
203 * 0: Serial interface clock is low when inactive
204 * 1: Serial interface clock is high when inactive
207 setbits_le32(®
->cfg
, MVEBU_SPI_A3700_CLK_POL
);
209 clrbits_le32(®
->cfg
, MVEBU_SPI_A3700_CLK_POL
);
211 setbits_le32(®
->cfg
, MVEBU_SPI_A3700_CLK_PHA
);
213 clrbits_le32(®
->cfg
, MVEBU_SPI_A3700_CLK_PHA
);
218 static int mvebu_spi_probe(struct udevice
*bus
)
220 struct mvebu_spi_platdata
*plat
= dev_get_platdata(bus
);
221 struct spi_reg
*reg
= plat
->spireg
;
226 * Settings SPI controller to be working in legacy mode, which
227 * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
231 /* Flush read/write FIFO */
232 data
= readl(®
->cfg
);
233 writel(data
| MVEBU_SPI_A3700_FIFO_FLUSH
, ®
->cfg
);
234 ret
= wait_for_bit(__func__
, ®
->cfg
, MVEBU_SPI_A3700_FIFO_FLUSH
,
239 /* Disable FIFO mode */
240 data
&= ~MVEBU_SPI_A3700_FIFO_EN
;
242 /* Always shift 1 byte at a time */
243 data
&= ~MVEBU_SPI_A3700_BYTE_LEN
;
245 writel(data
, ®
->cfg
);
250 static int mvebu_spi_ofdata_to_platdata(struct udevice
*bus
)
252 struct mvebu_spi_platdata
*plat
= dev_get_platdata(bus
);
254 plat
->spireg
= (struct spi_reg
*)dev_get_addr(bus
);
258 * Right now, mvebu does not have a clock infrastructure in U-Boot
259 * which should be used to query the input clock to the SPI
260 * controller. Once this clock driver is integrated into U-Boot
261 * it should be used to read the input clock and the DT property
264 plat
->clock
= fdtdec_get_int(gd
->fdt_blob
, bus
->of_offset
,
265 "clock-frequency", 160000);
266 plat
->frequency
= fdtdec_get_int(gd
->fdt_blob
, bus
->of_offset
,
267 "spi-max-frequency", 40000);
272 static const struct dm_spi_ops mvebu_spi_ops
= {
273 .xfer
= mvebu_spi_xfer
,
274 .set_speed
= mvebu_spi_set_speed
,
275 .set_mode
= mvebu_spi_set_mode
,
277 * cs_info is not needed, since we require all chip selects to be
278 * in the device tree explicitly
282 static const struct udevice_id mvebu_spi_ids
[] = {
283 { .compatible
= "marvell,armada-3700-spi" },
287 U_BOOT_DRIVER(mvebu_spi
) = {
290 .of_match
= mvebu_spi_ids
,
291 .ops
= &mvebu_spi_ops
,
292 .ofdata_to_platdata
= mvebu_spi_ofdata_to_platdata
,
293 .platdata_auto_alloc_size
= sizeof(struct mvebu_spi_platdata
),
294 .probe
= mvebu_spi_probe
,