]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/spi/mxc_spi.c
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/errno.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/clock.h>
31 /* i.MX27 has a completely wrong register layout and register definitions in the
32 * datasheet, the correct one is in the Freescale's Linux driver */
34 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
35 "See linux mxc_spi driver from Freescale for details."
38 static unsigned long spi_bases
[] = {
39 MXC_SPI_BASE_ADDRESSES
42 #define OUT MXC_GPIO_DIRECTION_OUT
44 #define reg_read readl
45 #define reg_write(a, v) writel(v, a)
47 struct mxc_spi_slave
{
48 struct spi_slave slave
;
51 #if defined(MXC_ECSPI)
58 static inline struct mxc_spi_slave
*to_mxc_spi_slave(struct spi_slave
*slave
)
60 return container_of(slave
, struct mxc_spi_slave
, slave
);
63 void spi_cs_activate(struct spi_slave
*slave
)
65 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
67 gpio_set_value(mxcs
->gpio
, mxcs
->ss_pol
);
70 void spi_cs_deactivate(struct spi_slave
*slave
)
72 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
74 gpio_set_value(mxcs
->gpio
,
78 u32
get_cspi_div(u32 div
)
82 for (i
= 0; i
< 8; i
++) {
90 static s32
spi_cfg_mxc(struct mxc_spi_slave
*mxcs
, unsigned int cs
,
91 unsigned int max_hz
, unsigned int mode
)
93 unsigned int ctrl_reg
;
97 clk_src
= mxc_get_clock(MXC_CSPI_CLK
);
99 div
= DIV_ROUND_UP(clk_src
, max_hz
);
100 div
= get_cspi_div(div
);
102 debug("clk %d Hz, div %d, real clk %d Hz\n",
103 max_hz
, div
, clk_src
/ (4 << div
));
105 ctrl_reg
= MXC_CSPICTRL_CHIPSELECT(cs
) |
106 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS
) |
107 MXC_CSPICTRL_DATARATE(div
) |
115 ctrl_reg
|= MXC_CSPICTRL_PHA
;
117 ctrl_reg
|= MXC_CSPICTRL_POL
;
118 if (mode
& SPI_CS_HIGH
)
119 ctrl_reg
|= MXC_CSPICTRL_SSPOL
;
120 mxcs
->ctrl_reg
= ctrl_reg
;
127 static s32
spi_cfg_mxc(struct mxc_spi_slave
*mxcs
, unsigned int cs
,
128 unsigned int max_hz
, unsigned int mode
)
130 u32 clk_src
= mxc_get_clock(MXC_CSPI_CLK
);
131 s32 pre_div
= 0, post_div
= 0, i
, reg_ctrl
, reg_config
;
132 u32 ss_pol
= 0, sclkpol
= 0, sclkpha
= 0;
133 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
136 printf("Error: desired clock is 0\n");
141 * Reset SPI and set all CSs to master mode, if toggling
142 * between slave and master mode we might see a glitch
145 reg_ctrl
= MXC_CSPICTRL_MODE_MASK
;
146 reg_write(®s
->ctrl
, reg_ctrl
);
147 reg_ctrl
|= MXC_CSPICTRL_EN
;
148 reg_write(®s
->ctrl
, reg_ctrl
);
151 * The following computation is taken directly from Freescale's code.
153 if (clk_src
> max_hz
) {
154 pre_div
= DIV_ROUND_UP(clk_src
, max_hz
);
156 post_div
= pre_div
/ 16;
160 for (i
= 0; i
< 16; i
++) {
161 if ((1 << i
) >= post_div
)
165 printf("Error: no divider for the freq: %d\n",
173 debug("pre_div = %d, post_div=%d\n", pre_div
, post_div
);
174 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_SELCHAN(3)) |
175 MXC_CSPICTRL_SELCHAN(cs
);
176 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_PREDIV(0x0F)) |
177 MXC_CSPICTRL_PREDIV(pre_div
);
178 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_POSTDIV(0x0F)) |
179 MXC_CSPICTRL_POSTDIV(post_div
);
181 /* We need to disable SPI before changing registers */
182 reg_ctrl
&= ~MXC_CSPICTRL_EN
;
184 if (mode
& SPI_CS_HIGH
)
193 reg_config
= reg_read(®s
->cfg
);
196 * Configuration register setup
197 * The MX51 supports different setup for each SS
199 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_SSPOL
))) |
200 (ss_pol
<< (cs
+ MXC_CSPICON_SSPOL
));
201 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_POL
))) |
202 (sclkpol
<< (cs
+ MXC_CSPICON_POL
));
203 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_PHA
))) |
204 (sclkpha
<< (cs
+ MXC_CSPICON_PHA
));
206 debug("reg_ctrl = 0x%x\n", reg_ctrl
);
207 reg_write(®s
->ctrl
, reg_ctrl
);
208 debug("reg_config = 0x%x\n", reg_config
);
209 reg_write(®s
->cfg
, reg_config
);
211 /* save config register and control register */
212 mxcs
->ctrl_reg
= reg_ctrl
;
213 mxcs
->cfg_reg
= reg_config
;
215 /* clear interrupt reg */
216 reg_write(®s
->intr
, 0);
217 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
223 int spi_xchg_single(struct spi_slave
*slave
, unsigned int bitlen
,
224 const u8
*dout
, u8
*din
, unsigned long flags
)
226 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
227 int nbytes
= (bitlen
+ 7) / 8;
229 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
231 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
232 __func__
, bitlen
, (u32
)dout
, (u32
)din
);
234 mxcs
->ctrl_reg
= (mxcs
->ctrl_reg
&
235 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS
)) |
236 MXC_CSPICTRL_BITCOUNT(bitlen
- 1);
238 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
| MXC_CSPICTRL_EN
);
240 reg_write(®s
->cfg
, mxcs
->cfg_reg
);
243 /* Clear interrupt register */
244 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
247 * The SPI controller works only with words,
248 * check if less than a word is sent.
249 * Access to the FIFO is only 32 bit
253 cnt
= (bitlen
% 32) / 8;
255 for (i
= 0; i
< cnt
; i
++) {
256 data
= (data
<< 8) | (*dout
++ & 0xFF);
259 debug("Sending SPI 0x%x\n", data
);
261 reg_write(®s
->txdata
, data
);
270 /* Buffer is not 32-bit aligned */
271 if ((unsigned long)dout
& 0x03) {
273 for (i
= 0; i
< 4; i
++)
274 data
= (data
<< 8) | (*dout
++ & 0xFF);
277 data
= cpu_to_be32(data
);
281 debug("Sending SPI 0x%x\n", data
);
282 reg_write(®s
->txdata
, data
);
286 /* FIFO is written, now starts the transfer setting the XCH bit */
287 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
|
288 MXC_CSPICTRL_EN
| MXC_CSPICTRL_XCH
);
290 /* Wait until the TC (Transfer completed) bit is set */
291 while ((reg_read(®s
->stat
) & MXC_CSPICTRL_TC
) == 0)
294 /* Transfer completed, clear any pending request */
295 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
297 nbytes
= (bitlen
+ 7) / 8;
302 data
= reg_read(®s
->rxdata
);
303 cnt
= (bitlen
% 32) / 8;
304 data
= cpu_to_be32(data
) >> ((sizeof(data
) - cnt
) * 8);
305 debug("SPI Rx unaligned: 0x%x\n", data
);
307 memcpy(din
, &data
, cnt
);
315 tmp
= reg_read(®s
->rxdata
);
316 data
= cpu_to_be32(tmp
);
317 debug("SPI Rx: 0x%x 0x%x\n", tmp
, data
);
318 cnt
= min(nbytes
, sizeof(data
));
320 memcpy(din
, &data
, cnt
);
330 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
, const void *dout
,
331 void *din
, unsigned long flags
)
333 int n_bytes
= (bitlen
+ 7) / 8;
337 u8
*p_outbuf
= (u8
*)dout
;
338 u8
*p_inbuf
= (u8
*)din
;
343 if (flags
& SPI_XFER_BEGIN
)
344 spi_cs_activate(slave
);
346 while (n_bytes
> 0) {
347 if (n_bytes
< MAX_SPI_BYTES
)
350 blk_size
= MAX_SPI_BYTES
;
352 n_bits
= blk_size
* 8;
354 ret
= spi_xchg_single(slave
, n_bits
, p_outbuf
, p_inbuf
, 0);
359 p_outbuf
+= blk_size
;
365 if (flags
& SPI_XFER_END
) {
366 spi_cs_deactivate(slave
);
376 static int decode_cs(struct mxc_spi_slave
*mxcs
, unsigned int cs
)
381 * Some SPI devices require active chip-select over multiple
382 * transactions, we achieve this using a GPIO. Still, the SPI
383 * controller has to be configured to use one of its own chipselects.
384 * To use this feature you have to call spi_setup_slave() with
385 * cs = internal_cs | (gpio << 8), and you have to use some unused
386 * on this SPI controller cs between 0 and 3.
389 mxcs
->gpio
= cs
>> 8;
391 ret
= gpio_direction_output(mxcs
->gpio
, !(mxcs
->ss_pol
));
393 printf("mxc_spi: cannot setup gpio %d\n", mxcs
->gpio
);
403 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
404 unsigned int max_hz
, unsigned int mode
)
406 struct mxc_spi_slave
*mxcs
;
409 if (bus
>= ARRAY_SIZE(spi_bases
))
412 mxcs
= spi_alloc_slave(struct mxc_spi_slave
, bus
, cs
);
414 puts("mxc_spi: SPI Slave not allocated !\n");
418 mxcs
->ss_pol
= (mode
& SPI_CS_HIGH
) ? 1 : 0;
420 ret
= decode_cs(mxcs
, cs
);
428 mxcs
->base
= spi_bases
[bus
];
430 ret
= spi_cfg_mxc(mxcs
, cs
, max_hz
, mode
);
432 printf("mxc_spi: cannot setup SPI controller\n");
439 void spi_free_slave(struct spi_slave
*slave
)
441 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
446 int spi_claim_bus(struct spi_slave
*slave
)
448 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
449 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
451 reg_write(®s
->rxdata
, 1);
453 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
);
454 reg_write(®s
->period
, MXC_CSPIPERIOD_32KHZ
);
455 reg_write(®s
->intr
, 0);
460 void spi_release_bus(struct spi_slave
*slave
)
462 /* TODO: Shut the controller down */