]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/spi/mxc_spi.c
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/imx-common/spi.h>
18 /* i.MX27 has a completely wrong register layout and register definitions in the
19 * datasheet, the correct one is in the Freescale's Linux driver */
21 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
22 "See linux mxc_spi driver from Freescale for details."
25 static unsigned long spi_bases
[] = {
26 MXC_SPI_BASE_ADDRESSES
29 __weak
int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
34 #define OUT MXC_GPIO_DIRECTION_OUT
36 #define reg_read readl
37 #define reg_write(a, v) writel(v, a)
39 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
40 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
43 struct mxc_spi_slave
{
44 struct spi_slave slave
;
47 #if defined(MXC_ECSPI)
56 static inline struct mxc_spi_slave
*to_mxc_spi_slave(struct spi_slave
*slave
)
58 return container_of(slave
, struct mxc_spi_slave
, slave
);
61 void spi_cs_activate(struct spi_slave
*slave
)
63 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
65 gpio_set_value(mxcs
->gpio
, mxcs
->ss_pol
);
68 void spi_cs_deactivate(struct spi_slave
*slave
)
70 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
72 gpio_set_value(mxcs
->gpio
,
76 u32
get_cspi_div(u32 div
)
80 for (i
= 0; i
< 8; i
++) {
88 static s32
spi_cfg_mxc(struct mxc_spi_slave
*mxcs
, unsigned int cs
)
90 unsigned int ctrl_reg
;
93 unsigned int max_hz
= mxcs
->max_hz
;
94 unsigned int mode
= mxcs
->mode
;
96 clk_src
= mxc_get_clock(MXC_CSPI_CLK
);
98 div
= DIV_ROUND_UP(clk_src
, max_hz
);
99 div
= get_cspi_div(div
);
101 debug("clk %d Hz, div %d, real clk %d Hz\n",
102 max_hz
, div
, clk_src
/ (4 << div
));
104 ctrl_reg
= MXC_CSPICTRL_CHIPSELECT(cs
) |
105 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS
) |
106 MXC_CSPICTRL_DATARATE(div
) |
114 ctrl_reg
|= MXC_CSPICTRL_PHA
;
116 ctrl_reg
|= MXC_CSPICTRL_POL
;
117 if (mode
& SPI_CS_HIGH
)
118 ctrl_reg
|= MXC_CSPICTRL_SSPOL
;
119 mxcs
->ctrl_reg
= ctrl_reg
;
126 static s32
spi_cfg_mxc(struct mxc_spi_slave
*mxcs
, unsigned int cs
)
128 u32 clk_src
= mxc_get_clock(MXC_CSPI_CLK
);
129 s32 reg_ctrl
, reg_config
;
130 u32 ss_pol
= 0, sclkpol
= 0, sclkpha
= 0, sclkctl
= 0;
131 u32 pre_div
= 0, post_div
= 0;
132 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
133 unsigned int max_hz
= mxcs
->max_hz
;
134 unsigned int mode
= mxcs
->mode
;
137 * Reset SPI and set all CSs to master mode, if toggling
138 * between slave and master mode we might see a glitch
141 reg_ctrl
= MXC_CSPICTRL_MODE_MASK
;
142 reg_write(®s
->ctrl
, reg_ctrl
);
143 reg_ctrl
|= MXC_CSPICTRL_EN
;
144 reg_write(®s
->ctrl
, reg_ctrl
);
146 if (clk_src
> max_hz
) {
147 pre_div
= (clk_src
- 1) / max_hz
;
148 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
149 post_div
= fls(pre_div
);
152 if (post_div
>= 16) {
153 printf("Error: no divider for the freq: %d\n",
157 pre_div
>>= post_div
;
163 debug("pre_div = %d, post_div=%d\n", pre_div
, post_div
);
164 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_SELCHAN(3)) |
165 MXC_CSPICTRL_SELCHAN(cs
);
166 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_PREDIV(0x0F)) |
167 MXC_CSPICTRL_PREDIV(pre_div
);
168 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_POSTDIV(0x0F)) |
169 MXC_CSPICTRL_POSTDIV(post_div
);
171 if (mode
& SPI_CS_HIGH
)
174 if (mode
& SPI_CPOL
) {
182 reg_config
= reg_read(®s
->cfg
);
185 * Configuration register setup
186 * The MX51 supports different setup for each SS
188 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_SSPOL
))) |
189 (ss_pol
<< (cs
+ MXC_CSPICON_SSPOL
));
190 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_POL
))) |
191 (sclkpol
<< (cs
+ MXC_CSPICON_POL
));
192 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_CTL
))) |
193 (sclkctl
<< (cs
+ MXC_CSPICON_CTL
));
194 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_PHA
))) |
195 (sclkpha
<< (cs
+ MXC_CSPICON_PHA
));
197 debug("reg_ctrl = 0x%x\n", reg_ctrl
);
198 reg_write(®s
->ctrl
, reg_ctrl
);
199 debug("reg_config = 0x%x\n", reg_config
);
200 reg_write(®s
->cfg
, reg_config
);
202 /* save config register and control register */
203 mxcs
->ctrl_reg
= reg_ctrl
;
204 mxcs
->cfg_reg
= reg_config
;
206 /* clear interrupt reg */
207 reg_write(®s
->intr
, 0);
208 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
214 int spi_xchg_single(struct spi_slave
*slave
, unsigned int bitlen
,
215 const u8
*dout
, u8
*din
, unsigned long flags
)
217 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
218 int nbytes
= DIV_ROUND_UP(bitlen
, 8);
220 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
224 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
225 __func__
, bitlen
, (u32
)dout
, (u32
)din
);
227 mxcs
->ctrl_reg
= (mxcs
->ctrl_reg
&
228 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS
)) |
229 MXC_CSPICTRL_BITCOUNT(bitlen
- 1);
231 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
| MXC_CSPICTRL_EN
);
233 reg_write(®s
->cfg
, mxcs
->cfg_reg
);
236 /* Clear interrupt register */
237 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
240 * The SPI controller works only with words,
241 * check if less than a word is sent.
242 * Access to the FIFO is only 32 bit
246 cnt
= (bitlen
% 32) / 8;
248 for (i
= 0; i
< cnt
; i
++) {
249 data
= (data
<< 8) | (*dout
++ & 0xFF);
252 debug("Sending SPI 0x%x\n", data
);
254 reg_write(®s
->txdata
, data
);
263 /* Buffer is not 32-bit aligned */
264 if ((unsigned long)dout
& 0x03) {
266 for (i
= 0; i
< 4; i
++)
267 data
= (data
<< 8) | (*dout
++ & 0xFF);
270 data
= cpu_to_be32(data
);
274 debug("Sending SPI 0x%x\n", data
);
275 reg_write(®s
->txdata
, data
);
279 /* FIFO is written, now starts the transfer setting the XCH bit */
280 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
|
281 MXC_CSPICTRL_EN
| MXC_CSPICTRL_XCH
);
284 status
= reg_read(®s
->stat
);
285 /* Wait until the TC (Transfer completed) bit is set */
286 while ((status
& MXC_CSPICTRL_TC
) == 0) {
287 if (get_timer(ts
) > CONFIG_SYS_SPI_MXC_WAIT
) {
288 printf("spi_xchg_single: Timeout!\n");
291 status
= reg_read(®s
->stat
);
294 /* Transfer completed, clear any pending request */
295 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
297 nbytes
= DIV_ROUND_UP(bitlen
, 8);
302 data
= reg_read(®s
->rxdata
);
303 cnt
= (bitlen
% 32) / 8;
304 data
= cpu_to_be32(data
) >> ((sizeof(data
) - cnt
) * 8);
305 debug("SPI Rx unaligned: 0x%x\n", data
);
307 memcpy(din
, &data
, cnt
);
315 tmp
= reg_read(®s
->rxdata
);
316 data
= cpu_to_be32(tmp
);
317 debug("SPI Rx: 0x%x 0x%x\n", tmp
, data
);
318 cnt
= min(nbytes
, sizeof(data
));
320 memcpy(din
, &data
, cnt
);
330 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
, const void *dout
,
331 void *din
, unsigned long flags
)
333 int n_bytes
= DIV_ROUND_UP(bitlen
, 8);
337 u8
*p_outbuf
= (u8
*)dout
;
338 u8
*p_inbuf
= (u8
*)din
;
343 if (flags
& SPI_XFER_BEGIN
)
344 spi_cs_activate(slave
);
346 while (n_bytes
> 0) {
347 if (n_bytes
< MAX_SPI_BYTES
)
350 blk_size
= MAX_SPI_BYTES
;
352 n_bits
= blk_size
* 8;
354 ret
= spi_xchg_single(slave
, n_bits
, p_outbuf
, p_inbuf
, 0);
359 p_outbuf
+= blk_size
;
365 if (flags
& SPI_XFER_END
) {
366 spi_cs_deactivate(slave
);
377 * Some SPI devices require active chip-select over multiple
378 * transactions, we achieve this using a GPIO. Still, the SPI
379 * controller has to be configured to use one of its own chipselects.
380 * To use this feature you have to implement board_spi_cs_gpio() to assign
381 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
382 * You must use some unused on this SPI controller cs between 0 and 3.
384 static int setup_cs_gpio(struct mxc_spi_slave
*mxcs
,
385 unsigned int bus
, unsigned int cs
)
389 mxcs
->gpio
= board_spi_cs_gpio(bus
, cs
);
390 if (mxcs
->gpio
== -1)
393 ret
= gpio_direction_output(mxcs
->gpio
, !(mxcs
->ss_pol
));
395 printf("mxc_spi: cannot setup gpio %d\n", mxcs
->gpio
);
402 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
403 unsigned int max_hz
, unsigned int mode
)
405 struct mxc_spi_slave
*mxcs
;
408 if (bus
>= ARRAY_SIZE(spi_bases
))
412 printf("Error: desired clock is 0\n");
416 mxcs
= spi_alloc_slave(struct mxc_spi_slave
, bus
, cs
);
418 puts("mxc_spi: SPI Slave not allocated !\n");
422 mxcs
->ss_pol
= (mode
& SPI_CS_HIGH
) ? 1 : 0;
424 ret
= setup_cs_gpio(mxcs
, bus
, cs
);
430 mxcs
->base
= spi_bases
[bus
];
431 mxcs
->max_hz
= max_hz
;
437 void spi_free_slave(struct spi_slave
*slave
)
439 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
444 int spi_claim_bus(struct spi_slave
*slave
)
447 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
448 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
450 reg_write(®s
->rxdata
, 1);
452 ret
= spi_cfg_mxc(mxcs
, slave
->cs
);
454 printf("mxc_spi: cannot setup SPI controller\n");
457 reg_write(®s
->period
, MXC_CSPIPERIOD_32KHZ
);
458 reg_write(®s
->intr
, 0);
463 void spi_release_bus(struct spi_slave
*slave
)
465 /* TODO: Shut the controller down */