]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/spi/mxc_spi.c
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/spi.h>
18 DECLARE_GLOBAL_DATA_PTR
;
21 /* i.MX27 has a completely wrong register layout and register definitions in the
22 * datasheet, the correct one is in the Freescale's Linux driver */
24 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
25 "See linux mxc_spi driver from Freescale for details."
28 __weak
int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
33 #define OUT MXC_GPIO_DIRECTION_OUT
35 #define reg_read readl
36 #define reg_write(a, v) writel(v, a)
38 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
39 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
42 struct mxc_spi_slave
{
43 struct spi_slave slave
;
46 #if defined(MXC_ECSPI)
56 static inline struct mxc_spi_slave
*to_mxc_spi_slave(struct spi_slave
*slave
)
58 return container_of(slave
, struct mxc_spi_slave
, slave
);
61 static void mxc_spi_cs_activate(struct mxc_spi_slave
*mxcs
)
63 if (CONFIG_IS_ENABLED(DM_SPI
)) {
64 dm_gpio_set_value(&mxcs
->ss
, mxcs
->ss_pol
);
67 gpio_set_value(mxcs
->gpio
, mxcs
->ss_pol
);
71 static void mxc_spi_cs_deactivate(struct mxc_spi_slave
*mxcs
)
73 if (CONFIG_IS_ENABLED(DM_SPI
)) {
74 dm_gpio_set_value(&mxcs
->ss
, !(mxcs
->ss_pol
));
77 gpio_set_value(mxcs
->gpio
, !(mxcs
->ss_pol
));
81 u32
get_cspi_div(u32 div
)
85 for (i
= 0; i
< 8; i
++) {
93 static s32
spi_cfg_mxc(struct mxc_spi_slave
*mxcs
, unsigned int cs
)
95 unsigned int ctrl_reg
;
98 unsigned int max_hz
= mxcs
->max_hz
;
99 unsigned int mode
= mxcs
->mode
;
101 clk_src
= mxc_get_clock(MXC_CSPI_CLK
);
103 div
= DIV_ROUND_UP(clk_src
, max_hz
);
104 div
= get_cspi_div(div
);
106 debug("clk %d Hz, div %d, real clk %d Hz\n",
107 max_hz
, div
, clk_src
/ (4 << div
));
109 ctrl_reg
= MXC_CSPICTRL_CHIPSELECT(cs
) |
110 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS
) |
111 MXC_CSPICTRL_DATARATE(div
) |
119 ctrl_reg
|= MXC_CSPICTRL_PHA
;
121 ctrl_reg
|= MXC_CSPICTRL_POL
;
122 if (mode
& SPI_CS_HIGH
)
123 ctrl_reg
|= MXC_CSPICTRL_SSPOL
;
124 mxcs
->ctrl_reg
= ctrl_reg
;
131 static s32
spi_cfg_mxc(struct mxc_spi_slave
*mxcs
, unsigned int cs
)
133 u32 clk_src
= mxc_get_clock(MXC_CSPI_CLK
);
134 s32 reg_ctrl
, reg_config
;
135 u32 ss_pol
= 0, sclkpol
= 0, sclkpha
= 0, sclkctl
= 0;
136 u32 pre_div
= 0, post_div
= 0;
137 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
138 unsigned int max_hz
= mxcs
->max_hz
;
139 unsigned int mode
= mxcs
->mode
;
142 * Reset SPI and set all CSs to master mode, if toggling
143 * between slave and master mode we might see a glitch
146 reg_ctrl
= MXC_CSPICTRL_MODE_MASK
;
147 reg_write(®s
->ctrl
, reg_ctrl
);
148 reg_ctrl
|= MXC_CSPICTRL_EN
;
149 reg_write(®s
->ctrl
, reg_ctrl
);
151 if (clk_src
> max_hz
) {
152 pre_div
= (clk_src
- 1) / max_hz
;
153 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
154 post_div
= fls(pre_div
);
157 if (post_div
>= 16) {
158 printf("Error: no divider for the freq: %d\n",
162 pre_div
>>= post_div
;
168 debug("pre_div = %d, post_div=%d\n", pre_div
, post_div
);
169 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_SELCHAN(3)) |
170 MXC_CSPICTRL_SELCHAN(cs
);
171 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_PREDIV(0x0F)) |
172 MXC_CSPICTRL_PREDIV(pre_div
);
173 reg_ctrl
= (reg_ctrl
& ~MXC_CSPICTRL_POSTDIV(0x0F)) |
174 MXC_CSPICTRL_POSTDIV(post_div
);
176 if (mode
& SPI_CS_HIGH
)
179 if (mode
& SPI_CPOL
) {
187 reg_config
= reg_read(®s
->cfg
);
190 * Configuration register setup
191 * The MX51 supports different setup for each SS
193 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_SSPOL
))) |
194 (ss_pol
<< (cs
+ MXC_CSPICON_SSPOL
));
195 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_POL
))) |
196 (sclkpol
<< (cs
+ MXC_CSPICON_POL
));
197 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_CTL
))) |
198 (sclkctl
<< (cs
+ MXC_CSPICON_CTL
));
199 reg_config
= (reg_config
& ~(1 << (cs
+ MXC_CSPICON_PHA
))) |
200 (sclkpha
<< (cs
+ MXC_CSPICON_PHA
));
202 debug("reg_ctrl = 0x%x\n", reg_ctrl
);
203 reg_write(®s
->ctrl
, reg_ctrl
);
204 debug("reg_config = 0x%x\n", reg_config
);
205 reg_write(®s
->cfg
, reg_config
);
207 /* save config register and control register */
208 mxcs
->ctrl_reg
= reg_ctrl
;
209 mxcs
->cfg_reg
= reg_config
;
211 /* clear interrupt reg */
212 reg_write(®s
->intr
, 0);
213 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
219 int spi_xchg_single(struct mxc_spi_slave
*mxcs
, unsigned int bitlen
,
220 const u8
*dout
, u8
*din
, unsigned long flags
)
222 int nbytes
= DIV_ROUND_UP(bitlen
, 8);
224 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
228 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
229 __func__
, bitlen
, (u32
)dout
, (u32
)din
);
231 mxcs
->ctrl_reg
= (mxcs
->ctrl_reg
&
232 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS
)) |
233 MXC_CSPICTRL_BITCOUNT(bitlen
- 1);
235 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
| MXC_CSPICTRL_EN
);
237 reg_write(®s
->cfg
, mxcs
->cfg_reg
);
240 /* Clear interrupt register */
241 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
244 * The SPI controller works only with words,
245 * check if less than a word is sent.
246 * Access to the FIFO is only 32 bit
250 cnt
= (bitlen
% 32) / 8;
252 for (i
= 0; i
< cnt
; i
++) {
253 data
= (data
<< 8) | (*dout
++ & 0xFF);
256 debug("Sending SPI 0x%x\n", data
);
258 reg_write(®s
->txdata
, data
);
267 /* Buffer is not 32-bit aligned */
268 if ((unsigned long)dout
& 0x03) {
270 for (i
= 0; i
< 4; i
++)
271 data
= (data
<< 8) | (*dout
++ & 0xFF);
274 data
= cpu_to_be32(data
);
278 debug("Sending SPI 0x%x\n", data
);
279 reg_write(®s
->txdata
, data
);
283 /* FIFO is written, now starts the transfer setting the XCH bit */
284 reg_write(®s
->ctrl
, mxcs
->ctrl_reg
|
285 MXC_CSPICTRL_EN
| MXC_CSPICTRL_XCH
);
288 status
= reg_read(®s
->stat
);
289 /* Wait until the TC (Transfer completed) bit is set */
290 while ((status
& MXC_CSPICTRL_TC
) == 0) {
291 if (get_timer(ts
) > CONFIG_SYS_SPI_MXC_WAIT
) {
292 printf("spi_xchg_single: Timeout!\n");
295 status
= reg_read(®s
->stat
);
298 /* Transfer completed, clear any pending request */
299 reg_write(®s
->stat
, MXC_CSPICTRL_TC
| MXC_CSPICTRL_RXOVF
);
301 nbytes
= DIV_ROUND_UP(bitlen
, 8);
306 data
= reg_read(®s
->rxdata
);
307 cnt
= (bitlen
% 32) / 8;
308 data
= cpu_to_be32(data
) >> ((sizeof(data
) - cnt
) * 8);
309 debug("SPI Rx unaligned: 0x%x\n", data
);
311 memcpy(din
, &data
, cnt
);
319 tmp
= reg_read(®s
->rxdata
);
320 data
= cpu_to_be32(tmp
);
321 debug("SPI Rx: 0x%x 0x%x\n", tmp
, data
);
322 cnt
= min_t(u32
, nbytes
, sizeof(data
));
324 memcpy(din
, &data
, cnt
);
334 static int mxc_spi_xfer_internal(struct mxc_spi_slave
*mxcs
,
335 unsigned int bitlen
, const void *dout
,
336 void *din
, unsigned long flags
)
338 int n_bytes
= DIV_ROUND_UP(bitlen
, 8);
342 u8
*p_outbuf
= (u8
*)dout
;
343 u8
*p_inbuf
= (u8
*)din
;
348 if (flags
& SPI_XFER_BEGIN
)
349 mxc_spi_cs_activate(mxcs
);
351 while (n_bytes
> 0) {
352 if (n_bytes
< MAX_SPI_BYTES
)
355 blk_size
= MAX_SPI_BYTES
;
357 n_bits
= blk_size
* 8;
359 ret
= spi_xchg_single(mxcs
, n_bits
, p_outbuf
, p_inbuf
, 0);
364 p_outbuf
+= blk_size
;
370 if (flags
& SPI_XFER_END
) {
371 mxc_spi_cs_deactivate(mxcs
);
377 static int mxc_spi_claim_bus_internal(struct mxc_spi_slave
*mxcs
, int cs
)
379 struct cspi_regs
*regs
= (struct cspi_regs
*)mxcs
->base
;
382 reg_write(®s
->rxdata
, 1);
384 ret
= spi_cfg_mxc(mxcs
, cs
);
386 printf("mxc_spi: cannot setup SPI controller\n");
389 reg_write(®s
->period
, MXC_CSPIPERIOD_32KHZ
);
390 reg_write(®s
->intr
, 0);
395 #ifndef CONFIG_DM_SPI
396 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
, const void *dout
,
397 void *din
, unsigned long flags
)
399 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
401 return mxc_spi_xfer_internal(mxcs
, bitlen
, dout
, din
, flags
);
409 * Some SPI devices require active chip-select over multiple
410 * transactions, we achieve this using a GPIO. Still, the SPI
411 * controller has to be configured to use one of its own chipselects.
412 * To use this feature you have to implement board_spi_cs_gpio() to assign
413 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
414 * You must use some unused on this SPI controller cs between 0 and 3.
416 static int setup_cs_gpio(struct mxc_spi_slave
*mxcs
,
417 unsigned int bus
, unsigned int cs
)
421 mxcs
->gpio
= board_spi_cs_gpio(bus
, cs
);
422 if (mxcs
->gpio
== -1)
425 gpio_request(mxcs
->gpio
, "spi-cs");
426 ret
= gpio_direction_output(mxcs
->gpio
, !(mxcs
->ss_pol
));
428 printf("mxc_spi: cannot setup gpio %d\n", mxcs
->gpio
);
435 static unsigned long spi_bases
[] = {
436 MXC_SPI_BASE_ADDRESSES
439 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
440 unsigned int max_hz
, unsigned int mode
)
442 struct mxc_spi_slave
*mxcs
;
445 if (bus
>= ARRAY_SIZE(spi_bases
))
449 printf("Error: desired clock is 0\n");
453 mxcs
= spi_alloc_slave(struct mxc_spi_slave
, bus
, cs
);
455 puts("mxc_spi: SPI Slave not allocated !\n");
459 mxcs
->ss_pol
= (mode
& SPI_CS_HIGH
) ? 1 : 0;
461 ret
= setup_cs_gpio(mxcs
, bus
, cs
);
467 mxcs
->base
= spi_bases
[bus
];
468 mxcs
->max_hz
= max_hz
;
474 void spi_free_slave(struct spi_slave
*slave
)
476 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
481 int spi_claim_bus(struct spi_slave
*slave
)
483 struct mxc_spi_slave
*mxcs
= to_mxc_spi_slave(slave
);
485 return mxc_spi_claim_bus_internal(mxcs
, slave
->cs
);
488 void spi_release_bus(struct spi_slave
*slave
)
490 /* TODO: Shut the controller down */
494 static int mxc_spi_probe(struct udevice
*bus
)
496 struct mxc_spi_slave
*plat
= bus
->platdata
;
497 struct mxc_spi_slave
*mxcs
= dev_get_platdata(bus
);
498 int node
= dev_of_offset(bus
);
499 const void *blob
= gd
->fdt_blob
;
502 if (gpio_request_by_name(bus
, "cs-gpios", 0, &plat
->ss
,
504 dev_err(bus
, "No cs-gpios property\n");
508 plat
->base
= dev_get_addr(bus
);
509 if (plat
->base
== FDT_ADDR_T_NONE
)
512 ret
= dm_gpio_set_value(&plat
->ss
, !(mxcs
->ss_pol
));
514 dev_err(bus
, "Setting cs error\n");
518 mxcs
->max_hz
= fdtdec_get_int(blob
, node
, "spi-max-frequency",
524 static int mxc_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
525 const void *dout
, void *din
, unsigned long flags
)
527 struct mxc_spi_slave
*mxcs
= dev_get_platdata(dev
->parent
);
530 return mxc_spi_xfer_internal(mxcs
, bitlen
, dout
, din
, flags
);
533 static int mxc_spi_claim_bus(struct udevice
*dev
)
535 struct mxc_spi_slave
*mxcs
= dev_get_platdata(dev
->parent
);
536 struct dm_spi_slave_platdata
*slave_plat
= dev_get_parent_platdata(dev
);
538 return mxc_spi_claim_bus_internal(mxcs
, slave_plat
->cs
);
541 static int mxc_spi_release_bus(struct udevice
*dev
)
546 static int mxc_spi_set_speed(struct udevice
*bus
, uint speed
)
552 static int mxc_spi_set_mode(struct udevice
*bus
, uint mode
)
554 struct mxc_spi_slave
*mxcs
= dev_get_platdata(bus
);
557 mxcs
->ss_pol
= (mode
& SPI_CS_HIGH
) ? 1 : 0;
562 static const struct dm_spi_ops mxc_spi_ops
= {
563 .claim_bus
= mxc_spi_claim_bus
,
564 .release_bus
= mxc_spi_release_bus
,
565 .xfer
= mxc_spi_xfer
,
566 .set_speed
= mxc_spi_set_speed
,
567 .set_mode
= mxc_spi_set_mode
,
570 static const struct udevice_id mxc_spi_ids
[] = {
571 { .compatible
= "fsl,imx51-ecspi" },
575 U_BOOT_DRIVER(mxc_spi
) = {
578 .of_match
= mxc_spi_ids
,
580 .platdata_auto_alloc_size
= sizeof(struct mxc_spi_slave
),
581 .probe
= mxc_spi_probe
,