drivers/spi/mxc_spi.c

   1 /*
   2  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <malloc.h>
   9 #include <spi.h>
  10 #include <asm/errno.h>
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15
  16 #ifdef CONFIG_MX27
  17 /* i.MX27 has a completely wrong register layout and register definitions in the
  18  * datasheet, the correct one is in the Freescale's Linux driver */
  19
  20 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
  21 "See linux mxc_spi driver from Freescale for details."
  22 #endif
  23
  24 static unsigned long spi_bases[] = {
  25         MXC_SPI_BASE_ADDRESSES
  26 };
  27
  28 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
  29 {
  30         return -1;
  31 }
  32
  33 #define OUT     MXC_GPIO_DIRECTION_OUT
  34
  35 #define reg_read readl
  36 #define reg_write(a, v) writel(v, a)
  37
  38 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
  39 #define CONFIG_SYS_SPI_MXC_WAIT         (CONFIG_SYS_HZ/100)     /* 10 ms */
  40 #endif
  41
  42 struct mxc_spi_slave {
  43         struct spi_slave slave;
  44         unsigned long   base;
  45         u32             ctrl_reg;
  46 #if defined(MXC_ECSPI)
  47         u32             cfg_reg;
  48 #endif
  49         int             gpio;
  50         int             ss_pol;
  51 };
  52
  53 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
  54 {
  55         return container_of(slave, struct mxc_spi_slave, slave);
  56 }
  57
  58 void spi_cs_activate(struct spi_slave *slave)
  59 {
  60         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  61         if (mxcs->gpio > 0)
  62                 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
  63 }
  64
  65 void spi_cs_deactivate(struct spi_slave *slave)
  66 {
  67         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  68         if (mxcs->gpio > 0)
  69                 gpio_set_value(mxcs->gpio,
  70                               !(mxcs->ss_pol));
  71 }
  72
  73 u32 get_cspi_div(u32 div)
  74 {
  75         int i;
  76
  77         for (i = 0; i < 8; i++) {
  78                 if (div <= (4 << i))
  79                         return i;
  80         }
  81         return i;
  82 }
  83
  84 #ifdef MXC_CSPI
  85 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
  86                 unsigned int max_hz, unsigned int mode)
  87 {
  88         unsigned int ctrl_reg;
  89         u32 clk_src;
  90         u32 div;
  91
  92         clk_src = mxc_get_clock(MXC_CSPI_CLK);
  93
  94         div = DIV_ROUND_UP(clk_src, max_hz);
  95         div = get_cspi_div(div);
  96
  97         debug("clk %d Hz, div %d, real clk %d Hz\n",
  98                 max_hz, div, clk_src / (4 << div));
  99
 100         ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 101                 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
 102                 MXC_CSPICTRL_DATARATE(div) |
 103                 MXC_CSPICTRL_EN |
 104 #ifdef CONFIG_MX35
 105                 MXC_CSPICTRL_SSCTL |
 106 #endif
 107                 MXC_CSPICTRL_MODE;
 108
 109         if (mode & SPI_CPHA)
 110                 ctrl_reg |= MXC_CSPICTRL_PHA;
 111         if (mode & SPI_CPOL)
 112                 ctrl_reg |= MXC_CSPICTRL_POL;
 113         if (mode & SPI_CS_HIGH)
 114                 ctrl_reg |= MXC_CSPICTRL_SSPOL;
 115         mxcs->ctrl_reg = ctrl_reg;
 116
 117         return 0;
 118 }
 119 #endif
 120
 121 #ifdef MXC_ECSPI
 122 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 123                 unsigned int max_hz, unsigned int mode)
 124 {
 125         u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
 126         s32 reg_ctrl, reg_config;
 127         u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
 128         u32 pre_div = 0, post_div = 0;
 129         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 130
 131         if (max_hz == 0) {
 132                 printf("Error: desired clock is 0\n");
 133                 return -1;
 134         }
 135
 136         /*
 137          * Reset SPI and set all CSs to master mode, if toggling
 138          * between slave and master mode we might see a glitch
 139          * on the clock line
 140          */
 141         reg_ctrl = MXC_CSPICTRL_MODE_MASK;
 142         reg_write(&regs->ctrl, reg_ctrl);
 143         reg_ctrl |=  MXC_CSPICTRL_EN;
 144         reg_write(&regs->ctrl, reg_ctrl);
 145
 146         if (clk_src > max_hz) {
 147                 pre_div = (clk_src - 1) / max_hz;
 148                 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
 149                 post_div = fls(pre_div);
 150                 if (post_div > 4) {
 151                         post_div -= 4;
 152                         if (post_div >= 16) {
 153                                 printf("Error: no divider for the freq: %d\n",
 154                                         max_hz);
 155                                 return -1;
 156                         }
 157                         pre_div >>= post_div;
 158                 } else {
 159                         post_div = 0;
 160                 }
 161         }
 162
 163         debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
 164         reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
 165                 MXC_CSPICTRL_SELCHAN(cs);
 166         reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
 167                 MXC_CSPICTRL_PREDIV(pre_div);
 168         reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
 169                 MXC_CSPICTRL_POSTDIV(post_div);
 170
 171         /* We need to disable SPI before changing registers */
 172         reg_ctrl &= ~MXC_CSPICTRL_EN;
 173
 174         if (mode & SPI_CS_HIGH)
 175                 ss_pol = 1;
 176
 177         if (mode & SPI_CPOL) {
 178                 sclkpol = 1;
 179                 sclkctl = 1;
 180         }
 181
 182         if (mode & SPI_CPHA)
 183                 sclkpha = 1;
 184
 185         reg_config = reg_read(&regs->cfg);
 186
 187         /*
 188          * Configuration register setup
 189          * The MX51 supports different setup for each SS
 190          */
 191         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
 192                 (ss_pol << (cs + MXC_CSPICON_SSPOL));
 193         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
 194                 (sclkpol << (cs + MXC_CSPICON_POL));
 195         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
 196                 (sclkctl << (cs + MXC_CSPICON_CTL));
 197         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
 198                 (sclkpha << (cs + MXC_CSPICON_PHA));
 199
 200         debug("reg_ctrl = 0x%x\n", reg_ctrl);
 201         reg_write(&regs->ctrl, reg_ctrl);
 202         debug("reg_config = 0x%x\n", reg_config);
 203         reg_write(&regs->cfg, reg_config);
 204
 205         /* save config register and control register */
 206         mxcs->ctrl_reg = reg_ctrl;
 207         mxcs->cfg_reg = reg_config;
 208
 209         /* clear interrupt reg */
 210         reg_write(&regs->intr, 0);
 211         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
 212
 213         return 0;
 214 }
 215 #endif
 216
 217 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
 218         const u8 *dout, u8 *din, unsigned long flags)
 219 {
 220         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 221         int nbytes = DIV_ROUND_UP(bitlen, 8);
 222         u32 data, cnt, i;
 223         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 224         u32 ts;
 225         int status;
 226
 227         debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 228                 __func__, bitlen, (u32)dout, (u32)din);
 229
 230         mxcs->ctrl_reg = (mxcs->ctrl_reg &
 231                 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
 232                 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
 233
 234         reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
 235 #ifdef MXC_ECSPI
 236         reg_write(&regs->cfg, mxcs->cfg_reg);
 237 #endif
 238
 239         /* Clear interrupt register */
 240         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
 241
 242         /*
 243          * The SPI controller works only with words,
 244          * check if less than a word is sent.
 245          * Access to the FIFO is only 32 bit
 246          */
 247         if (bitlen % 32) {
 248                 data = 0;
 249                 cnt = (bitlen % 32) / 8;
 250                 if (dout) {
 251                         for (i = 0; i < cnt; i++) {
 252                                 data = (data << 8) | (*dout++ & 0xFF);
 253                         }
 254                 }
 255                 debug("Sending SPI 0x%x\n", data);
 256
 257                 reg_write(&regs->txdata, data);
 258                 nbytes -= cnt;
 259         }
 260
 261         data = 0;
 262
 263         while (nbytes > 0) {
 264                 data = 0;
 265                 if (dout) {
 266                         /* Buffer is not 32-bit aligned */
 267                         if ((unsigned long)dout & 0x03) {
 268                                 data = 0;
 269                                 for (i = 0; i < 4; i++)
 270                                         data = (data << 8) | (*dout++ & 0xFF);
 271                         } else {
 272                                 data = *(u32 *)dout;
 273                                 data = cpu_to_be32(data);
 274                                 dout += 4;
 275                         }
 276                 }
 277                 debug("Sending SPI 0x%x\n", data);
 278                 reg_write(&regs->txdata, data);
 279                 nbytes -= 4;
 280         }
 281
 282         /* FIFO is written, now starts the transfer setting the XCH bit */
 283         reg_write(&regs->ctrl, mxcs->ctrl_reg |
 284                 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
 285
 286         ts = get_timer(0);
 287         status = reg_read(&regs->stat);
 288         /* Wait until the TC (Transfer completed) bit is set */
 289         while ((status & MXC_CSPICTRL_TC) == 0) {
 290                 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
 291                         printf("spi_xchg_single: Timeout!\n");
 292                         return -1;
 293                 }
 294                 status = reg_read(&regs->stat);
 295         }
 296
 297         /* Transfer completed, clear any pending request */
 298         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
 299
 300         nbytes = DIV_ROUND_UP(bitlen, 8);
 301
 302         cnt = nbytes % 32;
 303
 304         if (bitlen % 32) {
 305                 data = reg_read(&regs->rxdata);
 306                 cnt = (bitlen % 32) / 8;
 307                 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
 308                 debug("SPI Rx unaligned: 0x%x\n", data);
 309                 if (din) {
 310                         memcpy(din, &data, cnt);
 311                         din += cnt;
 312                 }
 313                 nbytes -= cnt;
 314         }
 315
 316         while (nbytes > 0) {
 317                 u32 tmp;
 318                 tmp = reg_read(&regs->rxdata);
 319                 data = cpu_to_be32(tmp);
 320                 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
 321                 cnt = min(nbytes, sizeof(data));
 322                 if (din) {
 323                         memcpy(din, &data, cnt);
 324                         din += cnt;
 325                 }
 326                 nbytes -= cnt;
 327         }
 328
 329         return 0;
 330
 331 }
 332
 333 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 334                 void *din, unsigned long flags)
 335 {
 336         int n_bytes = DIV_ROUND_UP(bitlen, 8);
 337         int n_bits;
 338         int ret;
 339         u32 blk_size;
 340         u8 *p_outbuf = (u8 *)dout;
 341         u8 *p_inbuf = (u8 *)din;
 342
 343         if (!slave)
 344                 return -1;
 345
 346         if (flags & SPI_XFER_BEGIN)
 347                 spi_cs_activate(slave);
 348
 349         while (n_bytes > 0) {
 350                 if (n_bytes < MAX_SPI_BYTES)
 351                         blk_size = n_bytes;
 352                 else
 353                         blk_size = MAX_SPI_BYTES;
 354
 355                 n_bits = blk_size * 8;
 356
 357                 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
 358
 359                 if (ret)
 360                         return ret;
 361                 if (dout)
 362                         p_outbuf += blk_size;
 363                 if (din)
 364                         p_inbuf += blk_size;
 365                 n_bytes -= blk_size;
 366         }
 367
 368         if (flags & SPI_XFER_END) {
 369                 spi_cs_deactivate(slave);
 370         }
 371
 372         return 0;
 373 }
 374
 375 void spi_init(void)
 376 {
 377 }
 378
 379 /*
 380  * Some SPI devices require active chip-select over multiple
 381  * transactions, we achieve this using a GPIO. Still, the SPI
 382  * controller has to be configured to use one of its own chipselects.
 383  * To use this feature you have to implement board_spi_cs_gpio() to assign
 384  * a gpio value for each cs (-1 if cs doesn't need to use gpio).
 385  * You must use some unused on this SPI controller cs between 0 and 3.
 386  */
 387 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
 388                          unsigned int bus, unsigned int cs)
 389 {
 390         int ret;
 391
 392         mxcs->gpio = board_spi_cs_gpio(bus, cs);
 393         if (mxcs->gpio == -1)
 394                 return 0;
 395
 396         ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
 397         if (ret) {
 398                 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
 399                 return -EINVAL;
 400         }
 401
 402         return 0;
 403 }
 404
 405 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 406                         unsigned int max_hz, unsigned int mode)
 407 {
 408         struct mxc_spi_slave *mxcs;
 409         int ret;
 410
 411         if (bus >= ARRAY_SIZE(spi_bases))
 412                 return NULL;
 413
 414         mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
 415         if (!mxcs) {
 416                 puts("mxc_spi: SPI Slave not allocated !\n");
 417                 return NULL;
 418         }
 419
 420         mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
 421
 422         ret = setup_cs_gpio(mxcs, bus, cs);
 423         if (ret < 0) {
 424                 free(mxcs);
 425                 return NULL;
 426         }
 427
 428         mxcs->base = spi_bases[bus];
 429
 430         ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
 431         if (ret) {
 432                 printf("mxc_spi: cannot setup SPI controller\n");
 433                 free(mxcs);
 434                 return NULL;
 435         }
 436         return &mxcs->slave;
 437 }
 438
 439 void spi_free_slave(struct spi_slave *slave)
 440 {
 441         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 442
 443         free(mxcs);
 444 }
 445
 446 int spi_claim_bus(struct spi_slave *slave)
 447 {
 448         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 449         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 450
 451         reg_write(&regs->rxdata, 1);
 452         udelay(1);
 453         reg_write(&regs->ctrl, mxcs->ctrl_reg);
 454         reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
 455         reg_write(&regs->intr, 0);
 456
 457         return 0;
 458 }
 459
 460 void spi_release_bus(struct spi_slave *slave)
 461 {
 462         /* TODO: Shut the controller down */
 463 }