drivers/spi/mxc_spi.c

   1 /*
   2  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  *
  19  */
  20
  21 #include <common.h>
  22 #include <malloc.h>
  23 #include <spi.h>
  24 #include <asm/errno.h>
  25 #include <asm/io.h>
  26 #include <asm/gpio.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/clock.h>
  29
  30 #ifdef CONFIG_MX27
  31 /* i.MX27 has a completely wrong register layout and register definitions in the
  32  * datasheet, the correct one is in the Freescale's Linux driver */
  33
  34 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
  35 "See linux mxc_spi driver from Freescale for details."
  36 #endif
  37
  38 static unsigned long spi_bases[] = {
  39         MXC_SPI_BASE_ADDRESSES
  40 };
  41
  42 #define OUT     MXC_GPIO_DIRECTION_OUT
  43
  44 #define reg_read readl
  45 #define reg_write(a, v) writel(v, a)
  46
  47 struct mxc_spi_slave {
  48         struct spi_slave slave;
  49         unsigned long   base;
  50         u32             ctrl_reg;
  51 #if defined(MXC_ECSPI)
  52         u32             cfg_reg;
  53 #endif
  54         int             gpio;
  55         int             ss_pol;
  56 };
  57
  58 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
  59 {
  60         return container_of(slave, struct mxc_spi_slave, slave);
  61 }
  62
  63 void spi_cs_activate(struct spi_slave *slave)
  64 {
  65         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  66         if (mxcs->gpio > 0)
  67                 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
  68 }
  69
  70 void spi_cs_deactivate(struct spi_slave *slave)
  71 {
  72         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  73         if (mxcs->gpio > 0)
  74                 gpio_set_value(mxcs->gpio,
  75                               !(mxcs->ss_pol));
  76 }
  77
  78 u32 get_cspi_div(u32 div)
  79 {
  80         int i;
  81
  82         for (i = 0; i < 8; i++) {
  83                 if (div <= (4 << i))
  84                         return i;
  85         }
  86         return i;
  87 }
  88
  89 #ifdef MXC_CSPI
  90 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
  91                 unsigned int max_hz, unsigned int mode)
  92 {
  93         unsigned int ctrl_reg;
  94         u32 clk_src;
  95         u32 div;
  96
  97         clk_src = mxc_get_clock(MXC_CSPI_CLK);
  98
  99         div = DIV_ROUND_UP(clk_src, max_hz);
 100         div = get_cspi_div(div);
 101
 102         debug("clk %d Hz, div %d, real clk %d Hz\n",
 103                 max_hz, div, clk_src / (4 << div));
 104
 105         ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 106                 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
 107                 MXC_CSPICTRL_DATARATE(div) |
 108                 MXC_CSPICTRL_EN |
 109 #ifdef CONFIG_MX35
 110                 MXC_CSPICTRL_SSCTL |
 111 #endif
 112                 MXC_CSPICTRL_MODE;
 113
 114         if (mode & SPI_CPHA)
 115                 ctrl_reg |= MXC_CSPICTRL_PHA;
 116         if (mode & SPI_CPOL)
 117                 ctrl_reg |= MXC_CSPICTRL_POL;
 118         if (mode & SPI_CS_HIGH)
 119                 ctrl_reg |= MXC_CSPICTRL_SSPOL;
 120         mxcs->ctrl_reg = ctrl_reg;
 121
 122         return 0;
 123 }
 124 #endif
 125
 126 #ifdef MXC_ECSPI
 127 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 128                 unsigned int max_hz, unsigned int mode)
 129 {
 130         u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
 131         s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
 132         u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
 133         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 134
 135         if (max_hz == 0) {
 136                 printf("Error: desired clock is 0\n");
 137                 return -1;
 138         }
 139
 140         reg_ctrl = reg_read(&regs->ctrl);
 141
 142         /* Reset spi */
 143         reg_write(&regs->ctrl, 0);
 144         reg_write(&regs->ctrl, (reg_ctrl | 0x1));
 145
 146         /*
 147          * The following computation is taken directly from Freescale's code.
 148          */
 149         if (clk_src > max_hz) {
 150                 pre_div = DIV_ROUND_UP(clk_src, max_hz);
 151                 if (pre_div > 16) {
 152                         post_div = pre_div / 16;
 153                         pre_div = 15;
 154                 }
 155                 if (post_div != 0) {
 156                         for (i = 0; i < 16; i++) {
 157                                 if ((1 << i) >= post_div)
 158                                         break;
 159                         }
 160                         if (i == 16) {
 161                                 printf("Error: no divider for the freq: %d\n",
 162                                         max_hz);
 163                                 return -1;
 164                         }
 165                         post_div = i;
 166                 }
 167         }
 168
 169         debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
 170         reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
 171                 MXC_CSPICTRL_SELCHAN(cs);
 172         reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
 173                 MXC_CSPICTRL_PREDIV(pre_div);
 174         reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
 175                 MXC_CSPICTRL_POSTDIV(post_div);
 176
 177         /* always set to master mode */
 178         reg_ctrl |= 1 << (cs + 4);
 179
 180         /* We need to disable SPI before changing registers */
 181         reg_ctrl &= ~MXC_CSPICTRL_EN;
 182
 183         if (mode & SPI_CS_HIGH)
 184                 ss_pol = 1;
 185
 186         if (mode & SPI_CPOL)
 187                 sclkpol = 1;
 188
 189         if (mode & SPI_CPHA)
 190                 sclkpha = 1;
 191
 192         reg_config = reg_read(&regs->cfg);
 193
 194         /*
 195          * Configuration register setup
 196          * The MX51 supports different setup for each SS
 197          */
 198         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
 199                 (ss_pol << (cs + MXC_CSPICON_SSPOL));
 200         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
 201                 (sclkpol << (cs + MXC_CSPICON_POL));
 202         reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
 203                 (sclkpha << (cs + MXC_CSPICON_PHA));
 204
 205         debug("reg_ctrl = 0x%x\n", reg_ctrl);
 206         reg_write(&regs->ctrl, reg_ctrl);
 207         debug("reg_config = 0x%x\n", reg_config);
 208         reg_write(&regs->cfg, reg_config);
 209
 210         /* save config register and control register */
 211         mxcs->ctrl_reg = reg_ctrl;
 212         mxcs->cfg_reg = reg_config;
 213
 214         /* clear interrupt reg */
 215         reg_write(&regs->intr, 0);
 216         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
 217
 218         return 0;
 219 }
 220 #endif
 221
 222 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
 223         const u8 *dout, u8 *din, unsigned long flags)
 224 {
 225         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 226         int nbytes = (bitlen + 7) / 8;
 227         u32 data, cnt, i;
 228         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 229
 230         debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 231                 __func__, bitlen, (u32)dout, (u32)din);
 232
 233         mxcs->ctrl_reg = (mxcs->ctrl_reg &
 234                 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
 235                 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
 236
 237         reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
 238 #ifdef MXC_ECSPI
 239         reg_write(&regs->cfg, mxcs->cfg_reg);
 240 #endif
 241
 242         /* Clear interrupt register */
 243         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
 244
 245         /*
 246          * The SPI controller works only with words,
 247          * check if less than a word is sent.
 248          * Access to the FIFO is only 32 bit
 249          */
 250         if (bitlen % 32) {
 251                 data = 0;
 252                 cnt = (bitlen % 32) / 8;
 253                 if (dout) {
 254                         for (i = 0; i < cnt; i++) {
 255                                 data = (data << 8) | (*dout++ & 0xFF);
 256                         }
 257                 }
 258                 debug("Sending SPI 0x%x\n", data);
 259
 260                 reg_write(&regs->txdata, data);
 261                 nbytes -= cnt;
 262         }
 263
 264         data = 0;
 265
 266         while (nbytes > 0) {
 267                 data = 0;
 268                 if (dout) {
 269                         /* Buffer is not 32-bit aligned */
 270                         if ((unsigned long)dout & 0x03) {
 271                                 data = 0;
 272                                 for (i = 0; i < 4; i++)
 273                                         data = (data << 8) | (*dout++ & 0xFF);
 274                         } else {
 275                                 data = *(u32 *)dout;
 276                                 data = cpu_to_be32(data);
 277                         }
 278                         dout += 4;
 279                 }
 280                 debug("Sending SPI 0x%x\n", data);
 281                 reg_write(&regs->txdata, data);
 282                 nbytes -= 4;
 283         }
 284
 285         /* FIFO is written, now starts the transfer setting the XCH bit */
 286         reg_write(&regs->ctrl, mxcs->ctrl_reg |
 287                 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
 288
 289         /* Wait until the TC (Transfer completed) bit is set */
 290         while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
 291                 ;
 292
 293         /* Transfer completed, clear any pending request */
 294         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
 295
 296         nbytes = (bitlen + 7) / 8;
 297
 298         cnt = nbytes % 32;
 299
 300         if (bitlen % 32) {
 301                 data = reg_read(&regs->rxdata);
 302                 cnt = (bitlen % 32) / 8;
 303                 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
 304                 debug("SPI Rx unaligned: 0x%x\n", data);
 305                 if (din) {
 306                         memcpy(din, &data, cnt);
 307                         din += cnt;
 308                 }
 309                 nbytes -= cnt;
 310         }
 311
 312         while (nbytes > 0) {
 313                 u32 tmp;
 314                 tmp = reg_read(&regs->rxdata);
 315                 data = cpu_to_be32(tmp);
 316                 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
 317                 cnt = min(nbytes, sizeof(data));
 318                 if (din) {
 319                         memcpy(din, &data, cnt);
 320                         din += cnt;
 321                 }
 322                 nbytes -= cnt;
 323         }
 324
 325         return 0;
 326
 327 }
 328
 329 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 330                 void *din, unsigned long flags)
 331 {
 332         int n_bytes = (bitlen + 7) / 8;
 333         int n_bits;
 334         int ret;
 335         u32 blk_size;
 336         u8 *p_outbuf = (u8 *)dout;
 337         u8 *p_inbuf = (u8 *)din;
 338
 339         if (!slave)
 340                 return -1;
 341
 342         if (flags & SPI_XFER_BEGIN)
 343                 spi_cs_activate(slave);
 344
 345         while (n_bytes > 0) {
 346                 if (n_bytes < MAX_SPI_BYTES)
 347                         blk_size = n_bytes;
 348                 else
 349                         blk_size = MAX_SPI_BYTES;
 350
 351                 n_bits = blk_size * 8;
 352
 353                 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
 354
 355                 if (ret)
 356                         return ret;
 357                 if (dout)
 358                         p_outbuf += blk_size;
 359                 if (din)
 360                         p_inbuf += blk_size;
 361                 n_bytes -= blk_size;
 362         }
 363
 364         if (flags & SPI_XFER_END) {
 365                 spi_cs_deactivate(slave);
 366         }
 367
 368         return 0;
 369 }
 370
 371 void spi_init(void)
 372 {
 373 }
 374
 375 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
 376 {
 377         int ret;
 378
 379         /*
 380          * Some SPI devices require active chip-select over multiple
 381          * transactions, we achieve this using a GPIO. Still, the SPI
 382          * controller has to be configured to use one of its own chipselects.
 383          * To use this feature you have to call spi_setup_slave() with
 384          * cs = internal_cs | (gpio << 8), and you have to use some unused
 385          * on this SPI controller cs between 0 and 3.
 386          */
 387         if (cs > 3) {
 388                 mxcs->gpio = cs >> 8;
 389                 cs &= 3;
 390                 ret = gpio_direction_output(mxcs->gpio, 0);
 391                 if (ret) {
 392                         printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
 393                         return -EINVAL;
 394                 }
 395         } else {
 396                 mxcs->gpio = -1;
 397         }
 398
 399         return cs;
 400 }
 401
 402 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 403                         unsigned int max_hz, unsigned int mode)
 404 {
 405         struct mxc_spi_slave *mxcs;
 406         int ret;
 407
 408         if (bus >= ARRAY_SIZE(spi_bases))
 409                 return NULL;
 410
 411         mxcs = calloc(sizeof(struct mxc_spi_slave), 1);
 412         if (!mxcs) {
 413                 puts("mxc_spi: SPI Slave not allocated !\n");
 414                 return NULL;
 415         }
 416
 417         ret = decode_cs(mxcs, cs);
 418         if (ret < 0) {
 419                 free(mxcs);
 420                 return NULL;
 421         }
 422
 423         cs = ret;
 424
 425         mxcs->slave.bus = bus;
 426         mxcs->slave.cs = cs;
 427         mxcs->base = spi_bases[bus];
 428         mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
 429
 430         ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
 431         if (ret) {
 432                 printf("mxc_spi: cannot setup SPI controller\n");
 433                 free(mxcs);
 434                 return NULL;
 435         }
 436         return &mxcs->slave;
 437 }
 438
 439 void spi_free_slave(struct spi_slave *slave)
 440 {
 441         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 442
 443         free(mxcs);
 444 }
 445
 446 int spi_claim_bus(struct spi_slave *slave)
 447 {
 448         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 449         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 450
 451         reg_write(&regs->rxdata, 1);
 452         udelay(1);
 453         reg_write(&regs->ctrl, mxcs->ctrl_reg);
 454         reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
 455         reg_write(&regs->intr, 0);
 456
 457         return 0;
 458 }
 459
 460 void spi_release_bus(struct spi_slave *slave)
 461 {
 462         /* TODO: Shut the controller down */
 463 }