drivers/spi/mxs_spi.c

   1 /*
   2  * Freescale i.MX28 SPI driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  *
   9  * NOTE: This driver only supports the SPI-controller chipselects,
  10  *       GPIO driven chipselects are not supported.
  11  */
  12
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <memalign.h>
  16 #include <spi.h>
  17 #include <linux/errno.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/mach-imx/dma.h>
  23
  24 #define MXS_SPI_MAX_TIMEOUT     1000000
  25 #define MXS_SPI_PORT_OFFSET     0x2000
  26 #define MXS_SSP_CHIPSELECT_MASK         0x00300000
  27 #define MXS_SSP_CHIPSELECT_SHIFT        20
  28
  29 #define MXSSSP_SMALL_TRANSFER   512
  30
  31 struct mxs_spi_slave {
  32         struct spi_slave        slave;
  33         uint32_t                max_khz;
  34         uint32_t                mode;
  35         struct mxs_ssp_regs     *regs;
  36 };
  37
  38 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
  39 {
  40         return container_of(slave, struct mxs_spi_slave, slave);
  41 }
  42
  43 void spi_init(void)
  44 {
  45 }
  46
  47 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  48 {
  49         /* MXS SPI: 4 ports and 3 chip selects maximum */
  50         if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
  51                 return 0;
  52         else
  53                 return 1;
  54 }
  55
  56 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  57                                   unsigned int max_hz, unsigned int mode)
  58 {
  59         struct mxs_spi_slave *mxs_slave;
  60
  61         if (!spi_cs_is_valid(bus, cs)) {
  62                 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
  63                 return NULL;
  64         }
  65
  66         mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
  67         if (!mxs_slave)
  68                 return NULL;
  69
  70         if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
  71                 goto err_init;
  72
  73         mxs_slave->max_khz = max_hz / 1000;
  74         mxs_slave->mode = mode;
  75         mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
  76
  77         return &mxs_slave->slave;
  78
  79 err_init:
  80         free(mxs_slave);
  81         return NULL;
  82 }
  83
  84 void spi_free_slave(struct spi_slave *slave)
  85 {
  86         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
  87         free(mxs_slave);
  88 }
  89
  90 int spi_claim_bus(struct spi_slave *slave)
  91 {
  92         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
  93         struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
  94         uint32_t reg = 0;
  95
  96         mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  97
  98         writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
  99                SSP_CTRL0_BUS_WIDTH_ONE_BIT,
 100                &ssp_regs->hw_ssp_ctrl0);
 101
 102         reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
 103         reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
 104         reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
 105         writel(reg, &ssp_regs->hw_ssp_ctrl1);
 106
 107         writel(0, &ssp_regs->hw_ssp_cmd0);
 108
 109         mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
 110
 111         return 0;
 112 }
 113
 114 void spi_release_bus(struct spi_slave *slave)
 115 {
 116 }
 117
 118 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
 119 {
 120         writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
 121         writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
 122 }
 123
 124 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
 125 {
 126         writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
 127         writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
 128 }
 129
 130 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 131                         char *data, int length, int write, unsigned long flags)
 132 {
 133         struct mxs_ssp_regs *ssp_regs = slave->regs;
 134
 135         if (flags & SPI_XFER_BEGIN)
 136                 mxs_spi_start_xfer(ssp_regs);
 137
 138         while (length--) {
 139                 /* We transfer 1 byte */
 140 #if defined(CONFIG_MX23)
 141                 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
 142                 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
 143 #elif defined(CONFIG_MX28)
 144                 writel(1, &ssp_regs->hw_ssp_xfer_size);
 145 #endif
 146
 147                 if ((flags & SPI_XFER_END) && !length)
 148                         mxs_spi_end_xfer(ssp_regs);
 149
 150                 if (write)
 151                         writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
 152                 else
 153                         writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
 154
 155                 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
 156
 157                 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
 158                         SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 159                         printf("MXS SPI: Timeout waiting for start\n");
 160                         return -ETIMEDOUT;
 161                 }
 162
 163                 if (write)
 164                         writel(*data++, &ssp_regs->hw_ssp_data);
 165
 166                 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
 167
 168                 if (!write) {
 169                         if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
 170                                 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
 171                                 printf("MXS SPI: Timeout waiting for data\n");
 172                                 return -ETIMEDOUT;
 173                         }
 174
 175                         *data = readl(&ssp_regs->hw_ssp_data);
 176                         data++;
 177                 }
 178
 179                 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
 180                         SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 181                         printf("MXS SPI: Timeout waiting for finish\n");
 182                         return -ETIMEDOUT;
 183                 }
 184         }
 185
 186         return 0;
 187 }
 188
 189 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 190                         char *data, int length, int write, unsigned long flags)
 191 {
 192         const int xfer_max_sz = 0xff00;
 193         const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
 194         struct mxs_ssp_regs *ssp_regs = slave->regs;
 195         struct mxs_dma_desc *dp;
 196         uint32_t ctrl0;
 197         uint32_t cache_data_count;
 198         const uint32_t dstart = (uint32_t)data;
 199         int dmach;
 200         int tl;
 201         int ret = 0;
 202
 203 #if defined(CONFIG_MX23)
 204         const int mxs_spi_pio_words = 1;
 205 #elif defined(CONFIG_MX28)
 206         const int mxs_spi_pio_words = 4;
 207 #endif
 208
 209         ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 210
 211         memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
 212
 213         ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
 214         ctrl0 |= SSP_CTRL0_DATA_XFER;
 215
 216         if (flags & SPI_XFER_BEGIN)
 217                 ctrl0 |= SSP_CTRL0_LOCK_CS;
 218         if (!write)
 219                 ctrl0 |= SSP_CTRL0_READ;
 220
 221         if (length % ARCH_DMA_MINALIGN)
 222                 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
 223         else
 224                 cache_data_count = length;
 225
 226         /* Flush data to DRAM so DMA can pick them up */
 227         if (write)
 228                 flush_dcache_range(dstart, dstart + cache_data_count);
 229
 230         /* Invalidate the area, so no writeback into the RAM races with DMA */
 231         invalidate_dcache_range(dstart, dstart + cache_data_count);
 232
 233         dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
 234
 235         dp = desc;
 236         while (length) {
 237                 dp->address = (dma_addr_t)dp;
 238                 dp->cmd.address = (dma_addr_t)data;
 239
 240                 /*
 241                  * This is correct, even though it does indeed look insane.
 242                  * I hereby have to, wholeheartedly, thank Freescale Inc.,
 243                  * for always inventing insane hardware and keeping me busy
 244                  * and employed ;-)
 245                  */
 246                 if (write)
 247                         dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 248                 else
 249                         dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 250
 251                 /*
 252                  * The DMA controller can transfer large chunks (64kB) at
 253                  * time by setting the transfer length to 0. Setting tl to
 254                  * 0x10000 will overflow below and make .data contain 0.
 255                  * Otherwise, 0xff00 is the transfer maximum.
 256                  */
 257                 if (length >= 0x10000)
 258                         tl = 0x10000;
 259                 else
 260                         tl = min(length, xfer_max_sz);
 261
 262                 dp->cmd.data |=
 263                         ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
 264                         (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 265                         MXS_DMA_DESC_HALT_ON_TERMINATE |
 266                         MXS_DMA_DESC_TERMINATE_FLUSH;
 267
 268                 data += tl;
 269                 length -= tl;
 270
 271                 if (!length) {
 272                         dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 273
 274                         if (flags & SPI_XFER_END) {
 275                                 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
 276                                 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 277                         }
 278                 }
 279
 280                 /*
 281                  * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
 282                  * case of MX28, write only CTRL0 in case of MX23 due
 283                  * to the difference in register layout. It is utterly
 284                  * essential that the XFER_SIZE register is written on
 285                  * a per-descriptor basis with the same size as is the
 286                  * descriptor!
 287                  */
 288                 dp->cmd.pio_words[0] = ctrl0;
 289 #ifdef CONFIG_MX28
 290                 dp->cmd.pio_words[1] = 0;
 291                 dp->cmd.pio_words[2] = 0;
 292                 dp->cmd.pio_words[3] = tl;
 293 #endif
 294
 295                 mxs_dma_desc_append(dmach, dp);
 296
 297                 dp++;
 298         }
 299
 300         if (mxs_dma_go(dmach))
 301                 ret = -EINVAL;
 302
 303         /* The data arrived into DRAM, invalidate cache over them */
 304         if (!write)
 305                 invalidate_dcache_range(dstart, dstart + cache_data_count);
 306
 307         return ret;
 308 }
 309
 310 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 311                 const void *dout, void *din, unsigned long flags)
 312 {
 313         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 314         struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 315         int len = bitlen / 8;
 316         char dummy;
 317         int write = 0;
 318         char *data = NULL;
 319         int dma = 1;
 320
 321         if (bitlen == 0) {
 322                 if (flags & SPI_XFER_END) {
 323                         din = (void *)&dummy;
 324                         len = 1;
 325                 } else
 326                         return 0;
 327         }
 328
 329         /* Half-duplex only */
 330         if (din && dout)
 331                 return -EINVAL;
 332         /* No data */
 333         if (!din && !dout)
 334                 return 0;
 335
 336         if (dout) {
 337                 data = (char *)dout;
 338                 write = 1;
 339         } else if (din) {
 340                 data = (char *)din;
 341                 write = 0;
 342         }
 343
 344         /*
 345          * Check for alignment, if the buffer is aligned, do DMA transfer,
 346          * PIO otherwise. This is a temporary workaround until proper bounce
 347          * buffer is in place.
 348          */
 349         if (dma) {
 350                 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
 351                         dma = 0;
 352                 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
 353                         dma = 0;
 354         }
 355
 356         if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
 357                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 358                 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
 359         } else {
 360                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 361                 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
 362         }
 363 }