drivers/spi/rk_spi.c

   1 /*
   2  * spi driver for rockchip
   3  *
   4  * (C) Copyright 2015 Google, Inc
   5  *
   6  * (C) Copyright 2008-2013 Rockchip Electronics
   7  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <spi.h>
  17 #include <asm/errno.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/periph.h>
  21 #include <dm/pinctrl.h>
  22 #include "rk_spi.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* Change to 1 to output registers at the start of each transaction */
  27 #define DEBUG_RK_SPI    0
  28
  29 struct rockchip_spi_platdata {
  30         int periph_id;
  31         struct udevice *pinctrl;
  32         s32 frequency;          /* Default clock frequency, -1 for none */
  33         fdt_addr_t base;
  34         uint deactivate_delay_us;       /* Delay to wait after deactivate */
  35 };
  36
  37 struct rockchip_spi_priv {
  38         struct rockchip_spi *regs;
  39         struct udevice *clk;
  40         int clk_id;
  41         unsigned int max_freq;
  42         unsigned int mode;
  43         ulong last_transaction_us;      /* Time of last transaction end */
  44         u8 bits_per_word;               /* max 16 bits per word */
  45         u8 n_bytes;
  46         unsigned int speed_hz;
  47         unsigned int tmode;
  48         uint input_rate;
  49 };
  50
  51 #define SPI_FIFO_DEPTH          32
  52
  53 static void rkspi_dump_regs(struct rockchip_spi *regs)
  54 {
  55         debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  56         debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  57         debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  58         debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  59         debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  60         debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  61         debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  62         debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  63         debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  64         debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  65         debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  66         debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  67         debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  68         debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  69         debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  70 }
  71
  72 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  73 {
  74         writel(enable ? 1 : 0, &regs->enr);
  75 }
  76
  77 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  78 {
  79         uint clk_div;
  80
  81         clk_div = clk_get_divisor(priv->input_rate, speed);
  82         debug("spi speed %u, div %u\n", speed, clk_div);
  83
  84         writel(clk_div, &priv->regs->baudr);
  85 }
  86
  87 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
  88 {
  89         unsigned long start;
  90
  91         start = get_timer(0);
  92         while (readl(&regs->sr) & SR_BUSY) {
  93                 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
  94                         debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
  95                         return -ETIMEDOUT;
  96                 }
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
 103 {
 104         debug("activate cs%u\n", cs);
 105         writel(1 << cs, &regs->ser);
 106 }
 107
 108 static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
 109 {
 110         debug("deactivate cs%u\n", cs);
 111         writel(0, &regs->ser);
 112 }
 113
 114 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 115 {
 116         struct rockchip_spi_platdata *plat = bus->platdata;
 117         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 118         const void *blob = gd->fdt_blob;
 119         int node = bus->of_offset;
 120         int ret;
 121
 122         plat->base = dev_get_addr(bus);
 123         ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
 124         if (ret)
 125                 return ret;
 126         ret = pinctrl_get_periph_id(plat->pinctrl, bus);
 127
 128         if (ret < 0) {
 129                 debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
 130                       bus->name, ret);
 131                 return ret;
 132         }
 133         plat->periph_id = ret;
 134         ret = clk_get_by_index(bus, 0, &priv->clk);
 135         if (ret < 0) {
 136                 debug("%s: Could not get clock for %s: %d\n", __func__,
 137                       bus->name, ret);
 138                 return ret;
 139         }
 140         priv->clk_id = ret;
 141
 142         plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 143                                          50000000);
 144         plat->deactivate_delay_us = fdtdec_get_int(blob, node,
 145                                         "spi-deactivate-delay", 0);
 146         debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
 147               __func__, (uint)plat->base, plat->periph_id, plat->frequency,
 148               plat->deactivate_delay_us);
 149
 150         return 0;
 151 }
 152
 153 static int rockchip_spi_probe(struct udevice *bus)
 154 {
 155         struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 156         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 157         int ret;
 158
 159         debug("%s: probe\n", __func__);
 160         priv->regs = (struct rockchip_spi *)plat->base;
 161
 162         priv->last_transaction_us = timer_get_us();
 163         priv->max_freq = plat->frequency;
 164
 165         /*
 166          * Use 99 MHz as our clock since it divides nicely into 594 MHz which
 167          * is the assumed speed for CLK_GENERAL.
 168          */
 169         ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
 170         if (ret < 0) {
 171                 debug("%s: Failed to set clock: %d\n", __func__, ret);
 172                 return ret;
 173         }
 174         priv->input_rate = ret;
 175         debug("%s: rate = %u\n", __func__, priv->input_rate);
 176         priv->bits_per_word = 8;
 177         priv->tmode = TMOD_TR; /* Tx & Rx */
 178
 179         return 0;
 180 }
 181
 182 static int rockchip_spi_claim_bus(struct udevice *dev)
 183 {
 184         struct udevice *bus = dev->parent;
 185         struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 186         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 187         struct rockchip_spi *regs = priv->regs;
 188         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 189         u8 spi_dfs, spi_tf;
 190         uint ctrlr0;
 191         int ret;
 192
 193         /* Disable the SPI hardware */
 194         rkspi_enable_chip(regs, 0);
 195
 196         switch (priv->bits_per_word) {
 197         case 8:
 198                 priv->n_bytes = 1;
 199                 spi_dfs = DFS_8BIT;
 200                 spi_tf = HALF_WORD_OFF;
 201                 break;
 202         case 16:
 203                 priv->n_bytes = 2;
 204                 spi_dfs = DFS_16BIT;
 205                 spi_tf = HALF_WORD_ON;
 206                 break;
 207         default:
 208                 debug("%s: unsupported bits: %dbits\n", __func__,
 209                       priv->bits_per_word);
 210                 return -EPROTONOSUPPORT;
 211         }
 212
 213         rkspi_set_clk(priv, priv->speed_hz);
 214
 215         /* Operation Mode */
 216         ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
 217
 218         /* Data Frame Size */
 219         ctrlr0 |= spi_dfs & DFS_MASK << DFS_SHIFT;
 220
 221         /* set SPI mode 0..3 */
 222         if (priv->mode & SPI_CPOL)
 223                 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
 224         if (priv->mode & SPI_CPHA)
 225                 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
 226
 227         /* Chip Select Mode */
 228         ctrlr0 |= CSM_KEEP << CSM_SHIFT;
 229
 230         /* SSN to Sclk_out delay */
 231         ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
 232
 233         /* Serial Endian Mode */
 234         ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
 235
 236         /* First Bit Mode */
 237         ctrlr0 |= FBM_MSB << FBM_SHIFT;
 238
 239         /* Byte and Halfword Transform */
 240         ctrlr0 |= (spi_tf & HALF_WORD_MASK) << HALF_WORD_TX_SHIFT;
 241
 242         /* Rxd Sample Delay */
 243         ctrlr0 |= 0 << RXDSD_SHIFT;
 244
 245         /* Frame Format */
 246         ctrlr0 |= FRF_SPI << FRF_SHIFT;
 247
 248         /* Tx and Rx mode */
 249         ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 250
 251         writel(ctrlr0, &regs->ctrlr0);
 252
 253         ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
 254         if (ret) {
 255                 debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
 256                 return ret;
 257         }
 258
 259         return 0;
 260 }
 261
 262 static int rockchip_spi_release_bus(struct udevice *dev)
 263 {
 264         return 0;
 265 }
 266
 267 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
 268                            const void *dout, void *din, unsigned long flags)
 269 {
 270         struct udevice *bus = dev->parent;
 271         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 272         struct rockchip_spi *regs = priv->regs;
 273         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 274         int len = bitlen >> 3;
 275         const u8 *out = dout;
 276         u8 *in = din;
 277         int toread, towrite;
 278         int ret;
 279
 280         debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
 281               len, flags);
 282         if (DEBUG_RK_SPI)
 283                 rkspi_dump_regs(regs);
 284
 285         /* Assert CS before transfer */
 286         if (flags & SPI_XFER_BEGIN)
 287                 spi_cs_activate(regs, slave_plat->cs);
 288
 289         while (len > 0) {
 290                 int todo = min(len, 0xffff);
 291
 292                 rkspi_enable_chip(regs, true);
 293                 writel(todo - 1, &regs->ctrlr1);
 294                 rkspi_enable_chip(regs, true);
 295
 296                 toread = todo;
 297                 towrite = todo;
 298                 while (toread || towrite) {
 299                         u32 status = readl(&regs->sr);
 300
 301                         if (towrite && !(status & SR_TF_FULL)) {
 302                                 writel(out ? *out++ : 0, regs->txdr);
 303                                 towrite--;
 304                         }
 305                         if (toread && !(status & SR_RF_EMPT)) {
 306                                 u32 byte = readl(regs->rxdr);
 307
 308                                 if (in)
 309                                         *in++ = byte;
 310                                 toread--;
 311                         }
 312                 }
 313                 ret = rkspi_wait_till_not_busy(regs);
 314                 if (ret)
 315                         break;
 316                 len -= todo;
 317         }
 318
 319         /* Deassert CS after transfer */
 320         if (flags & SPI_XFER_END)
 321                 spi_cs_deactivate(regs, slave_plat->cs);
 322
 323         rkspi_enable_chip(regs, false);
 324
 325         return ret;
 326 }
 327
 328 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
 329 {
 330         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 331
 332         if (speed > ROCKCHIP_SPI_MAX_RATE)
 333                 return -EINVAL;
 334         if (speed > priv->max_freq)
 335                 speed = priv->max_freq;
 336         priv->speed_hz = speed;
 337
 338         return 0;
 339 }
 340
 341 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
 342 {
 343         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 344
 345         priv->mode = mode;
 346
 347         return 0;
 348 }
 349
 350 static const struct dm_spi_ops rockchip_spi_ops = {
 351         .claim_bus      = rockchip_spi_claim_bus,
 352         .release_bus    = rockchip_spi_release_bus,
 353         .xfer           = rockchip_spi_xfer,
 354         .set_speed      = rockchip_spi_set_speed,
 355         .set_mode       = rockchip_spi_set_mode,
 356         /*
 357          * cs_info is not needed, since we require all chip selects to be
 358          * in the device tree explicitly
 359          */
 360 };
 361
 362 static const struct udevice_id rockchip_spi_ids[] = {
 363         { .compatible = "rockchip,rk3288-spi" },
 364         { }
 365 };
 366
 367 U_BOOT_DRIVER(rockchip_spi) = {
 368         .name   = "rockchip_spi",
 369         .id     = UCLASS_SPI,
 370         .of_match = rockchip_spi_ids,
 371         .ops    = &rockchip_spi_ops,
 372         .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
 373         .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
 374         .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
 375         .probe  = rockchip_spi_probe,
 376 };