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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/spi/rk_spi.h
2 * SPI driver for rockchip
4 * (C) Copyright 2015 Google, Inc
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 * SPDX-License-Identifier: GPL-2.0+
33 u32 dmardlr
; /* 0x44 */
35 u32 txdr
[0x100]; /* 0x400 */
36 u32 rxdr
[0x100]; /* 0x800 */
41 DFS_SHIFT
= 0, /* Data Frame Size */
48 CFS_SHIFT
= 2, /* Control Frame Size */
51 SCPH_SHIFT
= 6, /* Serial Clock Phase */
53 SCPH_TOGMID
= 0, /* SCLK toggles in middle of first data bit */
54 SCPH_TOGSTA
, /* SCLK toggles at start of first data bit */
56 SCOL_SHIFT
= 7, /* Serial Clock Polarity */
58 SCOL_LOW
= 0, /* Inactive state of serial clock is low */
59 SCOL_HIGH
, /* Inactive state of serial clock is high */
61 CSM_SHIFT
= 8, /* Chip Select Mode */
63 CSM_KEEP
= 0, /* ss_n stays low after each frame */
64 CSM_HALF
, /* ss_n high for half sclk_out cycles */
65 CSM_ONE
, /* ss_n high for one sclk_out cycle */
68 SSN_DELAY_SHIFT
= 10, /* SSN to Sclk_out delay */
70 SSN_DELAY_HALF
= 0, /* 1/2 sclk_out cycle */
71 SSN_DELAY_ONE
= 1, /* 1 sclk_out cycle */
73 SEM_SHIFT
= 11, /* Serial Endian Mode */
75 SEM_LITTLE
= 0, /* little endian */
76 SEM_BIG
, /* big endian */
78 FBM_SHIFT
= 12, /* First Bit Mode */
80 FBM_MSB
= 0, /* first bit is MSB */
81 FBM_LSB
, /* first bit in LSB */
83 HALF_WORD_TX_SHIFT
= 13, /* Byte and Halfword Transform */
85 HALF_WORD_ON
= 0, /* apb 16bit write/read, spi 8bit write/read */
86 HALF_WORD_OFF
, /* apb 8bit write/read, spi 8bit write/read */
88 RXDSD_SHIFT
= 14, /* Rxd Sample Delay, in cycles */
91 FRF_SHIFT
= 16, /* Frame Format */
93 FRF_SPI
= 0, /* Motorola SPI */
94 FRF_SSP
, /* Texas Instruments SSP*/
95 FRF_MICROWIRE
, /* National Semiconductors Microwire */
98 TMOD_SHIFT
= 18, /* Transfer Mode */
100 TMOD_TR
= 0, /* xmit & recv */
101 TMOD_TO
, /* xmit only */
102 TMOD_RO
, /* recv only */
105 OMOD_SHIFT
= 20, /* Operation Mode */
107 OMOD_MASTER
= 0, /* Master Mode */
108 OMOD_SLAVE
, /* Slave Mode */
121 #define ROCKCHIP_SPI_TIMEOUT_MS 1000
122 #define ROCKCHIP_SPI_MAX_RATE 48000000
124 #endif /* __RK_SPI_H */