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git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/spi/sh_qspi.c
2 * SH QSPI (Quad SPI) driver
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
14 #include <asm/arch/rmobile.h>
17 /* SH QSPI register bit masks <REG>_<BIT> */
18 #define SPCR_MSTR 0x08
20 #define SPSR_SPRFF 0x80
21 #define SPSR_SPTEF 0x20
22 #define SPPCR_IO3FV 0x04
23 #define SPPCR_IO2FV 0x02
24 #define SPPCR_IO1FV 0x01
25 #define SPBDCR_RXBC0 BIT(0)
26 #define SPCMD_SCKDEN BIT(15)
27 #define SPCMD_SLNDEN BIT(14)
28 #define SPCMD_SPNDEN BIT(13)
29 #define SPCMD_SSLKP BIT(7)
30 #define SPCMD_BRDV0 BIT(2)
31 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
32 SPCMD_SPNDEN | SPCMD_SSLKP | \
34 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
36 #define SPBFCR_TXRST BIT(7)
37 #define SPBFCR_RXRST BIT(6)
39 /* SH QSPI register set */
54 unsigned short spcmd0
;
55 unsigned short spcmd1
;
56 unsigned short spcmd2
;
57 unsigned short spcmd3
;
60 unsigned short spbdcr
;
61 unsigned long spbmul0
;
62 unsigned long spbmul1
;
63 unsigned long spbmul2
;
64 unsigned long spbmul3
;
67 struct sh_qspi_slave
{
68 struct spi_slave slave
;
69 struct sh_qspi_regs
*regs
;
72 static inline struct sh_qspi_slave
*to_sh_qspi(struct spi_slave
*slave
)
74 return container_of(slave
, struct sh_qspi_slave
, slave
);
77 static void sh_qspi_init(struct sh_qspi_slave
*ss
)
80 /* Set master mode only */
81 writeb(SPCR_MSTR
, &ss
->regs
->spcr
);
83 /* Set SSL signal level */
84 writeb(0x00, &ss
->regs
->sslp
);
86 /* Set MOSI signal value when transfer is in idle state */
87 writeb(SPPCR_IO3FV
|SPPCR_IO2FV
, &ss
->regs
->sppcr
);
89 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
90 writeb(0x01, &ss
->regs
->spbr
);
92 /* Disable Dummy Data Transmission */
93 writeb(0x00, &ss
->regs
->spdcr
);
95 /* Set clock delay value */
96 writeb(0x00, &ss
->regs
->spckd
);
98 /* Set SSL negation delay value */
99 writeb(0x00, &ss
->regs
->sslnd
);
101 /* Set next-access delay value */
102 writeb(0x00, &ss
->regs
->spnd
);
104 /* Set equence command */
105 writew(SPCMD_INIT2
, &ss
->regs
->spcmd0
);
107 /* Reset transfer and receive Buffer */
108 setbits_8(&ss
->regs
->spbfcr
, SPBFCR_TXRST
|SPBFCR_RXRST
);
110 /* Clear transfer and receive Buffer control bit */
111 clrbits_8(&ss
->regs
->spbfcr
, SPBFCR_TXRST
|SPBFCR_RXRST
);
113 /* Set equence control method. Use equence0 only */
114 writeb(0x00, &ss
->regs
->spscr
);
116 /* Enable SPI function */
117 setbits_8(&ss
->regs
->spcr
, SPCR_SPE
);
120 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
125 void spi_cs_activate(struct spi_slave
*slave
)
127 struct sh_qspi_slave
*ss
= to_sh_qspi(slave
);
129 /* Set master mode only */
130 writeb(SPCR_MSTR
, &ss
->regs
->spcr
);
133 writew(SPCMD_INIT1
, &ss
->regs
->spcmd0
);
135 /* Reset transfer and receive Buffer */
136 setbits_8(&ss
->regs
->spbfcr
, SPBFCR_TXRST
|SPBFCR_RXRST
);
138 /* Clear transfer and receive Buffer control bit */
139 clrbits_8(&ss
->regs
->spbfcr
, SPBFCR_TXRST
|SPBFCR_RXRST
);
141 /* Set equence control method. Use equence0 only */
142 writeb(0x00, &ss
->regs
->spscr
);
144 /* Enable SPI function */
145 setbits_8(&ss
->regs
->spcr
, SPCR_SPE
);
148 void spi_cs_deactivate(struct spi_slave
*slave
)
150 struct sh_qspi_slave
*ss
= to_sh_qspi(slave
);
152 /* Disable SPI Function */
153 clrbits_8(&ss
->regs
->spcr
, SPCR_SPE
);
161 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
162 unsigned int max_hz
, unsigned int mode
)
164 struct sh_qspi_slave
*ss
;
166 if (!spi_cs_is_valid(bus
, cs
))
169 ss
= spi_alloc_slave(struct sh_qspi_slave
, bus
, cs
);
171 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
175 ss
->regs
= (struct sh_qspi_regs
*)SH_QSPI_BASE
;
183 void spi_free_slave(struct spi_slave
*slave
)
185 struct sh_qspi_slave
*spi
= to_sh_qspi(slave
);
190 int spi_claim_bus(struct spi_slave
*slave
)
195 void spi_release_bus(struct spi_slave
*slave
)
199 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
, const void *dout
,
200 void *din
, unsigned long flags
)
202 struct sh_qspi_slave
*ss
= to_sh_qspi(slave
);
205 unsigned char dtdata
= 0, drdata
;
206 unsigned char *tdata
= &dtdata
, *rdata
= &drdata
;
207 unsigned long *spbmul0
= &ss
->regs
->spbmul0
;
209 if (dout
== NULL
&& din
== NULL
) {
210 if (flags
& SPI_XFER_END
)
211 spi_cs_deactivate(slave
);
216 printf("%s: bitlen is not 8bit alined %d", __func__
, bitlen
);
222 if (flags
& SPI_XFER_BEGIN
) {
223 spi_cs_activate(slave
);
225 /* Set 1048576 byte */
226 writel(0x100000, spbmul0
);
229 if (flags
& SPI_XFER_END
)
230 writel(nbyte
, spbmul0
);
233 tdata
= (unsigned char *)dout
;
239 while (!(readb(&ss
->regs
->spsr
) & SPSR_SPTEF
)) {
247 writeb(*tdata
, (unsigned char *)(&ss
->regs
->spdr
));
249 while ((readw(&ss
->regs
->spbdcr
) != SPBDCR_RXBC0
)) {
257 while (!(readb(&ss
->regs
->spsr
) & SPSR_SPRFF
)) {
265 *rdata
= readb((unsigned char *)(&ss
->regs
->spdr
));
275 if (flags
& SPI_XFER_END
)
276 spi_cs_deactivate(slave
);