1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for AT91 USART Controllers as SPI
5 // Copyright (C) 2018 Microchip Technology Inc.
7 // Author: Radu Pirea <radu.pirea@microchip.com>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
29 #define US_VERSION 0xFC
31 #define US_CR_RSTRX BIT(2)
32 #define US_CR_RSTTX BIT(3)
33 #define US_CR_RXEN BIT(4)
34 #define US_CR_RXDIS BIT(5)
35 #define US_CR_TXEN BIT(6)
36 #define US_CR_TXDIS BIT(7)
38 #define US_MR_SPI_MASTER 0x0E
39 #define US_MR_CHRL GENMASK(7, 6)
40 #define US_MR_CPHA BIT(8)
41 #define US_MR_CPOL BIT(16)
42 #define US_MR_CLKO BIT(18)
43 #define US_MR_WRDBT BIT(20)
44 #define US_MR_LOOP BIT(15)
46 #define US_IR_RXRDY BIT(0)
47 #define US_IR_TXRDY BIT(1)
48 #define US_IR_OVRE BIT(5)
50 #define US_BRGR_SIZE BIT(16)
52 #define US_MIN_CLK_DIV 0x06
53 #define US_MAX_CLK_DIV BIT(16)
55 #define US_RESET (US_CR_RSTRX | US_CR_RSTTX)
56 #define US_DISABLE (US_CR_RXDIS | US_CR_TXDIS)
57 #define US_ENABLE (US_CR_RXEN | US_CR_TXEN)
58 #define US_OVRE_RXRDY_IRQS (US_IR_OVRE | US_IR_RXRDY)
61 (US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT)
63 /* Register access macros */
64 #define at91_usart_spi_readl(port, reg) \
65 readl_relaxed((port)->regs + US_##reg)
66 #define at91_usart_spi_writel(port, reg, value) \
67 writel_relaxed((value), (port)->regs + US_##reg)
69 #define at91_usart_spi_readb(port, reg) \
70 readb_relaxed((port)->regs + US_##reg)
71 #define at91_usart_spi_writeb(port, reg, value) \
72 writeb_relaxed((value), (port)->regs + US_##reg)
74 struct at91_usart_spi
{
75 struct spi_transfer
*current_transfer
;
80 /*used in interrupt to protect data reading*/
84 unsigned int current_tx_remaining_bytes
;
85 unsigned int current_rx_remaining_bytes
;
93 static inline u32
at91_usart_spi_tx_ready(struct at91_usart_spi
*aus
)
95 return aus
->status
& US_IR_TXRDY
;
98 static inline u32
at91_usart_spi_rx_ready(struct at91_usart_spi
*aus
)
100 return aus
->status
& US_IR_RXRDY
;
103 static inline u32
at91_usart_spi_check_overrun(struct at91_usart_spi
*aus
)
105 return aus
->status
& US_IR_OVRE
;
108 static inline u32
at91_usart_spi_read_status(struct at91_usart_spi
*aus
)
110 aus
->status
= at91_usart_spi_readl(aus
, CSR
);
114 static inline void at91_usart_spi_tx(struct at91_usart_spi
*aus
)
116 unsigned int len
= aus
->current_transfer
->len
;
117 unsigned int remaining
= aus
->current_tx_remaining_bytes
;
118 const u8
*tx_buf
= aus
->current_transfer
->tx_buf
;
123 if (at91_usart_spi_tx_ready(aus
)) {
124 at91_usart_spi_writeb(aus
, THR
, tx_buf
[len
- remaining
]);
125 aus
->current_tx_remaining_bytes
--;
129 static inline void at91_usart_spi_rx(struct at91_usart_spi
*aus
)
131 int len
= aus
->current_transfer
->len
;
132 int remaining
= aus
->current_rx_remaining_bytes
;
133 u8
*rx_buf
= aus
->current_transfer
->rx_buf
;
138 rx_buf
[len
- remaining
] = at91_usart_spi_readb(aus
, RHR
);
139 aus
->current_rx_remaining_bytes
--;
143 at91_usart_spi_set_xfer_speed(struct at91_usart_spi
*aus
,
144 struct spi_transfer
*xfer
)
146 at91_usart_spi_writel(aus
, BRGR
,
147 DIV_ROUND_UP(aus
->spi_clk
, xfer
->speed_hz
));
150 static irqreturn_t
at91_usart_spi_interrupt(int irq
, void *dev_id
)
152 struct spi_controller
*controller
= dev_id
;
153 struct at91_usart_spi
*aus
= spi_master_get_devdata(controller
);
155 spin_lock(&aus
->lock
);
156 at91_usart_spi_read_status(aus
);
158 if (at91_usart_spi_check_overrun(aus
)) {
159 aus
->xfer_failed
= true;
160 at91_usart_spi_writel(aus
, IDR
, US_IR_OVRE
| US_IR_RXRDY
);
161 spin_unlock(&aus
->lock
);
165 if (at91_usart_spi_rx_ready(aus
)) {
166 at91_usart_spi_rx(aus
);
167 spin_unlock(&aus
->lock
);
171 spin_unlock(&aus
->lock
);
176 static int at91_usart_spi_setup(struct spi_device
*spi
)
178 struct at91_usart_spi
*aus
= spi_master_get_devdata(spi
->controller
);
179 u32
*ausd
= spi
->controller_state
;
180 unsigned int mr
= at91_usart_spi_readl(aus
, MR
);
181 u8 bits
= spi
->bits_per_word
;
184 dev_dbg(&spi
->dev
, "Only 8 bits per word are supported\n");
188 if (spi
->mode
& SPI_CPOL
)
193 if (spi
->mode
& SPI_CPHA
)
198 if (spi
->mode
& SPI_LOOP
)
204 ausd
= kzalloc(sizeof(*ausd
), GFP_KERNEL
);
208 spi
->controller_state
= ausd
;
214 "setup: bpw %u mode 0x%x -> mr %d %08x\n",
215 bits
, spi
->mode
, spi
->chip_select
, mr
);
220 static int at91_usart_spi_transfer_one(struct spi_controller
*ctlr
,
221 struct spi_device
*spi
,
222 struct spi_transfer
*xfer
)
224 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctlr
);
226 at91_usart_spi_set_xfer_speed(aus
, xfer
);
227 aus
->xfer_failed
= false;
228 aus
->current_transfer
= xfer
;
229 aus
->current_tx_remaining_bytes
= xfer
->len
;
230 aus
->current_rx_remaining_bytes
= xfer
->len
;
232 while ((aus
->current_tx_remaining_bytes
||
233 aus
->current_rx_remaining_bytes
) && !aus
->xfer_failed
) {
234 at91_usart_spi_read_status(aus
);
235 at91_usart_spi_tx(aus
);
239 if (aus
->xfer_failed
) {
240 dev_err(aus
->dev
, "Overrun!\n");
247 static int at91_usart_spi_prepare_message(struct spi_controller
*ctlr
,
248 struct spi_message
*message
)
250 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctlr
);
251 struct spi_device
*spi
= message
->spi
;
252 u32
*ausd
= spi
->controller_state
;
254 at91_usart_spi_writel(aus
, CR
, US_ENABLE
);
255 at91_usart_spi_writel(aus
, IER
, US_OVRE_RXRDY_IRQS
);
256 at91_usart_spi_writel(aus
, MR
, *ausd
);
261 static int at91_usart_spi_unprepare_message(struct spi_controller
*ctlr
,
262 struct spi_message
*message
)
264 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctlr
);
266 at91_usart_spi_writel(aus
, CR
, US_RESET
| US_DISABLE
);
267 at91_usart_spi_writel(aus
, IDR
, US_OVRE_RXRDY_IRQS
);
272 static void at91_usart_spi_cleanup(struct spi_device
*spi
)
274 struct at91_usart_spi_device
*ausd
= spi
->controller_state
;
276 spi
->controller_state
= NULL
;
280 static void at91_usart_spi_init(struct at91_usart_spi
*aus
)
282 at91_usart_spi_writel(aus
, MR
, US_INIT
);
283 at91_usart_spi_writel(aus
, CR
, US_RESET
| US_DISABLE
);
286 static int at91_usart_gpio_setup(struct platform_device
*pdev
)
288 struct device_node
*np
= pdev
->dev
.parent
->of_node
;
296 nb
= of_gpio_named_count(np
, "cs-gpios");
297 for (i
= 0; i
< nb
; i
++) {
298 int cs_gpio
= of_get_named_gpio(np
, "cs-gpios", i
);
303 if (gpio_is_valid(cs_gpio
)) {
304 ret
= devm_gpio_request_one(&pdev
->dev
, cs_gpio
,
306 dev_name(&pdev
->dev
));
315 static int at91_usart_spi_probe(struct platform_device
*pdev
)
317 struct resource
*regs
;
318 struct spi_controller
*controller
;
319 struct at91_usart_spi
*aus
;
324 regs
= platform_get_resource(to_platform_device(pdev
->dev
.parent
),
329 irq
= platform_get_irq(to_platform_device(pdev
->dev
.parent
), 0);
333 clk
= devm_clk_get(pdev
->dev
.parent
, "usart");
338 controller
= spi_alloc_master(&pdev
->dev
, sizeof(*aus
));
340 goto at91_usart_spi_probe_fail
;
342 ret
= at91_usart_gpio_setup(pdev
);
344 goto at91_usart_spi_probe_fail
;
346 controller
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LOOP
| SPI_CS_HIGH
;
347 controller
->dev
.of_node
= pdev
->dev
.parent
->of_node
;
348 controller
->bits_per_word_mask
= SPI_BPW_MASK(8);
349 controller
->setup
= at91_usart_spi_setup
;
350 controller
->flags
= SPI_MASTER_MUST_RX
| SPI_MASTER_MUST_TX
;
351 controller
->transfer_one
= at91_usart_spi_transfer_one
;
352 controller
->prepare_message
= at91_usart_spi_prepare_message
;
353 controller
->unprepare_message
= at91_usart_spi_unprepare_message
;
354 controller
->cleanup
= at91_usart_spi_cleanup
;
355 controller
->max_speed_hz
= DIV_ROUND_UP(clk_get_rate(clk
),
357 controller
->min_speed_hz
= DIV_ROUND_UP(clk_get_rate(clk
),
359 platform_set_drvdata(pdev
, controller
);
361 aus
= spi_master_get_devdata(controller
);
363 aus
->dev
= &pdev
->dev
;
364 aus
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
365 if (IS_ERR(aus
->regs
)) {
366 ret
= PTR_ERR(aus
->regs
);
367 goto at91_usart_spi_probe_fail
;
373 ret
= devm_request_irq(&pdev
->dev
, irq
, at91_usart_spi_interrupt
, 0,
374 dev_name(&pdev
->dev
), controller
);
376 goto at91_usart_spi_probe_fail
;
378 ret
= clk_prepare_enable(clk
);
380 goto at91_usart_spi_probe_fail
;
382 aus
->spi_clk
= clk_get_rate(clk
);
383 at91_usart_spi_init(aus
);
385 spin_lock_init(&aus
->lock
);
386 ret
= devm_spi_register_master(&pdev
->dev
, controller
);
388 goto at91_usart_fail_register_master
;
391 "AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
392 at91_usart_spi_readl(aus
, VERSION
),
397 at91_usart_fail_register_master
:
398 clk_disable_unprepare(clk
);
399 at91_usart_spi_probe_fail
:
400 spi_master_put(controller
);
404 __maybe_unused
static int at91_usart_spi_runtime_suspend(struct device
*dev
)
406 struct spi_controller
*ctlr
= dev_get_drvdata(dev
);
407 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctlr
);
409 clk_disable_unprepare(aus
->clk
);
410 pinctrl_pm_select_sleep_state(dev
);
415 __maybe_unused
static int at91_usart_spi_runtime_resume(struct device
*dev
)
417 struct spi_controller
*ctrl
= dev_get_drvdata(dev
);
418 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctrl
);
420 pinctrl_pm_select_default_state(dev
);
422 return clk_prepare_enable(aus
->clk
);
425 __maybe_unused
static int at91_usart_spi_suspend(struct device
*dev
)
427 struct spi_controller
*ctrl
= dev_get_drvdata(dev
);
430 ret
= spi_controller_suspend(ctrl
);
434 if (!pm_runtime_suspended(dev
))
435 at91_usart_spi_runtime_suspend(dev
);
440 __maybe_unused
static int at91_usart_spi_resume(struct device
*dev
)
442 struct spi_controller
*ctrl
= dev_get_drvdata(dev
);
443 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctrl
);
446 if (!pm_runtime_suspended(dev
)) {
447 ret
= at91_usart_spi_runtime_resume(dev
);
452 at91_usart_spi_init(aus
);
454 return spi_controller_resume(ctrl
);
457 static int at91_usart_spi_remove(struct platform_device
*pdev
)
459 struct spi_controller
*ctlr
= platform_get_drvdata(pdev
);
460 struct at91_usart_spi
*aus
= spi_master_get_devdata(ctlr
);
462 clk_disable_unprepare(aus
->clk
);
467 static const struct dev_pm_ops at91_usart_spi_pm_ops
= {
468 SET_SYSTEM_SLEEP_PM_OPS(at91_usart_spi_suspend
, at91_usart_spi_resume
)
469 SET_RUNTIME_PM_OPS(at91_usart_spi_runtime_suspend
,
470 at91_usart_spi_runtime_resume
, NULL
)
473 static const struct of_device_id at91_usart_spi_dt_ids
[] = {
474 { .compatible
= "microchip,at91sam9g45-usart-spi"},
478 MODULE_DEVICE_TABLE(of
, at91_usart_spi_dt_ids
);
480 static struct platform_driver at91_usart_spi_driver
= {
482 .name
= "at91_usart_spi",
483 .pm
= &at91_usart_spi_pm_ops
,
485 .probe
= at91_usart_spi_probe
,
486 .remove
= at91_usart_spi_remove
,
489 module_platform_driver(at91_usart_spi_driver
);
491 MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
492 MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
493 MODULE_LICENSE("GPL v2");
494 MODULE_ALIAS("platform:at91_usart_spi");